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path: root/drivers/gpu/drm/i915/intel_runtime_pm.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_runtime_pm.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index ff3fd8dbd2b4..1b10b7041513 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3848,13 +3848,14 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
3848 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 3848 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
3849 3849
3850 /* 3850 /*
3851 * In case of firmware assisted context save/restore don't manually 3851 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9
3852 * deinit the power domains. This also means the CSR/DMC firmware will 3852 * support don't manually deinit the power domains. This also means the
3853 * stay active, it will power down any HW resources as required and 3853 * CSR/DMC firmware will stay active, it will power down any HW
3854 * also enable deeper system power states that would be blocked if the 3854 * resources as required and also enable deeper system power states
3855 * firmware was inactive. 3855 * that would be blocked if the firmware was inactive.
3856 */ 3856 */
3857 if (!IS_GEN9_LP(dev_priv) && suspend_mode == I915_DRM_SUSPEND_IDLE && 3857 if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC9) &&
3858 suspend_mode == I915_DRM_SUSPEND_IDLE &&
3858 dev_priv->csr.dmc_payload != NULL) { 3859 dev_priv->csr.dmc_payload != NULL) {
3859 intel_power_domains_verify_state(dev_priv); 3860 intel_power_domains_verify_state(dev_priv);
3860 return; 3861 return;