1 files changed, 188 insertions, 231 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0a80e419b589..9f445e9a75d1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -589,14 +589,10 @@ static int init_ring_common(struct intel_engine_cs *ring)
                 goto out;
         }
 
-        if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
-                i915_kernel_lost_context(ring->dev);
-        else {
-                ringbuf->head = I915_READ_HEAD(ring);
-                ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
-                ringbuf->space = intel_ring_space(ringbuf);
-                ringbuf->last_retired_head = -1;
-        }
+        ringbuf->head = I915_READ_HEAD(ring);
+        ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
+        ringbuf->space = intel_ring_space(ringbuf);
+        ringbuf->last_retired_head = -1;
 
         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 
@@ -665,76 +661,112 @@ err:
         return ret;
 }
 
-static inline void intel_ring_emit_wa(struct intel_engine_cs *ring,
-                                       u32 addr, u32 value)
+static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
+                                       struct intel_context *ctx)
 {
+        int ret, i;
         struct drm_device *dev = ring->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
+        struct i915_workarounds *w = &dev_priv->workarounds;
 
-        if (WARN_ON(dev_priv->num_wa_regs >= I915_MAX_WA_REGS))
-                return;
+        if (WARN_ON(w->count == 0))
+                return 0;
 
-        intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
-        intel_ring_emit(ring, addr);
-        intel_ring_emit(ring, value);
+        ring->gpu_caches_dirty = true;
+        ret = intel_ring_flush_all_caches(ring);
+        if (ret)
+                return ret;
 
-        dev_priv->intel_wa_regs[dev_priv->num_wa_regs].addr = addr;
-        dev_priv->intel_wa_regs[dev_priv->num_wa_regs].mask = value & 0xFFFF;
-        /* value is updated with the status of remaining bits of this
-         * register when it is read from debugfs file
-         */
-        dev_priv->intel_wa_regs[dev_priv->num_wa_regs].value = value;
-        dev_priv->num_wa_regs++;
+        ret = intel_ring_begin(ring, (w->count * 2 + 2));
+        if (ret)
+                return ret;
+
+        intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
+        for (i = 0; i < w->count; i++) {
+                intel_ring_emit(ring, w->reg[i].addr);
+                intel_ring_emit(ring, w->reg[i].value);
+        }
+        intel_ring_emit(ring, MI_NOOP);
+
+        intel_ring_advance(ring);
 
-        return;
+        ring->gpu_caches_dirty = true;
+        ret = intel_ring_flush_all_caches(ring);
+        if (ret)
+                return ret;
+
+        DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
+
+        return 0;
 }
 
+static int wa_add(struct drm_i915_private *dev_priv,
+                  const u32 addr, const u32 mask, const u32 val)
+{
+        const u32 idx = dev_priv->workarounds.count;
+
+        if (WARN_ON(idx >= I915_MAX_WA_REGS))
+                return -ENOSPC;
+
+        dev_priv->workarounds.reg[idx].addr = addr;
+        dev_priv->workarounds.reg[idx].value = val;
+        dev_priv->workarounds.reg[idx].mask = mask;
+
+        dev_priv->workarounds.count++;
+
+        return 0;
+}
+
+#define WA_REG(addr, mask, val) { \
+                const int r = wa_add(dev_priv, (addr), (mask), (val)); \
+                if (r) \
+                        return r; \
+        }
+
+#define WA_SET_BIT_MASKED(addr, mask) \
+        WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
+
+#define WA_CLR_BIT_MASKED(addr, mask) \
+        WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
+
+#define WA_SET_FIELD_MASKED(addr, mask, value) \
+        WA_REG(addr, mask, _MASKED_FIELD(mask, value))
+
+#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
+#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
+
+#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
+
 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 {
-        int ret;
         struct drm_device *dev = ring->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
 
-        /*
-         * workarounds applied in this fn are part of register state context,
-         * they need to be re-initialized followed by gpu reset, suspend/resume,
-         * module reload.
-         */
-        dev_priv->num_wa_regs = 0;
-        memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
-
-        /*
-         * update the number of dwords required based on the
-         * actual number of workarounds applied
-         */
-        ret = intel_ring_begin(ring, 18);
-        if (ret)
-                return ret;
-
         /* WaDisablePartialInstShootdown:bdw */
-        /* WaDisableThreadStallDopClockGating:bdw */
-        /* FIXME: Unclear whether we really need this on production bdw. */
-        intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
-                           _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
-                                             | STALL_DOP_GATING_DISABLE));
+        /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
+        WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
+                          PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
+                          STALL_DOP_GATING_DISABLE);
 
-        /* WaDisableDopClockGating:bdw May not be needed for production */
-        intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
-                           _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+        /* WaDisableDopClockGating:bdw */
+        WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+                          DOP_CLOCK_GATING_DISABLE);
 
-        intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
-                           _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
+        WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
+                          GEN8_SAMPLER_POWER_BYPASS_DIS);
 
         /* Use Force Non-Coherent whenever executing a 3D context. This is a
          * workaround for for a possible hang in the unlikely event a TLB
          * invalidation occurs during a PSD flush.
          */
-        intel_ring_emit_wa(ring, HDC_CHICKEN0,
-                           _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
+        /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
+        WA_SET_BIT_MASKED(HDC_CHICKEN0,
+                          HDC_FORCE_NON_COHERENT |
+                          (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 
         /* Wa4x4STCOptimizationDisable:bdw */
-        intel_ring_emit_wa(ring, CACHE_MODE_1,
-                           _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
+        WA_SET_BIT_MASKED(CACHE_MODE_1,
+                          GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 
         /*
          * BSpec recommends 8x4 when MSAA is used,
@@ -744,52 +776,51 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
          * disable bit, which we don't touch here, but it's good
          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
          */
-        intel_ring_emit_wa(ring, GEN7_GT_MODE,
-                           GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
-
-        intel_ring_advance(ring);
-
-        DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
-                         dev_priv->num_wa_regs);
+        WA_SET_FIELD_MASKED(GEN7_GT_MODE,
+                            GEN6_WIZ_HASHING_MASK,
+                            GEN6_WIZ_HASHING_16x4);
 
         return 0;
 }
 
 static int chv_init_workarounds(struct intel_engine_cs *ring)
 {
-        int ret;
         struct drm_device *dev = ring->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
 
-        /*
-         * workarounds applied in this fn are part of register state context,
-         * they need to be re-initialized followed by gpu reset, suspend/resume,
-         * module reload.
+        /* WaDisablePartialInstShootdown:chv */
+        /* WaDisableThreadStallDopClockGating:chv */
+        WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
+                          PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
+                          STALL_DOP_GATING_DISABLE);
+
+        /* Use Force Non-Coherent whenever executing a 3D context. This is a
+         * workaround for a possible hang in the unlikely event a TLB
+         * invalidation occurs during a PSD flush.
          */
-        dev_priv->num_wa_regs = 0;
-        memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
+        /* WaForceEnableNonCoherent:chv */
+        /* WaHdcDisableFetchWhenMasked:chv */
+        WA_SET_BIT_MASKED(HDC_CHICKEN0,
+                          HDC_FORCE_NON_COHERENT |
+                          HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 
-        ret = intel_ring_begin(ring, 12);
-        if (ret)
-                return ret;
+        return 0;
+}
 
-        /* WaDisablePartialInstShootdown:chv */
-        intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
-                           _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
+int init_workarounds_ring(struct intel_engine_cs *ring)
+{
+        struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
 
-        /* WaDisableThreadStallDopClockGating:chv */
-        intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
-                           _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
+        WARN_ON(ring->id != RCS);
 
-        /* WaDisableDopClockGating:chv (pre-production hw) */
-        intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
-                           _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+        dev_priv->workarounds.count = 0;
 
-        /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
-        intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
-                           _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
+        if (IS_BROADWELL(dev))
+                return bdw_init_workarounds(ring);
 
-        intel_ring_advance(ring);
+        if (IS_CHERRYVIEW(dev))
+                return chv_init_workarounds(ring);
 
         return 0;
 }
@@ -812,7 +843,7 @@ static int init_render_ring(struct intel_engine_cs *ring)
          *
          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
          */
-        if (INTEL_INFO(dev)->gen >= 6)
+        if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 
         /* Required for the hardware to program scanline values for waiting */
@@ -849,7 +880,7 @@ static int init_render_ring(struct intel_engine_cs *ring)
         if (HAS_L3_DPF(dev))
                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 
-        return ret;
+        return init_workarounds_ring(ring);
 }
 
 static void render_ring_cleanup(struct intel_engine_cs *ring)
@@ -1186,7 +1217,7 @@ gen5_ring_get_irq(struct intel_engine_cs *ring)
         struct drm_i915_private *dev_priv = dev->dev_private;
         unsigned long flags;
 
-        if (!dev->irq_enabled)
+        if (WARN_ON(!intel_irqs_enabled(dev_priv)))
                 return false;
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1217,7 +1248,7 @@ i9xx_ring_get_irq(struct intel_engine_cs *ring)
         struct drm_i915_private *dev_priv = dev->dev_private;
         unsigned long flags;
 
-        if (!dev->irq_enabled)
+        if (!intel_irqs_enabled(dev_priv))
                 return false;
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1254,7 +1285,7 @@ i8xx_ring_get_irq(struct intel_engine_cs *ring)
         struct drm_i915_private *dev_priv = dev->dev_private;
         unsigned long flags;
 
-        if (!dev->irq_enabled)
+        if (!intel_irqs_enabled(dev_priv))
                 return false;
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1388,8 +1419,8 @@ gen6_ring_get_irq(struct intel_engine_cs *ring)
         struct drm_i915_private *dev_priv = dev->dev_private;
         unsigned long flags;
 
-        if (!dev->irq_enabled)
-               return false;
+        if (WARN_ON(!intel_irqs_enabled(dev_priv)))
+                return false;
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
         if (ring->irq_refcount++ == 0) {
@@ -1431,7 +1462,7 @@ hsw_vebox_get_irq(struct intel_engine_cs *ring)
         struct drm_i915_private *dev_priv = dev->dev_private;
         unsigned long flags;
 
-        if (!dev->irq_enabled)
+        if (WARN_ON(!intel_irqs_enabled(dev_priv)))
                 return false;
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1451,9 +1482,6 @@ hsw_vebox_put_irq(struct intel_engine_cs *ring)
         struct drm_i915_private *dev_priv = dev->dev_private;
         unsigned long flags;
 
-        if (!dev->irq_enabled)
-                return;
-
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
         if (--ring->irq_refcount == 0) {
                 I915_WRITE_IMR(ring, ~0);
@@ -1469,7 +1497,7 @@ gen8_ring_get_irq(struct intel_engine_cs *ring)
         struct drm_i915_private *dev_priv = dev->dev_private;
         unsigned long flags;
 
-        if (!dev->irq_enabled)
+        if (WARN_ON(!intel_irqs_enabled(dev_priv)))
                 return false;
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1694,13 +1722,42 @@ static int init_phys_status_page(struct intel_engine_cs *ring)
         return 0;
 }
 
-void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
+void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
 {
-        if (!ringbuf->obj)
-                return;
-
         iounmap(ringbuf->virtual_start);
+        ringbuf->virtual_start = NULL;
         i915_gem_object_ggtt_unpin(ringbuf->obj);
+}
+
+int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
+                                     struct intel_ringbuffer *ringbuf)
+{
+        struct drm_i915_private *dev_priv = to_i915(dev);
+        struct drm_i915_gem_object *obj = ringbuf->obj;
+        int ret;
+
+        ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
+        if (ret)
+                return ret;
+
+        ret = i915_gem_object_set_to_gtt_domain(obj, true);
+        if (ret) {
+                i915_gem_object_ggtt_unpin(obj);
+                return ret;
+        }
+
+        ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
+                        i915_gem_obj_ggtt_offset(obj), ringbuf->size);
+        if (ringbuf->virtual_start == NULL) {
+                i915_gem_object_ggtt_unpin(obj);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
+{
         drm_gem_object_unreference(&ringbuf->obj->base);
         ringbuf->obj = NULL;
 }
@@ -1708,12 +1765,7 @@ void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
                                struct intel_ringbuffer *ringbuf)
 {
-        struct drm_i915_private *dev_priv = to_i915(dev);
         struct drm_i915_gem_object *obj;
-        int ret;
-
-        if (ringbuf->obj)
-                return 0;
 
         obj = NULL;
         if (!HAS_LLC(dev))
@@ -1726,30 +1778,9 @@ int intel_alloc_ringbuffer_obj(struct drm_device *dev,
         /* mark ring buffers as read-only from GPU side by default */
         obj->gt_ro = 1;
 
-        ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
-        if (ret)
-                goto err_unref;
-
-        ret = i915_gem_object_set_to_gtt_domain(obj, true);
-        if (ret)
-                goto err_unpin;
-
-        ringbuf->virtual_start =
-                ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
-                                ringbuf->size);
-        if (ringbuf->virtual_start == NULL) {
-                ret = -EINVAL;
-                goto err_unpin;
-        }
-
         ringbuf->obj = obj;
-        return 0;
 
-err_unpin:
-        i915_gem_object_ggtt_unpin(obj);
-err_unref:
-        drm_gem_object_unreference(&obj->base);
-        return ret;
+        return 0;
 }
 
 static int intel_init_ring_buffer(struct drm_device *dev,
@@ -1786,10 +1817,21 @@ static int intel_init_ring_buffer(struct drm_device *dev,
                         goto error;
         }
 
-        ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
-        if (ret) {
-                DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
-                goto error;
+        if (ringbuf->obj == NULL) {
+                ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
+                if (ret) {
+                        DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
+                                        ring->name, ret);
+                        goto error;
+                }
+
+                ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
+                if (ret) {
+                        DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
+                                        ring->name, ret);
+                        intel_destroy_ringbuffer_obj(ringbuf);
+                        goto error;
+                }
         }
 
         /* Workaround an erratum on the i830 which causes a hang if
@@ -1818,15 +1860,19 @@ error:
 
 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
 {
-        struct drm_i915_private *dev_priv = to_i915(ring->dev);
-        struct intel_ringbuffer *ringbuf = ring->buffer;
+        struct drm_i915_private *dev_priv;
+        struct intel_ringbuffer *ringbuf;
 
         if (!intel_ring_initialized(ring))
                 return;
 
+        dev_priv = to_i915(ring->dev);
+        ringbuf = ring->buffer;
+
         intel_stop_ring_buffer(ring);
         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
 
+        intel_unpin_ringbuffer_obj(ringbuf);
         intel_destroy_ringbuffer_obj(ringbuf);
         ring->preallocated_lazy_request = NULL;
         ring->outstanding_lazy_seqno = 0;
@@ -1912,13 +1958,6 @@ static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
                         break;
                 }
 
-                if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
-                    dev->primary->master) {
-                        struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
-                        if (master_priv->sarea_priv)
-                                master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
-                }
-
                 msleep(1);
 
                 if (dev_priv->mm.interruptible && signal_pending(current)) {
@@ -2229,6 +2268,7 @@ static int gen6_ring_flush(struct intel_engine_cs *ring,
                            u32 invalidate, u32 flush)
 {
         struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
         uint32_t cmd;
         int ret;
 
@@ -2259,8 +2299,12 @@ static int gen6_ring_flush(struct intel_engine_cs *ring,
         }
         intel_ring_advance(ring);
 
-        if (IS_GEN7(dev) && !invalidate && flush)
-                return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
+        if (!invalidate && flush) {
+                if (IS_GEN7(dev))
+                        return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
+                else if (IS_BROADWELL(dev))
+                        dev_priv->fbc.need_sw_cache_clean = true;
+        }
 
         return 0;
 }
@@ -2293,10 +2337,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
                                         dev_priv->semaphore_obj = obj;
                         }
                 }
-                if (IS_CHERRYVIEW(dev))
-                        ring->init_context = chv_init_workarounds;
-                else
-                        ring->init_context = bdw_init_workarounds;
+
+                ring->init_context = intel_ring_workarounds_emit;
                 ring->add_request = gen6_add_request;
                 ring->flush = gen8_render_ring_flush;
                 ring->irq_get = gen8_ring_get_irq;
@@ -2406,91 +2448,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
         return intel_init_ring_buffer(dev, ring);
 }
 
-int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        struct intel_engine_cs *ring = &dev_priv->ring[RCS];
-        struct intel_ringbuffer *ringbuf = ring->buffer;
-        int ret;
-
-        if (ringbuf == NULL) {
-                ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
-                if (!ringbuf)
-                        return -ENOMEM;
-                ring->buffer = ringbuf;
-        }
-
-        ring->name = "render ring";
-        ring->id = RCS;
-        ring->mmio_base = RENDER_RING_BASE;
-
-        if (INTEL_INFO(dev)->gen >= 6) {
-                /* non-kms not supported on gen6+ */
-                ret = -ENODEV;
-                goto err_ringbuf;
-        }
-
-        /* Note: gem is not supported on gen5/ilk without kms (the corresponding
-         * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
-         * the special gen5 functions. */
-        ring->add_request = i9xx_add_request;
-        if (INTEL_INFO(dev)->gen < 4)
-                ring->flush = gen2_render_ring_flush;
-        else
-                ring->flush = gen4_render_ring_flush;
-        ring->get_seqno = ring_get_seqno;
-        ring->set_seqno = ring_set_seqno;
-        if (IS_GEN2(dev)) {
-                ring->irq_get = i8xx_ring_get_irq;
-                ring->irq_put = i8xx_ring_put_irq;
-        } else {
-                ring->irq_get = i9xx_ring_get_irq;
-                ring->irq_put = i9xx_ring_put_irq;
-        }
-        ring->irq_enable_mask = I915_USER_INTERRUPT;
-        ring->write_tail = ring_write_tail;
-        if (INTEL_INFO(dev)->gen >= 4)
-                ring->dispatch_execbuffer = i965_dispatch_execbuffer;
-        else if (IS_I830(dev) || IS_845G(dev))
-                ring->dispatch_execbuffer = i830_dispatch_execbuffer;
-        else
-                ring->dispatch_execbuffer = i915_dispatch_execbuffer;
-        ring->init = init_render_ring;
-        ring->cleanup = render_ring_cleanup;
-
-        ring->dev = dev;
-        INIT_LIST_HEAD(&ring->active_list);
-        INIT_LIST_HEAD(&ring->request_list);
-
-        ringbuf->size = size;
-        ringbuf->effective_size = ringbuf->size;
-        if (IS_I830(ring->dev) || IS_845G(ring->dev))
-                ringbuf->effective_size -= 2 * CACHELINE_BYTES;
-
-        ringbuf->virtual_start = ioremap_wc(start, size);
-        if (ringbuf->virtual_start == NULL) {
-                DRM_ERROR("can not ioremap virtual address for"
-                          " ring buffer\n");
-                ret = -ENOMEM;
-                goto err_ringbuf;
-        }
-
-        if (!I915_NEED_GFX_HWS(dev)) {
-                ret = init_phys_status_page(ring);
-                if (ret)
-                        goto err_vstart;
-        }
-
-        return 0;
-
-err_vstart:
-        iounmap(ringbuf->virtual_start);
-err_ringbuf:
-        kfree(ringbuf);
-        ring->buffer = NULL;
-        return ret;
-}
-
 int intel_init_bsd_ring_buffer(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;