1 files changed, 4 insertions, 4 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 02f6a9b81083..720c11e0acd1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -445,7 +445,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
         POSTING_READ(mmio);
 
         /* Flush the TLB for this page */
-        if (IS_GEN(dev_priv, 6, 7)) {
+        if (IS_GEN_RANGE(dev_priv, 6, 7)) {
                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 
                 /* ring should be idle before issuing a sync flush*/
@@ -679,7 +679,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
                 return ret;
 
         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
-        if (IS_GEN(dev_priv, 4, 6))
+        if (IS_GEN_RANGE(dev_priv, 4, 6))
                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 
         /* We need to disable the AsyncFlip performance optimisations in order
@@ -688,7 +688,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
          *
          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
          */
-        if (IS_GEN(dev_priv, 6, 7))
+        if (IS_GEN_RANGE(dev_priv, 6, 7))
                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 
         /* Required for the hardware to program scanline values for waiting */
@@ -713,7 +713,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
         }
 
-        if (IS_GEN(dev_priv, 6, 7))
+        if (IS_GEN_RANGE(dev_priv, 6, 7))
                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 
         if (INTEL_GEN(dev_priv) >= 6)