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path: root/drivers/gpu/drm/i915/intel_pm.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index adfeb7bb8874..c66af09e27a7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7825,7 +7825,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
7825 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a 7825 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7826 * requirement. 7826 * requirement.
7827 */ 7827 */
7828 if (!i915.enable_rc6) { 7828 if (!i915_modparams.enable_rc6) {
7829 DRM_INFO("RC6 disabled, disabling runtime PM support\n"); 7829 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7830 intel_runtime_pm_get(dev_priv); 7830 intel_runtime_pm_get(dev_priv);
7831 } 7831 }
@@ -7882,7 +7882,7 @@ void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
7882 if (IS_VALLEYVIEW(dev_priv)) 7882 if (IS_VALLEYVIEW(dev_priv))
7883 valleyview_cleanup_gt_powersave(dev_priv); 7883 valleyview_cleanup_gt_powersave(dev_priv);
7884 7884
7885 if (!i915.enable_rc6) 7885 if (!i915_modparams.enable_rc6)
7886 intel_runtime_pm_put(dev_priv); 7886 intel_runtime_pm_put(dev_priv);
7887} 7887}
7888 7888
@@ -8004,7 +8004,7 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
8004 if (IS_ERR(req)) 8004 if (IS_ERR(req))
8005 goto unlock; 8005 goto unlock;
8006 8006
8007 if (!i915.enable_execlists && i915_switch_context(req) == 0) 8007 if (!i915_modparams.enable_execlists && i915_switch_context(req) == 0)
8008 rcs->init_context(req); 8008 rcs->init_context(req);
8009 8009
8010 /* Mark the device busy, calling intel_enable_gt_powersave() */ 8010 /* Mark the device busy, calling intel_enable_gt_powersave() */