1 files changed, 61 insertions, 27 deletions
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 3c1482b8f2f4..927825f5b284 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -66,9 +66,10 @@ struct drm_i915_mocs_table {
 #define L3_WB                   3
 /* Target cache */
-#define ELLC                    0
+#define LE_TC_PAGETABLE         0
-#define LLC                     1
+#define LE_TC_LLC               1
-#define LLC_ELLC                2
+#define LE_TC_LLC_ELLC          2
+#define LE_TC_LLC_ELLC_ALT      3
 /*
 * MOCS tables
@@ -96,34 +97,67 @@ struct drm_i915_mocs_table {
 *       end.
 */
 static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
-        /* { 0x00000009, 0x0010 } */
+        { /* 0x00000009 */
-        { (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) |
+          .control_value = LE_CACHEABILITY(LE_UC) |
-           LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
+                           LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-          (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) },
+                           LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-        /* { 0x00000038, 0x0030 } */
+                           LE_PFM(0) | LE_SCF(0),
-        { (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
-           LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
+          /* 0x0010 */
-          (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) },
+          .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
-        /* { 0x0000003b, 0x0030 } */
+        },
-        { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
+        {
-           LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
+          /* 0x00000038 */
-          (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }
+          .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+                           LE_TGT_CACHE(LE_TC_LLC_ELLC) |
+                           LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+                           LE_PFM(0) | LE_SCF(0),
+          /* 0x0030 */
+          .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+        },
+        {
+          /* 0x0000003b */
+          .control_value = LE_CACHEABILITY(LE_WB) |
+                           LE_TGT_CACHE(LE_TC_LLC_ELLC) |
+                           LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+                           LE_PFM(0) | LE_SCF(0),
+          /* 0x0030 */
+          .l3cc_value =   L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+        },
 };
 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
-        /* { 0x00000009, 0x0010 } */
+        {
-        { (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) |
+          /* 0x00000009 */
-           LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
+          .control_value = LE_CACHEABILITY(LE_UC) |
-          (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) },
+                           LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-        /* { 0x00000038, 0x0030 } */
+                           LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-        { (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
+                           LE_PFM(0) | LE_SCF(0),
-           LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
-          (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) },
+          /* 0x0010 */
-        /* { 0x0000003b, 0x0030 } */
+          .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
-        { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
+        },
-           LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
+        {
-          (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }
+          /* 0x00000038 */
+          .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+                           LE_TGT_CACHE(LE_TC_LLC_ELLC) |
+                           LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+                           LE_PFM(0) | LE_SCF(0),
+          /* 0x0030 */
+          .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+        },
+        {
+          /* 0x00000039 */
+          .control_value = LE_CACHEABILITY(LE_UC) |
+                           LE_TGT_CACHE(LE_TC_LLC_ELLC) |
+                           LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+                           LE_PFM(0) | LE_SCF(0),
+          /* 0x0030 */
+          .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+        },
 };
 /**

diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 3c1482b8f2f4..927825f5b284 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -66,9 +66,10 @@ struct drm_i915_mocs_table {
66	#define L3_WB 3	66	#define L3_WB 3
67		67
68	/* Target cache */	68	/* Target cache */
69	#define ELLC 0	69	#define LE_TC_PAGETABLE 0
70	#define LLC 1	70	#define LE_TC_LLC 1
71	#define LLC_ELLC 2	71	#define LE_TC_LLC_ELLC 2
		72	#define LE_TC_LLC_ELLC_ALT 3
72		73
73	/*	74	/*
74	* MOCS tables	75	* MOCS tables
@@ -96,34 +97,67 @@ struct drm_i915_mocs_table {
96	* end.	97	* end.
97	*/	98	*/
98	static const struct drm_i915_mocs_entry skylake_mocs_table[] = {	99	static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
99	/* { 0x00000009, 0x0010 } */	100	{ /* 0x00000009 */
100	{ (LE_CACHEABILITY(LE_UC) \| LE_TGT_CACHE(LLC_ELLC) \| LE_LRUM(0) \|	101	.control_value = LE_CACHEABILITY(LE_UC) \|
101	LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \| LE_PFM(0) \| LE_SCF(0)),	102	LE_TGT_CACHE(LE_TC_LLC_ELLC) \|
102	(L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_UC)) },	103	LE_LRUM(0) \| LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \|
103	/* { 0x00000038, 0x0030 } */	104	LE_PFM(0) \| LE_SCF(0),
104	{ (LE_CACHEABILITY(LE_PAGETABLE) \| LE_TGT_CACHE(LLC_ELLC) \| LE_LRUM(3) \|	105
105	LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \| LE_PFM(0) \| LE_SCF(0)),	106	/* 0x0010 */
106	(L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_WB)) },	107	.l3cc_value = L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_UC),
107	/* { 0x0000003b, 0x0030 } */	108	},
108	{ (LE_CACHEABILITY(LE_WB) \| LE_TGT_CACHE(LLC_ELLC) \| LE_LRUM(3) \|	109	{
109	LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \| LE_PFM(0) \| LE_SCF(0)),	110	/* 0x00000038 */
110	(L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_WB)) }	111	.control_value = LE_CACHEABILITY(LE_PAGETABLE) \|
		112	LE_TGT_CACHE(LE_TC_LLC_ELLC) \|
		113	LE_LRUM(3) \| LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \|
		114	LE_PFM(0) \| LE_SCF(0),
		115	/* 0x0030 */
		116	.l3cc_value = L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_WB),
		117	},
		118	{
		119	/* 0x0000003b */
		120	.control_value = LE_CACHEABILITY(LE_WB) \|
		121	LE_TGT_CACHE(LE_TC_LLC_ELLC) \|
		122	LE_LRUM(3) \| LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \|
		123	LE_PFM(0) \| LE_SCF(0),
		124	/* 0x0030 */
		125	.l3cc_value = L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_WB),
		126	},
111	};	127	};
112		128
113	/* NOTE: the LE_TGT_CACHE is not used on Broxton */	129	/* NOTE: the LE_TGT_CACHE is not used on Broxton */
114	static const struct drm_i915_mocs_entry broxton_mocs_table[] = {	130	static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
115	/* { 0x00000009, 0x0010 } */	131	{
116	{ (LE_CACHEABILITY(LE_UC) \| LE_TGT_CACHE(LLC_ELLC) \| LE_LRUM(0) \|	132	/* 0x00000009 */
117	LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \| LE_PFM(0) \| LE_SCF(0)),	133	.control_value = LE_CACHEABILITY(LE_UC) \|
118	(L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_UC)) },	134	LE_TGT_CACHE(LE_TC_LLC_ELLC) \|
119	/* { 0x00000038, 0x0030 } */	135	LE_LRUM(0) \| LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \|
120	{ (LE_CACHEABILITY(LE_PAGETABLE) \| LE_TGT_CACHE(LLC_ELLC) \| LE_LRUM(3) \|	136	LE_PFM(0) \| LE_SCF(0),
121	LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \| LE_PFM(0) \| LE_SCF(0)),	137
122	(L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_WB)) },	138	/* 0x0010 */
123	/* { 0x0000003b, 0x0030 } */	139	.l3cc_value = L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_UC),
124	{ (LE_CACHEABILITY(LE_WB) \| LE_TGT_CACHE(LLC_ELLC) \| LE_LRUM(3) \|	140	},
125	LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \| LE_PFM(0) \| LE_SCF(0)),	141	{
126	(L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_WB)) }	142	/* 0x00000038 */
		143	.control_value = LE_CACHEABILITY(LE_PAGETABLE) \|
		144	LE_TGT_CACHE(LE_TC_LLC_ELLC) \|
		145	LE_LRUM(3) \| LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \|
		146	LE_PFM(0) \| LE_SCF(0),
		147
		148	/* 0x0030 */
		149	.l3cc_value = L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_WB),
		150	},
		151	{
		152	/* 0x00000039 */
		153	.control_value = LE_CACHEABILITY(LE_UC) \|
		154	LE_TGT_CACHE(LE_TC_LLC_ELLC) \|
		155	LE_LRUM(3) \| LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \|
		156	LE_PFM(0) \| LE_SCF(0),
		157
		158	/* 0x0030 */
		159	.l3cc_value = L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_WB),
		160	},
127	};	161	};
128		162
129	/**	163	/**