1 files changed, 15 insertions, 15 deletions

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 3bc6213afd3e..0668bbec5028 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -340,7 +340,7 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
         /* DSI uses short packets for sync events, so clear mode flags for DSI */
         adjusted_mode->flags = 0;
 
-        if (IS_BROXTON(dev_priv)) {
+        if (IS_GEN9_LP(dev_priv)) {
                 /* Dual link goes to DSI transcoder A. */
                 if (intel_dsi->ports == BIT(PORT_C))
                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
@@ -441,7 +441,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 
         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                 vlv_dsi_device_ready(encoder);
-        else if (IS_BROXTON(dev_priv))
+        else if (IS_GEN9_LP(dev_priv))
                 bxt_dsi_device_ready(encoder);
 }
 
@@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
         }
 
         for_each_dsi_port(port, intel_dsi->ports) {
-                i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+                i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
                 u32 temp;
 
@@ -497,7 +497,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
         enum port port;
 
         for_each_dsi_port(port, intel_dsi->ports) {
-                i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+                i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
                 u32 temp;
 
@@ -666,7 +666,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
         DRM_DEBUG_KMS("\n");
         for_each_dsi_port(port, intel_dsi->ports) {
                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
-                i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+                i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
                 u32 val;
 
@@ -758,12 +758,12 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
          * configuration, otherwise accessing DSI registers will hang the
          * machine. See BSpec North Display Engine registers/MIPI[BXT].
          */
-        if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
+        if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
                 goto out_put_power;
 
         /* XXX: this only works for one DSI output */
         for_each_dsi_port(port, intel_dsi->ports) {
-                i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
+                i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
                 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
 
@@ -788,7 +788,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
                         continue;
 
-                if (IS_BROXTON(dev_priv)) {
+                if (IS_GEN9_LP(dev_priv)) {
                         u32 tmp = I915_READ(MIPI_CTRL(port));
                         tmp &= BXT_PIPE_SELECT_MASK;
                         tmp >>= BXT_PIPE_SELECT_SHIFT;
@@ -976,7 +976,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
         u32 pclk;
         DRM_DEBUG_KMS("\n");
 
-        if (IS_BROXTON(dev_priv))
+        if (IS_GEN9_LP(dev_priv))
                 bxt_dsi_get_pipe_config(encoder, pipe_config);
 
         pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
@@ -1068,7 +1068,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 
         for_each_dsi_port(port, intel_dsi->ports) {
-                if (IS_BROXTON(dev_priv)) {
+                if (IS_GEN9_LP(dev_priv)) {
                         /*
                          * Program hdisplay and vdisplay on MIPI transcoder.
                          * This is different from calculated hactive and
@@ -1155,7 +1155,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
                         I915_WRITE(MIPI_CTRL(port), tmp |
                                         READ_REQUEST_PRIORITY_HIGH);
-                } else if (IS_BROXTON(dev_priv)) {
+                } else if (IS_GEN9_LP(dev_priv)) {
                         enum pipe pipe = intel_crtc->pipe;
 
                         tmp = I915_READ(MIPI_CTRL(port));
@@ -1193,7 +1193,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
         if (intel_dsi->clock_stop)
                 tmp |= CLOCKSTOP;
 
-        if (IS_BROXTON(dev_priv)) {
+        if (IS_GEN9_LP(dev_priv)) {
                 tmp |= BXT_DPHY_DEFEATURE_EN;
                 if (!is_cmd_mode(intel_dsi))
                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
@@ -1244,7 +1244,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
                 I915_WRITE(MIPI_INIT_COUNT(port),
                                 txclkesc(intel_dsi->escape_clk_div, 100));
 
-                if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
+                if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
                         /*
                          * BXT spec says write MIPI_INIT_COUNT for
                          * both the ports, even if only one is
@@ -1454,7 +1454,7 @@ void intel_dsi_init(struct drm_i915_private *dev_priv)
 
         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
-        } else if (IS_BROXTON(dev_priv)) {
+        } else if (IS_GEN9_LP(dev_priv)) {
                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
         } else {
                 DRM_ERROR("Unsupported Mipi device to reg base");
@@ -1495,7 +1495,7 @@ void intel_dsi_init(struct drm_i915_private *dev_priv)
          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
          * port C. BXT isn't limited like this.
          */
-        if (IS_BROXTON(dev_priv))
+        if (IS_GEN9_LP(dev_priv))
                 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
         else if (port == PORT_A)
                 intel_encoder->crtc_mask = BIT(PIPE_A);