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path: root/drivers/gpu/drm/i915/intel_drv.h
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_drv.h')
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h56
1 files changed, 33 insertions, 23 deletions
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6c7f8bca574e..bf8b057f72a6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -47,14 +47,11 @@
47 * contexts. Note that it's important that we check the condition again after 47 * contexts. Note that it's important that we check the condition again after
48 * having timed out, since the timeout could be due to preemption or similar and 48 * having timed out, since the timeout could be due to preemption or similar and
49 * we've never had a chance to check the condition before the timeout. 49 * we've never had a chance to check the condition before the timeout.
50 *
51 * TODO: When modesetting has fully transitioned to atomic, the below
52 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
53 * added.
54 */ 50 */
55#define _wait_for(COND, US, W) ({ \ 51#define _wait_for(COND, US, W) ({ \
56 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \ 52 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
57 int ret__; \ 53 int ret__; \
54 might_sleep(); \
58 for (;;) { \ 55 for (;;) { \
59 bool expired__ = time_after(jiffies, timeout__); \ 56 bool expired__ = time_after(jiffies, timeout__); \
60 if (COND) { \ 57 if (COND) { \
@@ -65,11 +62,7 @@
65 ret__ = -ETIMEDOUT; \ 62 ret__ = -ETIMEDOUT; \
66 break; \ 63 break; \
67 } \ 64 } \
68 if ((W) && drm_can_sleep()) { \ 65 usleep_range((W), (W) * 2); \
69 usleep_range((W), (W)*2); \
70 } else { \
71 cpu_relax(); \
72 } \
73 } \ 66 } \
74 ret__; \ 67 ret__; \
75}) 68})
@@ -173,7 +166,7 @@ enum intel_output_type {
173 INTEL_OUTPUT_DP = 7, 166 INTEL_OUTPUT_DP = 7,
174 INTEL_OUTPUT_EDP = 8, 167 INTEL_OUTPUT_EDP = 8,
175 INTEL_OUTPUT_DSI = 9, 168 INTEL_OUTPUT_DSI = 9,
176 INTEL_OUTPUT_UNKNOWN = 10, 169 INTEL_OUTPUT_DDI = 10,
177 INTEL_OUTPUT_DP_MST = 11, 170 INTEL_OUTPUT_DP_MST = 11,
178}; 171};
179 172
@@ -216,6 +209,9 @@ struct intel_encoder {
216 enum port port; 209 enum port port;
217 unsigned int cloneable; 210 unsigned int cloneable;
218 void (*hot_plug)(struct intel_encoder *); 211 void (*hot_plug)(struct intel_encoder *);
212 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
213 struct intel_crtc_state *,
214 struct drm_connector_state *);
219 bool (*compute_config)(struct intel_encoder *, 215 bool (*compute_config)(struct intel_encoder *,
220 struct intel_crtc_state *, 216 struct intel_crtc_state *,
221 struct drm_connector_state *); 217 struct drm_connector_state *);
@@ -386,6 +382,8 @@ struct intel_atomic_state {
386 unsigned int active_crtcs; 382 unsigned int active_crtcs;
387 /* minimum acceptable cdclk for each pipe */ 383 /* minimum acceptable cdclk for each pipe */
388 int min_cdclk[I915_MAX_PIPES]; 384 int min_cdclk[I915_MAX_PIPES];
385 /* minimum acceptable voltage level for each pipe */
386 u8 min_voltage_level[I915_MAX_PIPES];
389 387
390 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; 388 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
391 389
@@ -420,6 +418,9 @@ struct intel_plane_state {
420 /* plane control register */ 418 /* plane control register */
421 u32 ctl; 419 u32 ctl;
422 420
421 /* plane color control register */
422 u32 color_ctl;
423
423 /* 424 /*
424 * scaler_id 425 * scaler_id
425 * = -1 : not using a scaler 426 * = -1 : not using a scaler
@@ -738,6 +739,9 @@ struct intel_crtc_state {
738 */ 739 */
739 uint8_t lane_lat_optim_mask; 740 uint8_t lane_lat_optim_mask;
740 741
742 /* minimum acceptable voltage level */
743 u8 min_voltage_level;
744
741 /* Panel fitter controls for gen2-gen4 + VLV */ 745 /* Panel fitter controls for gen2-gen4 + VLV */
742 struct { 746 struct {
743 u32 control; 747 u32 control;
@@ -1048,7 +1052,6 @@ struct intel_lspcon {
1048 1052
1049struct intel_digital_port { 1053struct intel_digital_port {
1050 struct intel_encoder base; 1054 struct intel_encoder base;
1051 enum port port;
1052 u32 saved_port_bits; 1055 u32 saved_port_bits;
1053 struct intel_dp dp; 1056 struct intel_dp dp;
1054 struct intel_hdmi hdmi; 1057 struct intel_hdmi hdmi;
@@ -1080,7 +1083,7 @@ struct intel_dp_mst_encoder {
1080static inline enum dpio_channel 1083static inline enum dpio_channel
1081vlv_dport_to_channel(struct intel_digital_port *dport) 1084vlv_dport_to_channel(struct intel_digital_port *dport)
1082{ 1085{
1083 switch (dport->port) { 1086 switch (dport->base.port) {
1084 case PORT_B: 1087 case PORT_B:
1085 case PORT_D: 1088 case PORT_D:
1086 return DPIO_CH0; 1089 return DPIO_CH0;
@@ -1094,7 +1097,7 @@ vlv_dport_to_channel(struct intel_digital_port *dport)
1094static inline enum dpio_phy 1097static inline enum dpio_phy
1095vlv_dport_to_phy(struct intel_digital_port *dport) 1098vlv_dport_to_phy(struct intel_digital_port *dport)
1096{ 1099{
1097 switch (dport->port) { 1100 switch (dport->base.port) {
1098 case PORT_B: 1101 case PORT_B:
1099 case PORT_C: 1102 case PORT_C:
1100 return DPIO_PHY0; 1103 return DPIO_PHY0;
@@ -1147,7 +1150,7 @@ enc_to_dig_port(struct drm_encoder *encoder)
1147 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 1150 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1148 1151
1149 switch (intel_encoder->type) { 1152 switch (intel_encoder->type) {
1150 case INTEL_OUTPUT_UNKNOWN: 1153 case INTEL_OUTPUT_DDI:
1151 WARN_ON(!HAS_DDI(to_i915(encoder->dev))); 1154 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1152 case INTEL_OUTPUT_DP: 1155 case INTEL_OUTPUT_DP:
1153 case INTEL_OUTPUT_EDP: 1156 case INTEL_OUTPUT_EDP:
@@ -1271,7 +1274,6 @@ void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1271void hsw_fdi_link_train(struct intel_crtc *crtc, 1274void hsw_fdi_link_train(struct intel_crtc *crtc,
1272 const struct intel_crtc_state *crtc_state); 1275 const struct intel_crtc_state *crtc_state);
1273void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); 1276void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1274enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1275bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); 1277bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1276void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state); 1278void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1277void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 1279void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
@@ -1288,10 +1290,10 @@ bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1288void intel_ddi_get_config(struct intel_encoder *encoder, 1290void intel_ddi_get_config(struct intel_encoder *encoder,
1289 struct intel_crtc_state *pipe_config); 1291 struct intel_crtc_state *pipe_config);
1290 1292
1291void intel_ddi_clock_get(struct intel_encoder *encoder,
1292 struct intel_crtc_state *pipe_config);
1293void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, 1293void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1294 bool state); 1294 bool state);
1295void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1296 struct intel_crtc_state *crtc_state);
1295u32 bxt_signal_levels(struct intel_dp *intel_dp); 1297u32 bxt_signal_levels(struct intel_dp *intel_dp);
1296uint32_t ddi_signal_levels(struct intel_dp *intel_dp); 1298uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1297u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder); 1299u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
@@ -1304,7 +1306,9 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1304void intel_audio_codec_enable(struct intel_encoder *encoder, 1306void intel_audio_codec_enable(struct intel_encoder *encoder,
1305 const struct intel_crtc_state *crtc_state, 1307 const struct intel_crtc_state *crtc_state,
1306 const struct drm_connector_state *conn_state); 1308 const struct drm_connector_state *conn_state);
1307void intel_audio_codec_disable(struct intel_encoder *encoder); 1309void intel_audio_codec_disable(struct intel_encoder *encoder,
1310 const struct intel_crtc_state *old_crtc_state,
1311 const struct drm_connector_state *old_conn_state);
1308void i915_audio_component_init(struct drm_i915_private *dev_priv); 1312void i915_audio_component_init(struct drm_i915_private *dev_priv);
1309void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); 1313void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1310void intel_audio_init(struct drm_i915_private *dev_priv); 1314void intel_audio_init(struct drm_i915_private *dev_priv);
@@ -1322,10 +1326,14 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1322void intel_update_max_cdclk(struct drm_i915_private *dev_priv); 1326void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1323void intel_update_cdclk(struct drm_i915_private *dev_priv); 1327void intel_update_cdclk(struct drm_i915_private *dev_priv);
1324void intel_update_rawclk(struct drm_i915_private *dev_priv); 1328void intel_update_rawclk(struct drm_i915_private *dev_priv);
1325bool intel_cdclk_state_compare(const struct intel_cdclk_state *a, 1329bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1326 const struct intel_cdclk_state *b); 1330 const struct intel_cdclk_state *b);
1331bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1332 const struct intel_cdclk_state *b);
1327void intel_set_cdclk(struct drm_i915_private *dev_priv, 1333void intel_set_cdclk(struct drm_i915_private *dev_priv,
1328 const struct intel_cdclk_state *cdclk_state); 1334 const struct intel_cdclk_state *cdclk_state);
1335void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1336 const char *context);
1329 1337
1330/* intel_display.c */ 1338/* intel_display.c */
1331void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 1339void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
@@ -1477,8 +1485,8 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1477int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); 1485int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1478 1486
1479bool intel_crtc_active(struct intel_crtc *crtc); 1487bool intel_crtc_active(struct intel_crtc *crtc);
1480void hsw_enable_ips(struct intel_crtc *crtc); 1488void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1481void hsw_disable_ips(struct intel_crtc *crtc); 1489void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1482enum intel_display_power_domain intel_port_to_power_domain(enum port port); 1490enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1483void intel_mode_from_pipe_config(struct drm_display_mode *mode, 1491void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1484 struct intel_crtc_state *pipe_config); 1492 struct intel_crtc_state *pipe_config);
@@ -1491,6 +1499,8 @@ static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1491 return i915_ggtt_offset(state->vma); 1499 return i915_ggtt_offset(state->vma);
1492} 1500}
1493 1501
1502u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1503 const struct intel_plane_state *plane_state);
1494u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, 1504u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1495 const struct intel_plane_state *plane_state); 1505 const struct intel_plane_state *plane_state);
1496u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, 1506u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
@@ -1521,7 +1531,8 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1521void intel_dp_encoder_reset(struct drm_encoder *encoder); 1531void intel_dp_encoder_reset(struct drm_encoder *encoder);
1522void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); 1532void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1523void intel_dp_encoder_destroy(struct drm_encoder *encoder); 1533void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1524int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); 1534int intel_dp_sink_crc(struct intel_dp *intel_dp,
1535 struct intel_crtc_state *crtc_state, u8 *crc);
1525bool intel_dp_compute_config(struct intel_encoder *encoder, 1536bool intel_dp_compute_config(struct intel_encoder *encoder,
1526 struct intel_crtc_state *pipe_config, 1537 struct intel_crtc_state *pipe_config,
1527 struct drm_connector_state *conn_state); 1538 struct drm_connector_state *conn_state);
@@ -1868,7 +1879,6 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1868void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv); 1879void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1869void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv); 1880void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1870void intel_enable_gt_powersave(struct drm_i915_private *dev_priv); 1881void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1871void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1872void intel_disable_gt_powersave(struct drm_i915_private *dev_priv); 1882void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1873void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv); 1883void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1874void gen6_rps_busy(struct drm_i915_private *dev_priv); 1884void gen6_rps_busy(struct drm_i915_private *dev_priv);