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path: root/drivers/gpu/drm/i915/intel_dp.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c866
1 files changed, 615 insertions, 251 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 44fef5e1c490..4d0358fad937 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -27,6 +27,7 @@
27 27
28#include <linux/i2c.h> 28#include <linux/i2c.h>
29#include <linux/slab.h> 29#include <linux/slab.h>
30#include <linux/export.h>
30#include "drmP.h" 31#include "drmP.h"
31#include "drm.h" 32#include "drm.h"
32#include "drm_crtc.h" 33#include "drm_crtc.h"
@@ -36,7 +37,7 @@
36#include "i915_drv.h" 37#include "i915_drv.h"
37#include "drm_dp_helper.h" 38#include "drm_dp_helper.h"
38 39
39 40#define DP_RECEIVER_CAP_SIZE 0xf
40#define DP_LINK_STATUS_SIZE 6 41#define DP_LINK_STATUS_SIZE 6
41#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42 43
@@ -53,12 +54,19 @@ struct intel_dp {
53 int dpms_mode; 54 int dpms_mode;
54 uint8_t link_bw; 55 uint8_t link_bw;
55 uint8_t lane_count; 56 uint8_t lane_count;
56 uint8_t dpcd[8]; 57 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
57 struct i2c_adapter adapter; 58 struct i2c_adapter adapter;
58 struct i2c_algo_dp_aux_data algo; 59 struct i2c_algo_dp_aux_data algo;
59 bool is_pch_edp; 60 bool is_pch_edp;
60 uint8_t train_set[4]; 61 uint8_t train_set[4];
61 uint8_t link_status[DP_LINK_STATUS_SIZE]; 62 int panel_power_up_delay;
63 int panel_power_down_delay;
64 int panel_power_cycle_delay;
65 int backlight_on_delay;
66 int backlight_off_delay;
67 struct drm_display_mode *panel_fixed_mode; /* for eDP */
68 struct delayed_work panel_vdd_work;
69 bool want_panel_vdd;
62}; 70};
63 71
64/** 72/**
@@ -86,6 +94,17 @@ static bool is_pch_edp(struct intel_dp *intel_dp)
86 return intel_dp->is_pch_edp; 94 return intel_dp->is_pch_edp;
87} 95}
88 96
97/**
98 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
99 * @intel_dp: DP struct
100 *
101 * Returns true if the given DP struct corresponds to a CPU eDP port.
102 */
103static bool is_cpu_edp(struct intel_dp *intel_dp)
104{
105 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
106}
107
89static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 108static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
90{ 109{
91 return container_of(encoder, struct intel_dp, base.base); 110 return container_of(encoder, struct intel_dp, base.base);
@@ -121,7 +140,7 @@ static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
121static void intel_dp_link_down(struct intel_dp *intel_dp); 140static void intel_dp_link_down(struct intel_dp *intel_dp);
122 141
123void 142void
124intel_edp_link_config (struct intel_encoder *intel_encoder, 143intel_edp_link_config(struct intel_encoder *intel_encoder,
125 int *lane_num, int *link_bw) 144 int *lane_num, int *link_bw)
126{ 145{
127 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 146 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
@@ -136,16 +155,12 @@ intel_edp_link_config (struct intel_encoder *intel_encoder,
136static int 155static int
137intel_dp_max_lane_count(struct intel_dp *intel_dp) 156intel_dp_max_lane_count(struct intel_dp *intel_dp)
138{ 157{
139 int max_lane_count = 4; 158 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
140 159 switch (max_lane_count) {
141 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 160 case 1: case 2: case 4:
142 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; 161 break;
143 switch (max_lane_count) { 162 default:
144 case 1: case 2: case 4: 163 max_lane_count = 4;
145 break;
146 default:
147 max_lane_count = 4;
148 }
149 } 164 }
150 return max_lane_count; 165 return max_lane_count;
151} 166}
@@ -175,9 +190,25 @@ intel_dp_link_clock(uint8_t link_bw)
175 return 162000; 190 return 162000;
176} 191}
177 192
178/* I think this is a fiction */ 193/*
194 * The units on the numbers in the next two are... bizarre. Examples will
195 * make it clearer; this one parallels an example in the eDP spec.
196 *
197 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
198 *
199 * 270000 * 1 * 8 / 10 == 216000
200 *
201 * The actual data capacity of that configuration is 2.16Gbit/s, so the
202 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
203 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
204 * 119000. At 18bpp that's 2142000 kilobits per second.
205 *
206 * Thus the strange-looking division by 10 in intel_dp_link_required, to
207 * get the result in decakilobits instead of kilobits.
208 */
209
179static int 210static int
180intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) 211intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock)
181{ 212{
182 struct drm_crtc *crtc = intel_dp->base.base.crtc; 213 struct drm_crtc *crtc = intel_dp->base.base.crtc;
183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -186,7 +217,7 @@ intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pi
186 if (intel_crtc) 217 if (intel_crtc)
187 bpp = intel_crtc->bpp; 218 bpp = intel_crtc->bpp;
188 219
189 return (pixel_clock * bpp + 7) / 8; 220 return (pixel_clock * bpp + 9) / 10;
190} 221}
191 222
192static int 223static int
@@ -200,24 +231,19 @@ intel_dp_mode_valid(struct drm_connector *connector,
200 struct drm_display_mode *mode) 231 struct drm_display_mode *mode)
201{ 232{
202 struct intel_dp *intel_dp = intel_attached_dp(connector); 233 struct intel_dp *intel_dp = intel_attached_dp(connector);
203 struct drm_device *dev = connector->dev;
204 struct drm_i915_private *dev_priv = dev->dev_private;
205 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); 234 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
206 int max_lanes = intel_dp_max_lane_count(intel_dp); 235 int max_lanes = intel_dp_max_lane_count(intel_dp);
207 236
208 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { 237 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
209 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) 238 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
210 return MODE_PANEL; 239 return MODE_PANEL;
211 240
212 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) 241 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
213 return MODE_PANEL; 242 return MODE_PANEL;
214 } 243 }
215 244
216 /* only refuse the mode on non eDP since we have seen some weird eDP panels 245 if (intel_dp_link_required(intel_dp, mode->clock)
217 which are outside spec tolerances but somehow work by magic */ 246 > intel_dp_max_data_rate(max_link_clock, max_lanes))
218 if (!is_edp(intel_dp) &&
219 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
220 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
221 return MODE_CLOCK_HIGH; 247 return MODE_CLOCK_HIGH;
222 248
223 if (mode->clock < 10000) 249 if (mode->clock < 10000)
@@ -279,6 +305,38 @@ intel_hrawclk(struct drm_device *dev)
279 } 305 }
280} 306}
281 307
308static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
309{
310 struct drm_device *dev = intel_dp->base.base.dev;
311 struct drm_i915_private *dev_priv = dev->dev_private;
312
313 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
314}
315
316static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
317{
318 struct drm_device *dev = intel_dp->base.base.dev;
319 struct drm_i915_private *dev_priv = dev->dev_private;
320
321 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
322}
323
324static void
325intel_dp_check_edp(struct intel_dp *intel_dp)
326{
327 struct drm_device *dev = intel_dp->base.base.dev;
328 struct drm_i915_private *dev_priv = dev->dev_private;
329
330 if (!is_edp(intel_dp))
331 return;
332 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
333 WARN(1, "eDP powered off while attempting aux channel communication.\n");
334 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
335 I915_READ(PCH_PP_STATUS),
336 I915_READ(PCH_PP_CONTROL));
337 }
338}
339
282static int 340static int
283intel_dp_aux_ch(struct intel_dp *intel_dp, 341intel_dp_aux_ch(struct intel_dp *intel_dp,
284 uint8_t *send, int send_bytes, 342 uint8_t *send, int send_bytes,
@@ -295,6 +353,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
295 uint32_t aux_clock_divider; 353 uint32_t aux_clock_divider;
296 int try, precharge; 354 int try, precharge;
297 355
356 intel_dp_check_edp(intel_dp);
298 /* The clock divider is based off the hrawclk, 357 /* The clock divider is based off the hrawclk,
299 * and would like to run at 2MHz. So, take the 358 * and would like to run at 2MHz. So, take the
300 * hrawclk value and divide by 2 and use that 359 * hrawclk value and divide by 2 and use that
@@ -302,7 +361,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
302 * Note that PCH attached eDP panels should use a 125MHz input 361 * Note that PCH attached eDP panels should use a 125MHz input
303 * clock divider. 362 * clock divider.
304 */ 363 */
305 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { 364 if (is_cpu_edp(intel_dp)) {
306 if (IS_GEN6(dev)) 365 if (IS_GEN6(dev))
307 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ 366 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
308 else 367 else
@@ -337,7 +396,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
337 for (i = 0; i < send_bytes; i += 4) 396 for (i = 0; i < send_bytes; i += 4)
338 I915_WRITE(ch_data + i, 397 I915_WRITE(ch_data + i,
339 pack_aux(send + i, send_bytes - i)); 398 pack_aux(send + i, send_bytes - i));
340 399
341 /* Send the command and wait for it to complete */ 400 /* Send the command and wait for it to complete */
342 I915_WRITE(ch_ctl, 401 I915_WRITE(ch_ctl,
343 DP_AUX_CH_CTL_SEND_BUSY | 402 DP_AUX_CH_CTL_SEND_BUSY |
@@ -354,7 +413,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
354 break; 413 break;
355 udelay(100); 414 udelay(100);
356 } 415 }
357 416
358 /* Clear done status and any errors */ 417 /* Clear done status and any errors */
359 I915_WRITE(ch_ctl, 418 I915_WRITE(ch_ctl,
360 status | 419 status |
@@ -390,7 +449,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
390 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 449 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
391 if (recv_bytes > recv_size) 450 if (recv_bytes > recv_size)
392 recv_bytes = recv_size; 451 recv_bytes = recv_size;
393 452
394 for (i = 0; i < recv_bytes; i += 4) 453 for (i = 0; i < recv_bytes; i += 4)
395 unpack_aux(I915_READ(ch_data + i), 454 unpack_aux(I915_READ(ch_data + i),
396 recv + i, recv_bytes - i); 455 recv + i, recv_bytes - i);
@@ -408,6 +467,7 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
408 int msg_bytes; 467 int msg_bytes;
409 uint8_t ack; 468 uint8_t ack;
410 469
470 intel_dp_check_edp(intel_dp);
411 if (send_bytes > 16) 471 if (send_bytes > 16)
412 return -1; 472 return -1;
413 msg[0] = AUX_NATIVE_WRITE << 4; 473 msg[0] = AUX_NATIVE_WRITE << 4;
@@ -450,6 +510,7 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
450 uint8_t ack; 510 uint8_t ack;
451 int ret; 511 int ret;
452 512
513 intel_dp_check_edp(intel_dp);
453 msg[0] = AUX_NATIVE_READ << 4; 514 msg[0] = AUX_NATIVE_READ << 4;
454 msg[1] = address >> 8; 515 msg[1] = address >> 8;
455 msg[2] = address & 0xff; 516 msg[2] = address & 0xff;
@@ -493,6 +554,7 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
493 int reply_bytes; 554 int reply_bytes;
494 int ret; 555 int ret;
495 556
557 intel_dp_check_edp(intel_dp);
496 /* Set up the command byte */ 558 /* Set up the command byte */
497 if (mode & MODE_I2C_READ) 559 if (mode & MODE_I2C_READ)
498 msg[0] = AUX_I2C_READ << 4; 560 msg[0] = AUX_I2C_READ << 4;
@@ -573,24 +635,32 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
573 return -EREMOTEIO; 635 return -EREMOTEIO;
574} 636}
575 637
638static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
639static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
640
576static int 641static int
577intel_dp_i2c_init(struct intel_dp *intel_dp, 642intel_dp_i2c_init(struct intel_dp *intel_dp,
578 struct intel_connector *intel_connector, const char *name) 643 struct intel_connector *intel_connector, const char *name)
579{ 644{
645 int ret;
646
580 DRM_DEBUG_KMS("i2c_init %s\n", name); 647 DRM_DEBUG_KMS("i2c_init %s\n", name);
581 intel_dp->algo.running = false; 648 intel_dp->algo.running = false;
582 intel_dp->algo.address = 0; 649 intel_dp->algo.address = 0;
583 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; 650 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
584 651
585 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); 652 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
586 intel_dp->adapter.owner = THIS_MODULE; 653 intel_dp->adapter.owner = THIS_MODULE;
587 intel_dp->adapter.class = I2C_CLASS_DDC; 654 intel_dp->adapter.class = I2C_CLASS_DDC;
588 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 655 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
589 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 656 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
590 intel_dp->adapter.algo_data = &intel_dp->algo; 657 intel_dp->adapter.algo_data = &intel_dp->algo;
591 intel_dp->adapter.dev.parent = &intel_connector->base.kdev; 658 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
592 659
593 return i2c_dp_aux_add_bus(&intel_dp->adapter); 660 ironlake_edp_panel_vdd_on(intel_dp);
661 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
662 ironlake_edp_panel_vdd_off(intel_dp, false);
663 return ret;
594} 664}
595 665
596static bool 666static bool
@@ -598,29 +668,28 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
598 struct drm_display_mode *adjusted_mode) 668 struct drm_display_mode *adjusted_mode)
599{ 669{
600 struct drm_device *dev = encoder->dev; 670 struct drm_device *dev = encoder->dev;
601 struct drm_i915_private *dev_priv = dev->dev_private;
602 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 671 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
603 int lane_count, clock; 672 int lane_count, clock;
604 int max_lane_count = intel_dp_max_lane_count(intel_dp); 673 int max_lane_count = intel_dp_max_lane_count(intel_dp);
605 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 674 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
606 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 675 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
607 676
608 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { 677 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
609 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); 678 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
610 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, 679 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
611 mode, adjusted_mode); 680 mode, adjusted_mode);
612 /* 681 /*
613 * the mode->clock is used to calculate the Data&Link M/N 682 * the mode->clock is used to calculate the Data&Link M/N
614 * of the pipe. For the eDP the fixed clock should be used. 683 * of the pipe. For the eDP the fixed clock should be used.
615 */ 684 */
616 mode->clock = dev_priv->panel_fixed_mode->clock; 685 mode->clock = intel_dp->panel_fixed_mode->clock;
617 } 686 }
618 687
619 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 688 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
620 for (clock = 0; clock <= max_clock; clock++) { 689 for (clock = 0; clock <= max_clock; clock++) {
621 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 690 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
622 691
623 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) 692 if (intel_dp_link_required(intel_dp, mode->clock)
624 <= link_avail) { 693 <= link_avail) {
625 intel_dp->link_bw = bws[clock]; 694 intel_dp->link_bw = bws[clock];
626 intel_dp->lane_count = lane_count; 695 intel_dp->lane_count = lane_count;
@@ -634,19 +703,6 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
634 } 703 }
635 } 704 }
636 705
637 if (is_edp(intel_dp)) {
638 /* okay we failed just pick the highest */
639 intel_dp->lane_count = max_lane_count;
640 intel_dp->link_bw = bws[max_clock];
641 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
642 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
643 "count %d clock %d\n",
644 intel_dp->link_bw, intel_dp->lane_count,
645 adjusted_mode->clock);
646
647 return true;
648 }
649
650 return false; 706 return false;
651} 707}
652 708
@@ -706,12 +762,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
706 continue; 762 continue;
707 763
708 intel_dp = enc_to_intel_dp(encoder); 764 intel_dp = enc_to_intel_dp(encoder);
709 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { 765 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
766 intel_dp->base.type == INTEL_OUTPUT_EDP)
767 {
710 lane_count = intel_dp->lane_count; 768 lane_count = intel_dp->lane_count;
711 break; 769 break;
712 } else if (is_edp(intel_dp)) {
713 lane_count = dev_priv->edp.lanes;
714 break;
715 } 770 }
716 } 771 }
717 772
@@ -740,27 +795,52 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
740 } 795 }
741} 796}
742 797
798static void ironlake_edp_pll_on(struct drm_encoder *encoder);
799static void ironlake_edp_pll_off(struct drm_encoder *encoder);
800
743static void 801static void
744intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 802intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
745 struct drm_display_mode *adjusted_mode) 803 struct drm_display_mode *adjusted_mode)
746{ 804{
747 struct drm_device *dev = encoder->dev; 805 struct drm_device *dev = encoder->dev;
806 struct drm_i915_private *dev_priv = dev->dev_private;
748 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 807 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
749 struct drm_crtc *crtc = intel_dp->base.base.crtc; 808 struct drm_crtc *crtc = intel_dp->base.base.crtc;
750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
751 810
752 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 811 /* Turn on the eDP PLL if needed */
753 intel_dp->DP |= intel_dp->color_range; 812 if (is_edp(intel_dp)) {
813 if (!is_pch_edp(intel_dp))
814 ironlake_edp_pll_on(encoder);
815 else
816 ironlake_edp_pll_off(encoder);
817 }
754 818
755 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 819 /*
756 intel_dp->DP |= DP_SYNC_HS_HIGH; 820 * There are three kinds of DP registers:
757 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 821 *
758 intel_dp->DP |= DP_SYNC_VS_HIGH; 822 * IBX PCH
823 * CPU
824 * CPT PCH
825 *
826 * IBX PCH and CPU are the same for almost everything,
827 * except that the CPU DP PLL is configured in this
828 * register
829 *
830 * CPT PCH is quite different, having many bits moved
831 * to the TRANS_DP_CTL register instead. That
832 * configuration happens (oddly) in ironlake_pch_enable
833 */
759 834
760 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 835 /* Preserve the BIOS-computed detected bit. This is
761 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 836 * supposed to be read-only.
762 else 837 */
763 intel_dp->DP |= DP_LINK_TRAIN_OFF; 838 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
839 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
840
841 /* Handle DP bits in common between all three register formats */
842
843 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
764 844
765 switch (intel_dp->lane_count) { 845 switch (intel_dp->lane_count) {
766 case 1: 846 case 1:
@@ -773,135 +853,279 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
773 intel_dp->DP |= DP_PORT_WIDTH_4; 853 intel_dp->DP |= DP_PORT_WIDTH_4;
774 break; 854 break;
775 } 855 }
776 if (intel_dp->has_audio) 856 if (intel_dp->has_audio) {
857 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
858 pipe_name(intel_crtc->pipe));
777 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 859 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
778 860 intel_write_eld(encoder, adjusted_mode);
861 }
779 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 862 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
780 intel_dp->link_configuration[0] = intel_dp->link_bw; 863 intel_dp->link_configuration[0] = intel_dp->link_bw;
781 intel_dp->link_configuration[1] = intel_dp->lane_count; 864 intel_dp->link_configuration[1] = intel_dp->lane_count;
782 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; 865 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
783
784 /* 866 /*
785 * Check for DPCD version > 1.1 and enhanced framing support 867 * Check for DPCD version > 1.1 and enhanced framing support
786 */ 868 */
787 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 869 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
788 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { 870 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
789 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 871 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
790 intel_dp->DP |= DP_ENHANCED_FRAMING;
791 } 872 }
792 873
793 /* CPT DP's pipe select is decided in TRANS_DP_CTL */ 874 /* Split out the IBX/CPU vs CPT settings */
794 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
795 intel_dp->DP |= DP_PIPEB_SELECT;
796 875
797 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { 876 if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
798 /* don't miss out required setting for eDP */ 877 intel_dp->DP |= intel_dp->color_range;
799 intel_dp->DP |= DP_PLL_ENABLE; 878
800 if (adjusted_mode->clock < 200000) 879 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
801 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 880 intel_dp->DP |= DP_SYNC_HS_HIGH;
802 else 881 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
803 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 882 intel_dp->DP |= DP_SYNC_VS_HIGH;
883 intel_dp->DP |= DP_LINK_TRAIN_OFF;
884
885 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
886 intel_dp->DP |= DP_ENHANCED_FRAMING;
887
888 if (intel_crtc->pipe == 1)
889 intel_dp->DP |= DP_PIPEB_SELECT;
890
891 if (is_cpu_edp(intel_dp)) {
892 /* don't miss out required setting for eDP */
893 intel_dp->DP |= DP_PLL_ENABLE;
894 if (adjusted_mode->clock < 200000)
895 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
896 else
897 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
898 }
899 } else {
900 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
901 }
902}
903
904#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
905#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
906
907#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
908#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
909
910#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
911#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
912
913static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
914 u32 mask,
915 u32 value)
916{
917 struct drm_device *dev = intel_dp->base.base.dev;
918 struct drm_i915_private *dev_priv = dev->dev_private;
919
920 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
921 mask, value,
922 I915_READ(PCH_PP_STATUS),
923 I915_READ(PCH_PP_CONTROL));
924
925 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
926 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
927 I915_READ(PCH_PP_STATUS),
928 I915_READ(PCH_PP_CONTROL));
804 } 929 }
805} 930}
806 931
932static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
933{
934 DRM_DEBUG_KMS("Wait for panel power on\n");
935 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
936}
937
938static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
939{
940 DRM_DEBUG_KMS("Wait for panel power off time\n");
941 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
942}
943
944static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
945{
946 DRM_DEBUG_KMS("Wait for panel power cycle\n");
947 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
948}
949
950
951/* Read the current pp_control value, unlocking the register if it
952 * is locked
953 */
954
955static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
956{
957 u32 control = I915_READ(PCH_PP_CONTROL);
958
959 control &= ~PANEL_UNLOCK_MASK;
960 control |= PANEL_UNLOCK_REGS;
961 return control;
962}
963
807static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) 964static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
808{ 965{
809 struct drm_device *dev = intel_dp->base.base.dev; 966 struct drm_device *dev = intel_dp->base.base.dev;
810 struct drm_i915_private *dev_priv = dev->dev_private; 967 struct drm_i915_private *dev_priv = dev->dev_private;
811 u32 pp; 968 u32 pp;
812 969
813 /* 970 if (!is_edp(intel_dp))
814 * If the panel wasn't on, make sure there's not a currently 971 return;
815 * active PP sequence before enabling AUX VDD. 972 DRM_DEBUG_KMS("Turn eDP VDD on\n");
816 */ 973
817 if (!(I915_READ(PCH_PP_STATUS) & PP_ON)) 974 WARN(intel_dp->want_panel_vdd,
818 msleep(dev_priv->panel_t3); 975 "eDP VDD already requested on\n");
976
977 intel_dp->want_panel_vdd = true;
819 978
820 pp = I915_READ(PCH_PP_CONTROL); 979 if (ironlake_edp_have_panel_vdd(intel_dp)) {
980 DRM_DEBUG_KMS("eDP VDD already on\n");
981 return;
982 }
983
984 if (!ironlake_edp_have_panel_power(intel_dp))
985 ironlake_wait_panel_power_cycle(intel_dp);
986
987 pp = ironlake_get_pp_control(dev_priv);
821 pp |= EDP_FORCE_VDD; 988 pp |= EDP_FORCE_VDD;
822 I915_WRITE(PCH_PP_CONTROL, pp); 989 I915_WRITE(PCH_PP_CONTROL, pp);
823 POSTING_READ(PCH_PP_CONTROL); 990 POSTING_READ(PCH_PP_CONTROL);
991 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
992 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
993
994 /*
995 * If the panel wasn't on, delay before accessing aux channel
996 */
997 if (!ironlake_edp_have_panel_power(intel_dp)) {
998 DRM_DEBUG_KMS("eDP was not running\n");
999 msleep(intel_dp->panel_power_up_delay);
1000 }
824} 1001}
825 1002
826static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp) 1003static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
827{ 1004{
828 struct drm_device *dev = intel_dp->base.base.dev; 1005 struct drm_device *dev = intel_dp->base.base.dev;
829 struct drm_i915_private *dev_priv = dev->dev_private; 1006 struct drm_i915_private *dev_priv = dev->dev_private;
830 u32 pp; 1007 u32 pp;
831 1008
832 pp = I915_READ(PCH_PP_CONTROL); 1009 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
833 pp &= ~EDP_FORCE_VDD; 1010 pp = ironlake_get_pp_control(dev_priv);
834 I915_WRITE(PCH_PP_CONTROL, pp); 1011 pp &= ~EDP_FORCE_VDD;
835 POSTING_READ(PCH_PP_CONTROL); 1012 I915_WRITE(PCH_PP_CONTROL, pp);
1013 POSTING_READ(PCH_PP_CONTROL);
1014
1015 /* Make sure sequencer is idle before allowing subsequent activity */
1016 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1017 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1018
1019 msleep(intel_dp->panel_power_down_delay);
1020 }
1021}
1022
1023static void ironlake_panel_vdd_work(struct work_struct *__work)
1024{
1025 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1026 struct intel_dp, panel_vdd_work);
1027 struct drm_device *dev = intel_dp->base.base.dev;
1028
1029 mutex_lock(&dev->mode_config.mutex);
1030 ironlake_panel_vdd_off_sync(intel_dp);
1031 mutex_unlock(&dev->mode_config.mutex);
1032}
1033
1034static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1035{
1036 if (!is_edp(intel_dp))
1037 return;
1038
1039 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1040 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
836 1041
837 /* Make sure sequencer is idle before allowing subsequent activity */ 1042 intel_dp->want_panel_vdd = false;
838 msleep(dev_priv->panel_t12); 1043
1044 if (sync) {
1045 ironlake_panel_vdd_off_sync(intel_dp);
1046 } else {
1047 /*
1048 * Queue the timer to fire a long
1049 * time from now (relative to the power down delay)
1050 * to keep the panel power up across a sequence of operations
1051 */
1052 schedule_delayed_work(&intel_dp->panel_vdd_work,
1053 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1054 }
839} 1055}
840 1056
841/* Returns true if the panel was already on when called */ 1057static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
842static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
843{ 1058{
844 struct drm_device *dev = intel_dp->base.base.dev; 1059 struct drm_device *dev = intel_dp->base.base.dev;
845 struct drm_i915_private *dev_priv = dev->dev_private; 1060 struct drm_i915_private *dev_priv = dev->dev_private;
846 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; 1061 u32 pp;
847 1062
848 if (I915_READ(PCH_PP_STATUS) & PP_ON) 1063 if (!is_edp(intel_dp))
849 return true; 1064 return;
850 1065
851 pp = I915_READ(PCH_PP_CONTROL); 1066 DRM_DEBUG_KMS("Turn eDP power on\n");
852 1067
853 /* ILK workaround: disable reset around power sequence */ 1068 if (ironlake_edp_have_panel_power(intel_dp)) {
854 pp &= ~PANEL_POWER_RESET; 1069 DRM_DEBUG_KMS("eDP power already on\n");
855 I915_WRITE(PCH_PP_CONTROL, pp); 1070 return;
856 POSTING_READ(PCH_PP_CONTROL); 1071 }
857 1072
858 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; 1073 ironlake_wait_panel_power_cycle(intel_dp);
859 I915_WRITE(PCH_PP_CONTROL, pp);
860 POSTING_READ(PCH_PP_CONTROL);
861 1074
862 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, 1075 pp = ironlake_get_pp_control(dev_priv);
863 5000)) 1076 if (IS_GEN5(dev)) {
864 DRM_ERROR("panel on wait timed out: 0x%08x\n", 1077 /* ILK workaround: disable reset around power sequence */
865 I915_READ(PCH_PP_STATUS)); 1078 pp &= ~PANEL_POWER_RESET;
1079 I915_WRITE(PCH_PP_CONTROL, pp);
1080 POSTING_READ(PCH_PP_CONTROL);
1081 }
1082
1083 pp |= POWER_TARGET_ON;
1084 if (!IS_GEN5(dev))
1085 pp |= PANEL_POWER_RESET;
866 1086
867 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
868 I915_WRITE(PCH_PP_CONTROL, pp); 1087 I915_WRITE(PCH_PP_CONTROL, pp);
869 POSTING_READ(PCH_PP_CONTROL); 1088 POSTING_READ(PCH_PP_CONTROL);
870 1089
871 return false; 1090 ironlake_wait_panel_on(intel_dp);
1091
1092 if (IS_GEN5(dev)) {
1093 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1094 I915_WRITE(PCH_PP_CONTROL, pp);
1095 POSTING_READ(PCH_PP_CONTROL);
1096 }
872} 1097}
873 1098
874static void ironlake_edp_panel_off (struct drm_device *dev) 1099static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
875{ 1100{
1101 struct drm_device *dev = intel_dp->base.base.dev;
876 struct drm_i915_private *dev_priv = dev->dev_private; 1102 struct drm_i915_private *dev_priv = dev->dev_private;
877 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | 1103 u32 pp;
878 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
879
880 pp = I915_READ(PCH_PP_CONTROL);
881 1104
882 /* ILK workaround: disable reset around power sequence */ 1105 if (!is_edp(intel_dp))
883 pp &= ~PANEL_POWER_RESET; 1106 return;
884 I915_WRITE(PCH_PP_CONTROL, pp);
885 POSTING_READ(PCH_PP_CONTROL);
886 1107
887 pp &= ~POWER_TARGET_ON; 1108 DRM_DEBUG_KMS("Turn eDP power off\n");
888 I915_WRITE(PCH_PP_CONTROL, pp);
889 POSTING_READ(PCH_PP_CONTROL);
890 1109
891 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) 1110 WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
892 DRM_ERROR("panel off wait timed out: 0x%08x\n",
893 I915_READ(PCH_PP_STATUS));
894 1111
895 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1112 pp = ironlake_get_pp_control(dev_priv);
1113 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
896 I915_WRITE(PCH_PP_CONTROL, pp); 1114 I915_WRITE(PCH_PP_CONTROL, pp);
897 POSTING_READ(PCH_PP_CONTROL); 1115 POSTING_READ(PCH_PP_CONTROL);
1116
1117 ironlake_wait_panel_off(intel_dp);
898} 1118}
899 1119
900static void ironlake_edp_backlight_on (struct drm_device *dev) 1120static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
901{ 1121{
1122 struct drm_device *dev = intel_dp->base.base.dev;
902 struct drm_i915_private *dev_priv = dev->dev_private; 1123 struct drm_i915_private *dev_priv = dev->dev_private;
903 u32 pp; 1124 u32 pp;
904 1125
1126 if (!is_edp(intel_dp))
1127 return;
1128
905 DRM_DEBUG_KMS("\n"); 1129 DRM_DEBUG_KMS("\n");
906 /* 1130 /*
907 * If we enable the backlight right away following a panel power 1131 * If we enable the backlight right away following a panel power
@@ -909,21 +1133,28 @@ static void ironlake_edp_backlight_on (struct drm_device *dev)
909 * link. So delay a bit to make sure the image is solid before 1133 * link. So delay a bit to make sure the image is solid before
910 * allowing it to appear. 1134 * allowing it to appear.
911 */ 1135 */
912 msleep(300); 1136 msleep(intel_dp->backlight_on_delay);
913 pp = I915_READ(PCH_PP_CONTROL); 1137 pp = ironlake_get_pp_control(dev_priv);
914 pp |= EDP_BLC_ENABLE; 1138 pp |= EDP_BLC_ENABLE;
915 I915_WRITE(PCH_PP_CONTROL, pp); 1139 I915_WRITE(PCH_PP_CONTROL, pp);
1140 POSTING_READ(PCH_PP_CONTROL);
916} 1141}
917 1142
918static void ironlake_edp_backlight_off (struct drm_device *dev) 1143static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
919{ 1144{
1145 struct drm_device *dev = intel_dp->base.base.dev;
920 struct drm_i915_private *dev_priv = dev->dev_private; 1146 struct drm_i915_private *dev_priv = dev->dev_private;
921 u32 pp; 1147 u32 pp;
922 1148
1149 if (!is_edp(intel_dp))
1150 return;
1151
923 DRM_DEBUG_KMS("\n"); 1152 DRM_DEBUG_KMS("\n");
924 pp = I915_READ(PCH_PP_CONTROL); 1153 pp = ironlake_get_pp_control(dev_priv);
925 pp &= ~EDP_BLC_ENABLE; 1154 pp &= ~EDP_BLC_ENABLE;
926 I915_WRITE(PCH_PP_CONTROL, pp); 1155 I915_WRITE(PCH_PP_CONTROL, pp);
1156 POSTING_READ(PCH_PP_CONTROL);
1157 msleep(intel_dp->backlight_off_delay);
927} 1158}
928 1159
929static void ironlake_edp_pll_on(struct drm_encoder *encoder) 1160static void ironlake_edp_pll_on(struct drm_encoder *encoder)
@@ -986,43 +1217,39 @@ static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
986static void intel_dp_prepare(struct drm_encoder *encoder) 1217static void intel_dp_prepare(struct drm_encoder *encoder)
987{ 1218{
988 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1219 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
989 struct drm_device *dev = encoder->dev; 1220
1221 ironlake_edp_backlight_off(intel_dp);
1222 ironlake_edp_panel_off(intel_dp);
990 1223
991 /* Wake up the sink first */ 1224 /* Wake up the sink first */
1225 ironlake_edp_panel_vdd_on(intel_dp);
992 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1226 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
993
994 if (is_edp(intel_dp)) {
995 ironlake_edp_backlight_off(dev);
996 ironlake_edp_panel_off(dev);
997 if (!is_pch_edp(intel_dp))
998 ironlake_edp_pll_on(encoder);
999 else
1000 ironlake_edp_pll_off(encoder);
1001 }
1002 intel_dp_link_down(intel_dp); 1227 intel_dp_link_down(intel_dp);
1228 ironlake_edp_panel_vdd_off(intel_dp, false);
1229
1230 /* Make sure the panel is off before trying to
1231 * change the mode
1232 */
1003} 1233}
1004 1234
1005static void intel_dp_commit(struct drm_encoder *encoder) 1235static void intel_dp_commit(struct drm_encoder *encoder)
1006{ 1236{
1007 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1237 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1008 struct drm_device *dev = encoder->dev; 1238 struct drm_device *dev = encoder->dev;
1239 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1009 1240
1010 if (is_edp(intel_dp)) 1241 ironlake_edp_panel_vdd_on(intel_dp);
1011 ironlake_edp_panel_vdd_on(intel_dp); 1242 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1012
1013 intel_dp_start_link_train(intel_dp); 1243 intel_dp_start_link_train(intel_dp);
1014 1244 ironlake_edp_panel_on(intel_dp);
1015 if (is_edp(intel_dp)) { 1245 ironlake_edp_panel_vdd_off(intel_dp, true);
1016 ironlake_edp_panel_on(intel_dp);
1017 ironlake_edp_panel_vdd_off(intel_dp);
1018 }
1019
1020 intel_dp_complete_link_train(intel_dp); 1246 intel_dp_complete_link_train(intel_dp);
1021 1247 ironlake_edp_backlight_on(intel_dp);
1022 if (is_edp(intel_dp))
1023 ironlake_edp_backlight_on(dev);
1024 1248
1025 intel_dp->dpms_mode = DRM_MODE_DPMS_ON; 1249 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1250
1251 if (HAS_PCH_CPT(dev))
1252 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1026} 1253}
1027 1254
1028static void 1255static void
@@ -1034,28 +1261,30 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
1034 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1261 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1035 1262
1036 if (mode != DRM_MODE_DPMS_ON) { 1263 if (mode != DRM_MODE_DPMS_ON) {
1037 if (is_edp(intel_dp)) 1264 ironlake_edp_backlight_off(intel_dp);
1038 ironlake_edp_backlight_off(dev); 1265 ironlake_edp_panel_off(intel_dp);
1266
1267 ironlake_edp_panel_vdd_on(intel_dp);
1039 intel_dp_sink_dpms(intel_dp, mode); 1268 intel_dp_sink_dpms(intel_dp, mode);
1040 intel_dp_link_down(intel_dp); 1269 intel_dp_link_down(intel_dp);
1041 if (is_edp(intel_dp)) 1270 ironlake_edp_panel_vdd_off(intel_dp, false);
1042 ironlake_edp_panel_off(dev); 1271
1043 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) 1272 if (is_cpu_edp(intel_dp))
1044 ironlake_edp_pll_off(encoder); 1273 ironlake_edp_pll_off(encoder);
1045 } else { 1274 } else {
1046 if (is_edp(intel_dp)) 1275 if (is_cpu_edp(intel_dp))
1047 ironlake_edp_panel_vdd_on(intel_dp); 1276 ironlake_edp_pll_on(encoder);
1277
1278 ironlake_edp_panel_vdd_on(intel_dp);
1048 intel_dp_sink_dpms(intel_dp, mode); 1279 intel_dp_sink_dpms(intel_dp, mode);
1049 if (!(dp_reg & DP_PORT_EN)) { 1280 if (!(dp_reg & DP_PORT_EN)) {
1050 intel_dp_start_link_train(intel_dp); 1281 intel_dp_start_link_train(intel_dp);
1051 if (is_edp(intel_dp)) { 1282 ironlake_edp_panel_on(intel_dp);
1052 ironlake_edp_panel_on(intel_dp); 1283 ironlake_edp_panel_vdd_off(intel_dp, true);
1053 ironlake_edp_panel_vdd_off(intel_dp);
1054 }
1055 intel_dp_complete_link_train(intel_dp); 1284 intel_dp_complete_link_train(intel_dp);
1056 } 1285 } else
1057 if (is_edp(intel_dp)) 1286 ironlake_edp_panel_vdd_off(intel_dp, false);
1058 ironlake_edp_backlight_on(dev); 1287 ironlake_edp_backlight_on(intel_dp);
1059 } 1288 }
1060 intel_dp->dpms_mode = mode; 1289 intel_dp->dpms_mode = mode;
1061} 1290}
@@ -1090,11 +1319,11 @@ intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1090 * link status information 1319 * link status information
1091 */ 1320 */
1092static bool 1321static bool
1093intel_dp_get_link_status(struct intel_dp *intel_dp) 1322intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1094{ 1323{
1095 return intel_dp_aux_native_read_retry(intel_dp, 1324 return intel_dp_aux_native_read_retry(intel_dp,
1096 DP_LANE0_1_STATUS, 1325 DP_LANE0_1_STATUS,
1097 intel_dp->link_status, 1326 link_status,
1098 DP_LINK_STATUS_SIZE); 1327 DP_LINK_STATUS_SIZE);
1099} 1328}
1100 1329
@@ -1106,27 +1335,25 @@ intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1106} 1335}
1107 1336
1108static uint8_t 1337static uint8_t
1109intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], 1338intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1110 int lane) 1339 int lane)
1111{ 1340{
1112 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1113 int s = ((lane & 1) ? 1341 int s = ((lane & 1) ?
1114 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 1342 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1115 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 1343 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1116 uint8_t l = intel_dp_link_status(link_status, i); 1344 uint8_t l = adjust_request[lane>>1];
1117 1345
1118 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 1346 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1119} 1347}
1120 1348
1121static uint8_t 1349static uint8_t
1122intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], 1350intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1123 int lane) 1351 int lane)
1124{ 1352{
1125 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1126 int s = ((lane & 1) ? 1353 int s = ((lane & 1) ?
1127 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 1354 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1128 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 1355 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1129 uint8_t l = intel_dp_link_status(link_status, i); 1356 uint8_t l = adjust_request[lane>>1];
1130 1357
1131 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 1358 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1132} 1359}
@@ -1149,6 +1376,7 @@ static char *link_train_names[] = {
1149 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 1376 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1150 */ 1377 */
1151#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 1378#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1379#define I830_DP_VOLTAGE_MAX_CPT DP_TRAIN_VOLTAGE_SWING_1200
1152 1380
1153static uint8_t 1381static uint8_t
1154intel_dp_pre_emphasis_max(uint8_t voltage_swing) 1382intel_dp_pre_emphasis_max(uint8_t voltage_swing)
@@ -1167,15 +1395,18 @@ intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1167} 1395}
1168 1396
1169static void 1397static void
1170intel_get_adjust_train(struct intel_dp *intel_dp) 1398intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1171{ 1399{
1400 struct drm_device *dev = intel_dp->base.base.dev;
1172 uint8_t v = 0; 1401 uint8_t v = 0;
1173 uint8_t p = 0; 1402 uint8_t p = 0;
1174 int lane; 1403 int lane;
1404 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1405 int voltage_max;
1175 1406
1176 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1407 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1177 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); 1408 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1178 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); 1409 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1179 1410
1180 if (this_v > v) 1411 if (this_v > v)
1181 v = this_v; 1412 v = this_v;
@@ -1183,8 +1414,12 @@ intel_get_adjust_train(struct intel_dp *intel_dp)
1183 p = this_p; 1414 p = this_p;
1184 } 1415 }
1185 1416
1186 if (v >= I830_DP_VOLTAGE_MAX) 1417 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1187 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; 1418 voltage_max = I830_DP_VOLTAGE_MAX_CPT;
1419 else
1420 voltage_max = I830_DP_VOLTAGE_MAX;
1421 if (v >= voltage_max)
1422 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1188 1423
1189 if (p >= intel_dp_pre_emphasis_max(v)) 1424 if (p >= intel_dp_pre_emphasis_max(v))
1190 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1425 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
@@ -1194,7 +1429,7 @@ intel_get_adjust_train(struct intel_dp *intel_dp)
1194} 1429}
1195 1430
1196static uint32_t 1431static uint32_t
1197intel_dp_signal_levels(uint8_t train_set, int lane_count) 1432intel_dp_signal_levels(uint8_t train_set)
1198{ 1433{
1199 uint32_t signal_levels = 0; 1434 uint32_t signal_levels = 0;
1200 1435
@@ -1263,9 +1498,8 @@ static uint8_t
1263intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1498intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1264 int lane) 1499 int lane)
1265{ 1500{
1266 int i = DP_LANE0_1_STATUS + (lane >> 1);
1267 int s = (lane & 1) * 4; 1501 int s = (lane & 1) * 4;
1268 uint8_t l = intel_dp_link_status(link_status, i); 1502 uint8_t l = link_status[lane>>1];
1269 1503
1270 return (l >> s) & 0xf; 1504 return (l >> s) & 0xf;
1271} 1505}
@@ -1290,18 +1524,18 @@ intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count
1290 DP_LANE_CHANNEL_EQ_DONE|\ 1524 DP_LANE_CHANNEL_EQ_DONE|\
1291 DP_LANE_SYMBOL_LOCKED) 1525 DP_LANE_SYMBOL_LOCKED)
1292static bool 1526static bool
1293intel_channel_eq_ok(struct intel_dp *intel_dp) 1527intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1294{ 1528{
1295 uint8_t lane_align; 1529 uint8_t lane_align;
1296 uint8_t lane_status; 1530 uint8_t lane_status;
1297 int lane; 1531 int lane;
1298 1532
1299 lane_align = intel_dp_link_status(intel_dp->link_status, 1533 lane_align = intel_dp_link_status(link_status,
1300 DP_LANE_ALIGN_STATUS_UPDATED); 1534 DP_LANE_ALIGN_STATUS_UPDATED);
1301 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 1535 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1302 return false; 1536 return false;
1303 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1537 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1304 lane_status = intel_get_lane_status(intel_dp->link_status, lane); 1538 lane_status = intel_get_lane_status(link_status, lane);
1305 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) 1539 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1306 return false; 1540 return false;
1307 } 1541 }
@@ -1326,8 +1560,9 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
1326 1560
1327 ret = intel_dp_aux_native_write(intel_dp, 1561 ret = intel_dp_aux_native_write(intel_dp,
1328 DP_TRAINING_LANE0_SET, 1562 DP_TRAINING_LANE0_SET,
1329 intel_dp->train_set, 4); 1563 intel_dp->train_set,
1330 if (ret != 4) 1564 intel_dp->lane_count);
1565 if (ret != intel_dp->lane_count)
1331 return false; 1566 return false;
1332 1567
1333 return true; 1568 return true;
@@ -1343,7 +1578,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
1343 int i; 1578 int i;
1344 uint8_t voltage; 1579 uint8_t voltage;
1345 bool clock_recovery = false; 1580 bool clock_recovery = false;
1346 int tries; 1581 int voltage_tries, loop_tries;
1347 u32 reg; 1582 u32 reg;
1348 uint32_t DP = intel_dp->DP; 1583 uint32_t DP = intel_dp->DP;
1349 1584
@@ -1364,26 +1599,30 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
1364 DP_LINK_CONFIGURATION_SIZE); 1599 DP_LINK_CONFIGURATION_SIZE);
1365 1600
1366 DP |= DP_PORT_EN; 1601 DP |= DP_PORT_EN;
1367 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1602 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1368 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1603 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1369 else 1604 else
1370 DP &= ~DP_LINK_TRAIN_MASK; 1605 DP &= ~DP_LINK_TRAIN_MASK;
1371 memset(intel_dp->train_set, 0, 4); 1606 memset(intel_dp->train_set, 0, 4);
1372 voltage = 0xff; 1607 voltage = 0xff;
1373 tries = 0; 1608 voltage_tries = 0;
1609 loop_tries = 0;
1374 clock_recovery = false; 1610 clock_recovery = false;
1375 for (;;) { 1611 for (;;) {
1376 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1612 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1613 uint8_t link_status[DP_LINK_STATUS_SIZE];
1377 uint32_t signal_levels; 1614 uint32_t signal_levels;
1378 if (IS_GEN6(dev) && is_edp(intel_dp)) { 1615
1616 if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1379 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1617 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1380 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1618 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1381 } else { 1619 } else {
1382 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); 1620 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1621 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1383 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1622 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1384 } 1623 }
1385 1624
1386 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1625 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1387 reg = DP | DP_LINK_TRAIN_PAT_1_CPT; 1626 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1388 else 1627 else
1389 reg = DP | DP_LINK_TRAIN_PAT_1; 1628 reg = DP | DP_LINK_TRAIN_PAT_1;
@@ -1395,10 +1634,13 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
1395 /* Set training pattern 1 */ 1634 /* Set training pattern 1 */
1396 1635
1397 udelay(100); 1636 udelay(100);
1398 if (!intel_dp_get_link_status(intel_dp)) 1637 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1638 DRM_ERROR("failed to get link status\n");
1399 break; 1639 break;
1640 }
1400 1641
1401 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1642 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1643 DRM_DEBUG_KMS("clock recovery OK\n");
1402 clock_recovery = true; 1644 clock_recovery = true;
1403 break; 1645 break;
1404 } 1646 }
@@ -1407,20 +1649,30 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
1407 for (i = 0; i < intel_dp->lane_count; i++) 1649 for (i = 0; i < intel_dp->lane_count; i++)
1408 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1650 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1409 break; 1651 break;
1410 if (i == intel_dp->lane_count) 1652 if (i == intel_dp->lane_count) {
1411 break; 1653 ++loop_tries;
1654 if (loop_tries == 5) {
1655 DRM_DEBUG_KMS("too many full retries, give up\n");
1656 break;
1657 }
1658 memset(intel_dp->train_set, 0, 4);
1659 voltage_tries = 0;
1660 continue;
1661 }
1412 1662
1413 /* Check to see if we've tried the same voltage 5 times */ 1663 /* Check to see if we've tried the same voltage 5 times */
1414 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 1664 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1415 ++tries; 1665 ++voltage_tries;
1416 if (tries == 5) 1666 if (voltage_tries == 5) {
1667 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1417 break; 1668 break;
1669 }
1418 } else 1670 } else
1419 tries = 0; 1671 voltage_tries = 0;
1420 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1672 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1421 1673
1422 /* Compute new intel_dp->train_set as requested by target */ 1674 /* Compute new intel_dp->train_set as requested by target */
1423 intel_get_adjust_train(intel_dp); 1675 intel_get_adjust_train(intel_dp, link_status);
1424 } 1676 }
1425 1677
1426 intel_dp->DP = DP; 1678 intel_dp->DP = DP;
@@ -1443,6 +1695,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
1443 for (;;) { 1695 for (;;) {
1444 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1696 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1445 uint32_t signal_levels; 1697 uint32_t signal_levels;
1698 uint8_t link_status[DP_LINK_STATUS_SIZE];
1446 1699
1447 if (cr_tries > 5) { 1700 if (cr_tries > 5) {
1448 DRM_ERROR("failed to train DP, aborting\n"); 1701 DRM_ERROR("failed to train DP, aborting\n");
@@ -1450,15 +1703,15 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
1450 break; 1703 break;
1451 } 1704 }
1452 1705
1453 if (IS_GEN6(dev) && is_edp(intel_dp)) { 1706 if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1454 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1707 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1455 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1708 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1456 } else { 1709 } else {
1457 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); 1710 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1458 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1711 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1459 } 1712 }
1460 1713
1461 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1714 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1462 reg = DP | DP_LINK_TRAIN_PAT_2_CPT; 1715 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1463 else 1716 else
1464 reg = DP | DP_LINK_TRAIN_PAT_2; 1717 reg = DP | DP_LINK_TRAIN_PAT_2;
@@ -1470,17 +1723,17 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
1470 break; 1723 break;
1471 1724
1472 udelay(400); 1725 udelay(400);
1473 if (!intel_dp_get_link_status(intel_dp)) 1726 if (!intel_dp_get_link_status(intel_dp, link_status))
1474 break; 1727 break;
1475 1728
1476 /* Make sure clock is still ok */ 1729 /* Make sure clock is still ok */
1477 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1730 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1478 intel_dp_start_link_train(intel_dp); 1731 intel_dp_start_link_train(intel_dp);
1479 cr_tries++; 1732 cr_tries++;
1480 continue; 1733 continue;
1481 } 1734 }
1482 1735
1483 if (intel_channel_eq_ok(intel_dp)) { 1736 if (intel_channel_eq_ok(intel_dp, link_status)) {
1484 channel_eq = true; 1737 channel_eq = true;
1485 break; 1738 break;
1486 } 1739 }
@@ -1495,11 +1748,11 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
1495 } 1748 }
1496 1749
1497 /* Compute new intel_dp->train_set as requested by target */ 1750 /* Compute new intel_dp->train_set as requested by target */
1498 intel_get_adjust_train(intel_dp); 1751 intel_get_adjust_train(intel_dp, link_status);
1499 ++tries; 1752 ++tries;
1500 } 1753 }
1501 1754
1502 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1755 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1503 reg = DP | DP_LINK_TRAIN_OFF_CPT; 1756 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1504 else 1757 else
1505 reg = DP | DP_LINK_TRAIN_OFF; 1758 reg = DP | DP_LINK_TRAIN_OFF;
@@ -1529,7 +1782,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
1529 udelay(100); 1782 udelay(100);
1530 } 1783 }
1531 1784
1532 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) { 1785 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) {
1533 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1786 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1534 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 1787 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1535 } else { 1788 } else {
@@ -1540,8 +1793,12 @@ intel_dp_link_down(struct intel_dp *intel_dp)
1540 1793
1541 msleep(17); 1794 msleep(17);
1542 1795
1543 if (is_edp(intel_dp)) 1796 if (is_edp(intel_dp)) {
1544 DP |= DP_LINK_TRAIN_OFF; 1797 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1798 DP |= DP_LINK_TRAIN_OFF_CPT;
1799 else
1800 DP |= DP_LINK_TRAIN_OFF;
1801 }
1545 1802
1546 if (!HAS_PCH_CPT(dev) && 1803 if (!HAS_PCH_CPT(dev) &&
1547 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 1804 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
@@ -1578,13 +1835,14 @@ intel_dp_link_down(struct intel_dp *intel_dp)
1578 1835
1579 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 1836 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1580 POSTING_READ(intel_dp->output_reg); 1837 POSTING_READ(intel_dp->output_reg);
1838 msleep(intel_dp->panel_power_down_delay);
1581} 1839}
1582 1840
1583static bool 1841static bool
1584intel_dp_get_dpcd(struct intel_dp *intel_dp) 1842intel_dp_get_dpcd(struct intel_dp *intel_dp)
1585{ 1843{
1586 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, 1844 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1587 sizeof (intel_dp->dpcd)) && 1845 sizeof(intel_dp->dpcd)) &&
1588 (intel_dp->dpcd[DP_DPCD_REV] != 0)) { 1846 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1589 return true; 1847 return true;
1590 } 1848 }
@@ -1592,6 +1850,27 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
1592 return false; 1850 return false;
1593} 1851}
1594 1852
1853static bool
1854intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1855{
1856 int ret;
1857
1858 ret = intel_dp_aux_native_read_retry(intel_dp,
1859 DP_DEVICE_SERVICE_IRQ_VECTOR,
1860 sink_irq_vector, 1);
1861 if (!ret)
1862 return false;
1863
1864 return true;
1865}
1866
1867static void
1868intel_dp_handle_test_request(struct intel_dp *intel_dp)
1869{
1870 /* NAK by default */
1871 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1872}
1873
1595/* 1874/*
1596 * According to DP spec 1875 * According to DP spec
1597 * 5.1.2: 1876 * 5.1.2:
@@ -1604,6 +1883,9 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
1604static void 1883static void
1605intel_dp_check_link_status(struct intel_dp *intel_dp) 1884intel_dp_check_link_status(struct intel_dp *intel_dp)
1606{ 1885{
1886 u8 sink_irq_vector;
1887 u8 link_status[DP_LINK_STATUS_SIZE];
1888
1607 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON) 1889 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1608 return; 1890 return;
1609 1891
@@ -1611,7 +1893,7 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
1611 return; 1893 return;
1612 1894
1613 /* Try to read receiver status if the link appears to be up */ 1895 /* Try to read receiver status if the link appears to be up */
1614 if (!intel_dp_get_link_status(intel_dp)) { 1896 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1615 intel_dp_link_down(intel_dp); 1897 intel_dp_link_down(intel_dp);
1616 return; 1898 return;
1617 } 1899 }
@@ -1622,7 +1904,21 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
1622 return; 1904 return;
1623 } 1905 }
1624 1906
1625 if (!intel_channel_eq_ok(intel_dp)) { 1907 /* Try to read the source of the interrupt */
1908 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
1909 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
1910 /* Clear interrupt source */
1911 intel_dp_aux_native_write_1(intel_dp,
1912 DP_DEVICE_SERVICE_IRQ_VECTOR,
1913 sink_irq_vector);
1914
1915 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
1916 intel_dp_handle_test_request(intel_dp);
1917 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
1918 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
1919 }
1920
1921 if (!intel_channel_eq_ok(intel_dp, link_status)) {
1626 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 1922 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1627 drm_get_encoder_name(&intel_dp->base.base)); 1923 drm_get_encoder_name(&intel_dp->base.base));
1628 intel_dp_start_link_train(intel_dp); 1924 intel_dp_start_link_train(intel_dp);
@@ -1683,6 +1979,31 @@ g4x_dp_detect(struct intel_dp *intel_dp)
1683 return intel_dp_detect_dpcd(intel_dp); 1979 return intel_dp_detect_dpcd(intel_dp);
1684} 1980}
1685 1981
1982static struct edid *
1983intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
1984{
1985 struct intel_dp *intel_dp = intel_attached_dp(connector);
1986 struct edid *edid;
1987
1988 ironlake_edp_panel_vdd_on(intel_dp);
1989 edid = drm_get_edid(connector, adapter);
1990 ironlake_edp_panel_vdd_off(intel_dp, false);
1991 return edid;
1992}
1993
1994static int
1995intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
1996{
1997 struct intel_dp *intel_dp = intel_attached_dp(connector);
1998 int ret;
1999
2000 ironlake_edp_panel_vdd_on(intel_dp);
2001 ret = intel_ddc_get_modes(connector, adapter);
2002 ironlake_edp_panel_vdd_off(intel_dp, false);
2003 return ret;
2004}
2005
2006
1686/** 2007/**
1687 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. 2008 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1688 * 2009 *
@@ -1715,7 +2036,7 @@ intel_dp_detect(struct drm_connector *connector, bool force)
1715 if (intel_dp->force_audio) { 2036 if (intel_dp->force_audio) {
1716 intel_dp->has_audio = intel_dp->force_audio > 0; 2037 intel_dp->has_audio = intel_dp->force_audio > 0;
1717 } else { 2038 } else {
1718 edid = drm_get_edid(connector, &intel_dp->adapter); 2039 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1719 if (edid) { 2040 if (edid) {
1720 intel_dp->has_audio = drm_detect_monitor_audio(edid); 2041 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1721 connector->display_info.raw_edid = NULL; 2042 connector->display_info.raw_edid = NULL;
@@ -1736,28 +2057,36 @@ static int intel_dp_get_modes(struct drm_connector *connector)
1736 /* We should parse the EDID data and find out if it has an audio sink 2057 /* We should parse the EDID data and find out if it has an audio sink
1737 */ 2058 */
1738 2059
1739 ret = intel_ddc_get_modes(connector, &intel_dp->adapter); 2060 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
1740 if (ret) { 2061 if (ret) {
1741 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) { 2062 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
1742 struct drm_display_mode *newmode; 2063 struct drm_display_mode *newmode;
1743 list_for_each_entry(newmode, &connector->probed_modes, 2064 list_for_each_entry(newmode, &connector->probed_modes,
1744 head) { 2065 head) {
1745 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 2066 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
1746 dev_priv->panel_fixed_mode = 2067 intel_dp->panel_fixed_mode =
1747 drm_mode_duplicate(dev, newmode); 2068 drm_mode_duplicate(dev, newmode);
1748 break; 2069 break;
1749 } 2070 }
1750 } 2071 }
1751 } 2072 }
1752
1753 return ret; 2073 return ret;
1754 } 2074 }
1755 2075
1756 /* if eDP has no EDID, try to use fixed panel mode from VBT */ 2076 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1757 if (is_edp(intel_dp)) { 2077 if (is_edp(intel_dp)) {
1758 if (dev_priv->panel_fixed_mode != NULL) { 2078 /* initialize panel mode from VBT if available for eDP */
2079 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2080 intel_dp->panel_fixed_mode =
2081 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2082 if (intel_dp->panel_fixed_mode) {
2083 intel_dp->panel_fixed_mode->type |=
2084 DRM_MODE_TYPE_PREFERRED;
2085 }
2086 }
2087 if (intel_dp->panel_fixed_mode) {
1759 struct drm_display_mode *mode; 2088 struct drm_display_mode *mode;
1760 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); 2089 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
1761 drm_mode_probed_add(connector, mode); 2090 drm_mode_probed_add(connector, mode);
1762 return 1; 2091 return 1;
1763 } 2092 }
@@ -1772,7 +2101,7 @@ intel_dp_detect_audio(struct drm_connector *connector)
1772 struct edid *edid; 2101 struct edid *edid;
1773 bool has_audio = false; 2102 bool has_audio = false;
1774 2103
1775 edid = drm_get_edid(connector, &intel_dp->adapter); 2104 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1776 if (edid) { 2105 if (edid) {
1777 has_audio = drm_detect_monitor_audio(edid); 2106 has_audio = drm_detect_monitor_audio(edid);
1778 2107
@@ -1839,7 +2168,7 @@ done:
1839} 2168}
1840 2169
1841static void 2170static void
1842intel_dp_destroy (struct drm_connector *connector) 2171intel_dp_destroy(struct drm_connector *connector)
1843{ 2172{
1844 struct drm_device *dev = connector->dev; 2173 struct drm_device *dev = connector->dev;
1845 2174
@@ -1857,6 +2186,10 @@ static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1857 2186
1858 i2c_del_adapter(&intel_dp->adapter); 2187 i2c_del_adapter(&intel_dp->adapter);
1859 drm_encoder_cleanup(encoder); 2188 drm_encoder_cleanup(encoder);
2189 if (is_edp(intel_dp)) {
2190 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2191 ironlake_panel_vdd_off_sync(intel_dp);
2192 }
1860 kfree(intel_dp); 2193 kfree(intel_dp);
1861} 2194}
1862 2195
@@ -1896,7 +2229,7 @@ intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1896 2229
1897/* Return which DP Port should be selected for Transcoder DP control */ 2230/* Return which DP Port should be selected for Transcoder DP control */
1898int 2231int
1899intel_trans_dp_port_sel (struct drm_crtc *crtc) 2232intel_trans_dp_port_sel(struct drm_crtc *crtc)
1900{ 2233{
1901 struct drm_device *dev = crtc->dev; 2234 struct drm_device *dev = crtc->dev;
1902 struct drm_mode_config *mode_config = &dev->mode_config; 2235 struct drm_mode_config *mode_config = &dev->mode_config;
@@ -1909,7 +2242,8 @@ intel_trans_dp_port_sel (struct drm_crtc *crtc)
1909 continue; 2242 continue;
1910 2243
1911 intel_dp = enc_to_intel_dp(encoder); 2244 intel_dp = enc_to_intel_dp(encoder);
1912 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) 2245 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2246 intel_dp->base.type == INTEL_OUTPUT_EDP)
1913 return intel_dp->output_reg; 2247 return intel_dp->output_reg;
1914 } 2248 }
1915 2249
@@ -1993,10 +2327,13 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1993 else if (output_reg == DP_D || output_reg == PCH_DP_D) 2327 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1994 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); 2328 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1995 2329
1996 if (is_edp(intel_dp)) 2330 if (is_edp(intel_dp)) {
1997 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); 2331 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2332 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2333 ironlake_panel_vdd_work);
2334 }
1998 2335
1999 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 2336 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2000 connector->interlace_allowed = true; 2337 connector->interlace_allowed = true;
2001 connector->doublescan_allowed = 0; 2338 connector->doublescan_allowed = 0;
2002 2339
@@ -2032,25 +2369,59 @@ intel_dp_init(struct drm_device *dev, int output_reg)
2032 break; 2369 break;
2033 } 2370 }
2034 2371
2035 intel_dp_i2c_init(intel_dp, intel_connector, name);
2036
2037 /* Cache some DPCD data in the eDP case */ 2372 /* Cache some DPCD data in the eDP case */
2038 if (is_edp(intel_dp)) { 2373 if (is_edp(intel_dp)) {
2039 bool ret; 2374 bool ret;
2040 u32 pp_on, pp_div; 2375 struct edp_power_seq cur, vbt;
2376 u32 pp_on, pp_off, pp_div;
2041 2377
2042 pp_on = I915_READ(PCH_PP_ON_DELAYS); 2378 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2379 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2043 pp_div = I915_READ(PCH_PP_DIVISOR); 2380 pp_div = I915_READ(PCH_PP_DIVISOR);
2044 2381
2045 /* Get T3 & T12 values (note: VESA not bspec terminology) */ 2382 /* Pull timing values out of registers */
2046 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16; 2383 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2047 dev_priv->panel_t3 /= 10; /* t3 in 100us units */ 2384 PANEL_POWER_UP_DELAY_SHIFT;
2048 dev_priv->panel_t12 = pp_div & 0xf; 2385
2049 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */ 2386 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2387 PANEL_LIGHT_ON_DELAY_SHIFT;
2388
2389 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2390 PANEL_LIGHT_OFF_DELAY_SHIFT;
2391
2392 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2393 PANEL_POWER_DOWN_DELAY_SHIFT;
2394
2395 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2396 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2397
2398 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2399 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2400
2401 vbt = dev_priv->edp.pps;
2402
2403 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2404 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2405
2406#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2407
2408 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2409 intel_dp->backlight_on_delay = get_delay(t8);
2410 intel_dp->backlight_off_delay = get_delay(t9);
2411 intel_dp->panel_power_down_delay = get_delay(t10);
2412 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2413
2414 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2415 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2416 intel_dp->panel_power_cycle_delay);
2417
2418 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2419 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2050 2420
2051 ironlake_edp_panel_vdd_on(intel_dp); 2421 ironlake_edp_panel_vdd_on(intel_dp);
2052 ret = intel_dp_get_dpcd(intel_dp); 2422 ret = intel_dp_get_dpcd(intel_dp);
2053 ironlake_edp_panel_vdd_off(intel_dp); 2423 ironlake_edp_panel_vdd_off(intel_dp, false);
2424
2054 if (ret) { 2425 if (ret) {
2055 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 2426 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2056 dev_priv->no_aux_handshake = 2427 dev_priv->no_aux_handshake =
@@ -2065,18 +2436,11 @@ intel_dp_init(struct drm_device *dev, int output_reg)
2065 } 2436 }
2066 } 2437 }
2067 2438
2439 intel_dp_i2c_init(intel_dp, intel_connector, name);
2440
2068 intel_encoder->hot_plug = intel_dp_hot_plug; 2441 intel_encoder->hot_plug = intel_dp_hot_plug;
2069 2442
2070 if (is_edp(intel_dp)) { 2443 if (is_edp(intel_dp)) {
2071 /* initialize panel mode from VBT if available for eDP */
2072 if (dev_priv->lfp_lvds_vbt_mode) {
2073 dev_priv->panel_fixed_mode =
2074 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2075 if (dev_priv->panel_fixed_mode) {
2076 dev_priv->panel_fixed_mode->type |=
2077 DRM_MODE_TYPE_PREFERRED;
2078 }
2079 }
2080 dev_priv->int_edp_connector = connector; 2444 dev_priv->int_edp_connector = connector;
2081 intel_panel_setup_backlight(dev); 2445 intel_panel_setup_backlight(dev);
2082 } 2446 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-11 02:13:16 -0400