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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c775
1 files changed, 350 insertions, 425 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0b2cd669ac05..be3b2cab2640 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -530,52 +530,6 @@ needs_modeset(struct drm_crtc_state *state)
530 return drm_atomic_crtc_needs_modeset(state); 530 return drm_atomic_crtc_needs_modeset(state);
531} 531}
532 532
533/**
534 * Returns whether any output on the specified pipe is of the specified type
535 */
536bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
537{
538 struct drm_device *dev = crtc->base.dev;
539 struct intel_encoder *encoder;
540
541 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
542 if (encoder->type == type)
543 return true;
544
545 return false;
546}
547
548/**
549 * Returns whether any output on the specified pipe will have the specified
550 * type after a staged modeset is complete, i.e., the same as
551 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
552 * encoder->crtc.
553 */
554static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
555 int type)
556{
557 struct drm_atomic_state *state = crtc_state->base.state;
558 struct drm_connector *connector;
559 struct drm_connector_state *connector_state;
560 struct intel_encoder *encoder;
561 int i, num_connectors = 0;
562
563 for_each_connector_in_state(state, connector, connector_state, i) {
564 if (connector_state->crtc != crtc_state->base.crtc)
565 continue;
566
567 num_connectors++;
568
569 encoder = to_intel_encoder(connector_state->best_encoder);
570 if (encoder->type == type)
571 return true;
572 }
573
574 WARN_ON(num_connectors == 0);
575
576 return false;
577}
578
579/* 533/*
580 * Platform specific helpers to calculate the port PLL loopback- (clock.m), 534 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
581 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast 535 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
@@ -688,7 +642,7 @@ i9xx_select_p2_div(const struct intel_limit *limit,
688{ 642{
689 struct drm_device *dev = crtc_state->base.crtc->dev; 643 struct drm_device *dev = crtc_state->base.crtc->dev;
690 644
691 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { 645 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
692 /* 646 /*
693 * For LVDS just rely on its current settings for dual-channel. 647 * For LVDS just rely on its current settings for dual-channel.
694 * We haven't figured out how to reliably set up different 648 * We haven't figured out how to reliably set up different
@@ -1080,7 +1034,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1080 1034
1081static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) 1035static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1082{ 1036{
1083 struct drm_i915_private *dev_priv = dev->dev_private; 1037 struct drm_i915_private *dev_priv = to_i915(dev);
1084 i915_reg_t reg = PIPEDSL(pipe); 1038 i915_reg_t reg = PIPEDSL(pipe);
1085 u32 line1, line2; 1039 u32 line1, line2;
1086 u32 line_mask; 1040 u32 line_mask;
@@ -1116,7 +1070,7 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1116static void intel_wait_for_pipe_off(struct intel_crtc *crtc) 1070static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1117{ 1071{
1118 struct drm_device *dev = crtc->base.dev; 1072 struct drm_device *dev = crtc->base.dev;
1119 struct drm_i915_private *dev_priv = dev->dev_private; 1073 struct drm_i915_private *dev_priv = to_i915(dev);
1120 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; 1074 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1121 enum pipe pipe = crtc->pipe; 1075 enum pipe pipe = crtc->pipe;
1122 1076
@@ -1124,8 +1078,9 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1124 i915_reg_t reg = PIPECONF(cpu_transcoder); 1078 i915_reg_t reg = PIPECONF(cpu_transcoder);
1125 1079
1126 /* Wait for the Pipe State to go off */ 1080 /* Wait for the Pipe State to go off */
1127 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 1081 if (intel_wait_for_register(dev_priv,
1128 100)) 1082 reg, I965_PIPECONF_ACTIVE, 0,
1083 100))
1129 WARN(1, "pipe_off wait timed out\n"); 1084 WARN(1, "pipe_off wait timed out\n");
1130 } else { 1085 } else {
1131 /* Wait for the display line to settle */ 1086 /* Wait for the display line to settle */
@@ -1234,7 +1189,7 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1234void assert_panel_unlocked(struct drm_i915_private *dev_priv, 1189void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1235 enum pipe pipe) 1190 enum pipe pipe)
1236{ 1191{
1237 struct drm_device *dev = dev_priv->dev; 1192 struct drm_device *dev = &dev_priv->drm;
1238 i915_reg_t pp_reg; 1193 i915_reg_t pp_reg;
1239 u32 val; 1194 u32 val;
1240 enum pipe panel_pipe = PIPE_A; 1195 enum pipe panel_pipe = PIPE_A;
@@ -1276,7 +1231,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1276static void assert_cursor(struct drm_i915_private *dev_priv, 1231static void assert_cursor(struct drm_i915_private *dev_priv,
1277 enum pipe pipe, bool state) 1232 enum pipe pipe, bool state)
1278{ 1233{
1279 struct drm_device *dev = dev_priv->dev; 1234 struct drm_device *dev = &dev_priv->drm;
1280 bool cur_state; 1235 bool cur_state;
1281 1236
1282 if (IS_845G(dev) || IS_I865G(dev)) 1237 if (IS_845G(dev) || IS_I865G(dev))
@@ -1338,7 +1293,7 @@ static void assert_plane(struct drm_i915_private *dev_priv,
1338static void assert_planes_disabled(struct drm_i915_private *dev_priv, 1293static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe) 1294 enum pipe pipe)
1340{ 1295{
1341 struct drm_device *dev = dev_priv->dev; 1296 struct drm_device *dev = &dev_priv->drm;
1342 int i; 1297 int i;
1343 1298
1344 /* Primary planes are fixed to pipes on gen4+ */ 1299 /* Primary planes are fixed to pipes on gen4+ */
@@ -1364,7 +1319,7 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1364static void assert_sprites_disabled(struct drm_i915_private *dev_priv, 1319static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1365 enum pipe pipe) 1320 enum pipe pipe)
1366{ 1321{
1367 struct drm_device *dev = dev_priv->dev; 1322 struct drm_device *dev = &dev_priv->drm;
1368 int sprite; 1323 int sprite;
1369 1324
1370 if (INTEL_INFO(dev)->gen >= 9) { 1325 if (INTEL_INFO(dev)->gen >= 9) {
@@ -1544,7 +1499,11 @@ static void _vlv_enable_pll(struct intel_crtc *crtc,
1544 POSTING_READ(DPLL(pipe)); 1499 POSTING_READ(DPLL(pipe));
1545 udelay(150); 1500 udelay(150);
1546 1501
1547 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) 1502 if (intel_wait_for_register(dev_priv,
1503 DPLL(pipe),
1504 DPLL_LOCK_VLV,
1505 DPLL_LOCK_VLV,
1506 1))
1548 DRM_ERROR("DPLL %d failed to lock\n", pipe); 1507 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1549} 1508}
1550 1509
@@ -1593,7 +1552,9 @@ static void _chv_enable_pll(struct intel_crtc *crtc,
1593 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); 1552 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1594 1553
1595 /* Check PLL is locked */ 1554 /* Check PLL is locked */
1596 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) 1555 if (intel_wait_for_register(dev_priv,
1556 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1557 1))
1597 DRM_ERROR("PLL %d failed to lock\n", pipe); 1558 DRM_ERROR("PLL %d failed to lock\n", pipe);
1598} 1559}
1599 1560
@@ -1639,9 +1600,10 @@ static int intel_num_dvo_pipes(struct drm_device *dev)
1639 struct intel_crtc *crtc; 1600 struct intel_crtc *crtc;
1640 int count = 0; 1601 int count = 0;
1641 1602
1642 for_each_intel_crtc(dev, crtc) 1603 for_each_intel_crtc(dev, crtc) {
1643 count += crtc->base.state->active && 1604 count += crtc->base.state->active &&
1644 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); 1605 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1606 }
1645 1607
1646 return count; 1608 return count;
1647} 1609}
@@ -1649,7 +1611,7 @@ static int intel_num_dvo_pipes(struct drm_device *dev)
1649static void i9xx_enable_pll(struct intel_crtc *crtc) 1611static void i9xx_enable_pll(struct intel_crtc *crtc)
1650{ 1612{
1651 struct drm_device *dev = crtc->base.dev; 1613 struct drm_device *dev = crtc->base.dev;
1652 struct drm_i915_private *dev_priv = dev->dev_private; 1614 struct drm_i915_private *dev_priv = to_i915(dev);
1653 i915_reg_t reg = DPLL(crtc->pipe); 1615 i915_reg_t reg = DPLL(crtc->pipe);
1654 u32 dpll = crtc->config->dpll_hw_state.dpll; 1616 u32 dpll = crtc->config->dpll_hw_state.dpll;
1655 1617
@@ -1721,12 +1683,12 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
1721static void i9xx_disable_pll(struct intel_crtc *crtc) 1683static void i9xx_disable_pll(struct intel_crtc *crtc)
1722{ 1684{
1723 struct drm_device *dev = crtc->base.dev; 1685 struct drm_device *dev = crtc->base.dev;
1724 struct drm_i915_private *dev_priv = dev->dev_private; 1686 struct drm_i915_private *dev_priv = to_i915(dev);
1725 enum pipe pipe = crtc->pipe; 1687 enum pipe pipe = crtc->pipe;
1726 1688
1727 /* Disable DVO 2x clock on both PLLs if necessary */ 1689 /* Disable DVO 2x clock on both PLLs if necessary */
1728 if (IS_I830(dev) && 1690 if (IS_I830(dev) &&
1729 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && 1691 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1730 !intel_num_dvo_pipes(dev)) { 1692 !intel_num_dvo_pipes(dev)) {
1731 I915_WRITE(DPLL(PIPE_B), 1693 I915_WRITE(DPLL(PIPE_B),
1732 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); 1694 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
@@ -1813,7 +1775,9 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1813 BUG(); 1775 BUG();
1814 } 1776 }
1815 1777
1816 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) 1778 if (intel_wait_for_register(dev_priv,
1779 dpll_reg, port_mask, expected_mask,
1780 1000))
1817 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", 1781 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1818 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); 1782 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1819} 1783}
@@ -1821,7 +1785,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1821static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, 1785static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1822 enum pipe pipe) 1786 enum pipe pipe)
1823{ 1787{
1824 struct drm_device *dev = dev_priv->dev; 1788 struct drm_device *dev = &dev_priv->drm;
1825 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1789 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1827 i915_reg_t reg; 1791 i915_reg_t reg;
@@ -1854,7 +1818,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1854 * here for both 8bpc and 12bpc. 1818 * here for both 8bpc and 12bpc.
1855 */ 1819 */
1856 val &= ~PIPECONF_BPC_MASK; 1820 val &= ~PIPECONF_BPC_MASK;
1857 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) 1821 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1858 val |= PIPECONF_8BPC; 1822 val |= PIPECONF_8BPC;
1859 else 1823 else
1860 val |= pipeconf_val & PIPECONF_BPC_MASK; 1824 val |= pipeconf_val & PIPECONF_BPC_MASK;
@@ -1863,7 +1827,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1863 val &= ~TRANS_INTERLACE_MASK; 1827 val &= ~TRANS_INTERLACE_MASK;
1864 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) 1828 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1865 if (HAS_PCH_IBX(dev_priv) && 1829 if (HAS_PCH_IBX(dev_priv) &&
1866 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) 1830 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1867 val |= TRANS_LEGACY_INTERLACED_ILK; 1831 val |= TRANS_LEGACY_INTERLACED_ILK;
1868 else 1832 else
1869 val |= TRANS_INTERLACED; 1833 val |= TRANS_INTERLACED;
@@ -1871,7 +1835,9 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1871 val |= TRANS_PROGRESSIVE; 1835 val |= TRANS_PROGRESSIVE;
1872 1836
1873 I915_WRITE(reg, val | TRANS_ENABLE); 1837 I915_WRITE(reg, val | TRANS_ENABLE);
1874 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) 1838 if (intel_wait_for_register(dev_priv,
1839 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1840 100))
1875 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); 1841 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1876} 1842}
1877 1843
@@ -1899,14 +1865,18 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1899 val |= TRANS_PROGRESSIVE; 1865 val |= TRANS_PROGRESSIVE;
1900 1866
1901 I915_WRITE(LPT_TRANSCONF, val); 1867 I915_WRITE(LPT_TRANSCONF, val);
1902 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) 1868 if (intel_wait_for_register(dev_priv,
1869 LPT_TRANSCONF,
1870 TRANS_STATE_ENABLE,
1871 TRANS_STATE_ENABLE,
1872 100))
1903 DRM_ERROR("Failed to enable PCH transcoder\n"); 1873 DRM_ERROR("Failed to enable PCH transcoder\n");
1904} 1874}
1905 1875
1906static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, 1876static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1907 enum pipe pipe) 1877 enum pipe pipe)
1908{ 1878{
1909 struct drm_device *dev = dev_priv->dev; 1879 struct drm_device *dev = &dev_priv->drm;
1910 i915_reg_t reg; 1880 i915_reg_t reg;
1911 uint32_t val; 1881 uint32_t val;
1912 1882
@@ -1922,7 +1892,9 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1922 val &= ~TRANS_ENABLE; 1892 val &= ~TRANS_ENABLE;
1923 I915_WRITE(reg, val); 1893 I915_WRITE(reg, val);
1924 /* wait for PCH transcoder off, transcoder state */ 1894 /* wait for PCH transcoder off, transcoder state */
1925 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) 1895 if (intel_wait_for_register(dev_priv,
1896 reg, TRANS_STATE_ENABLE, 0,
1897 50))
1926 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); 1898 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1927 1899
1928 if (HAS_PCH_CPT(dev)) { 1900 if (HAS_PCH_CPT(dev)) {
@@ -1942,7 +1914,9 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1942 val &= ~TRANS_ENABLE; 1914 val &= ~TRANS_ENABLE;
1943 I915_WRITE(LPT_TRANSCONF, val); 1915 I915_WRITE(LPT_TRANSCONF, val);
1944 /* wait for PCH transcoder off, transcoder state */ 1916 /* wait for PCH transcoder off, transcoder state */
1945 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) 1917 if (intel_wait_for_register(dev_priv,
1918 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1919 50))
1946 DRM_ERROR("Failed to disable PCH transcoder\n"); 1920 DRM_ERROR("Failed to disable PCH transcoder\n");
1947 1921
1948 /* Workaround: clear timing override bit. */ 1922 /* Workaround: clear timing override bit. */
@@ -1961,7 +1935,7 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1961static void intel_enable_pipe(struct intel_crtc *crtc) 1935static void intel_enable_pipe(struct intel_crtc *crtc)
1962{ 1936{
1963 struct drm_device *dev = crtc->base.dev; 1937 struct drm_device *dev = crtc->base.dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private; 1938 struct drm_i915_private *dev_priv = to_i915(dev);
1965 enum pipe pipe = crtc->pipe; 1939 enum pipe pipe = crtc->pipe;
1966 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; 1940 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1967 enum pipe pch_transcoder; 1941 enum pipe pch_transcoder;
@@ -1985,7 +1959,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
1985 * need the check. 1959 * need the check.
1986 */ 1960 */
1987 if (HAS_GMCH_DISPLAY(dev_priv)) 1961 if (HAS_GMCH_DISPLAY(dev_priv))
1988 if (crtc->config->has_dsi_encoder) 1962 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1989 assert_dsi_pll_enabled(dev_priv); 1963 assert_dsi_pll_enabled(dev_priv);
1990 else 1964 else
1991 assert_pll_enabled(dev_priv, pipe); 1965 assert_pll_enabled(dev_priv, pipe);
@@ -2034,7 +2008,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
2034 */ 2008 */
2035static void intel_disable_pipe(struct intel_crtc *crtc) 2009static void intel_disable_pipe(struct intel_crtc *crtc)
2036{ 2010{
2037 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 2011 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2038 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; 2012 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2039 enum pipe pipe = crtc->pipe; 2013 enum pipe pipe = crtc->pipe;
2040 i915_reg_t reg; 2014 i915_reg_t reg;
@@ -2072,15 +2046,6 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
2072 intel_wait_for_pipe_off(crtc); 2046 intel_wait_for_pipe_off(crtc);
2073} 2047}
2074 2048
2075static bool need_vtd_wa(struct drm_device *dev)
2076{
2077#ifdef CONFIG_INTEL_IOMMU
2078 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2079 return true;
2080#endif
2081 return false;
2082}
2083
2084static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) 2049static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2085{ 2050{
2086 return IS_GEN2(dev_priv) ? 2048 : 4096; 2051 return IS_GEN2(dev_priv) ? 2048 : 4096;
@@ -2245,7 +2210,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2245 unsigned int rotation) 2210 unsigned int rotation)
2246{ 2211{
2247 struct drm_device *dev = fb->dev; 2212 struct drm_device *dev = fb->dev;
2248 struct drm_i915_private *dev_priv = dev->dev_private; 2213 struct drm_i915_private *dev_priv = to_i915(dev);
2249 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 2214 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2250 struct i915_ggtt_view view; 2215 struct i915_ggtt_view view;
2251 u32 alignment; 2216 u32 alignment;
@@ -2262,7 +2227,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2262 * we should always have valid PTE following the scanout preventing 2227 * we should always have valid PTE following the scanout preventing
2263 * the VT-d warning. 2228 * the VT-d warning.
2264 */ 2229 */
2265 if (need_vtd_wa(dev) && alignment < 256 * 1024) 2230 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2266 alignment = 256 * 1024; 2231 alignment = 256 * 1024;
2267 2232
2268 /* 2233 /*
@@ -2547,7 +2512,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2547 struct intel_initial_plane_config *plane_config) 2512 struct intel_initial_plane_config *plane_config)
2548{ 2513{
2549 struct drm_device *dev = intel_crtc->base.dev; 2514 struct drm_device *dev = intel_crtc->base.dev;
2550 struct drm_i915_private *dev_priv = dev->dev_private; 2515 struct drm_i915_private *dev_priv = to_i915(dev);
2551 struct drm_crtc *c; 2516 struct drm_crtc *c;
2552 struct intel_crtc *i; 2517 struct intel_crtc *i;
2553 struct drm_i915_gem_object *obj; 2518 struct drm_i915_gem_object *obj;
@@ -2643,7 +2608,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
2643 const struct intel_plane_state *plane_state) 2608 const struct intel_plane_state *plane_state)
2644{ 2609{
2645 struct drm_device *dev = primary->dev; 2610 struct drm_device *dev = primary->dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private; 2611 struct drm_i915_private *dev_priv = to_i915(dev);
2647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 2612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2648 struct drm_framebuffer *fb = plane_state->base.fb; 2613 struct drm_framebuffer *fb = plane_state->base.fb;
2649 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 2614 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
@@ -2756,7 +2721,7 @@ static void i9xx_disable_primary_plane(struct drm_plane *primary,
2756 struct drm_crtc *crtc) 2721 struct drm_crtc *crtc)
2757{ 2722{
2758 struct drm_device *dev = crtc->dev; 2723 struct drm_device *dev = crtc->dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private; 2724 struct drm_i915_private *dev_priv = to_i915(dev);
2760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2761 int plane = intel_crtc->plane; 2726 int plane = intel_crtc->plane;
2762 2727
@@ -2773,7 +2738,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
2773 const struct intel_plane_state *plane_state) 2738 const struct intel_plane_state *plane_state)
2774{ 2739{
2775 struct drm_device *dev = primary->dev; 2740 struct drm_device *dev = primary->dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private; 2741 struct drm_i915_private *dev_priv = to_i915(dev);
2777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 2742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2778 struct drm_framebuffer *fb = plane_state->base.fb; 2743 struct drm_framebuffer *fb = plane_state->base.fb;
2779 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 2744 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
@@ -2901,7 +2866,7 @@ u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2901static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) 2866static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2902{ 2867{
2903 struct drm_device *dev = intel_crtc->base.dev; 2868 struct drm_device *dev = intel_crtc->base.dev;
2904 struct drm_i915_private *dev_priv = dev->dev_private; 2869 struct drm_i915_private *dev_priv = to_i915(dev);
2905 2870
2906 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); 2871 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2907 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); 2872 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
@@ -3011,7 +2976,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
3011 const struct intel_plane_state *plane_state) 2976 const struct intel_plane_state *plane_state)
3012{ 2977{
3013 struct drm_device *dev = plane->dev; 2978 struct drm_device *dev = plane->dev;
3014 struct drm_i915_private *dev_priv = dev->dev_private; 2979 struct drm_i915_private *dev_priv = to_i915(dev);
3015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 2980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3016 struct drm_framebuffer *fb = plane_state->base.fb; 2981 struct drm_framebuffer *fb = plane_state->base.fb;
3017 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 2982 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
@@ -3095,7 +3060,7 @@ static void skylake_disable_primary_plane(struct drm_plane *primary,
3095 struct drm_crtc *crtc) 3060 struct drm_crtc *crtc)
3096{ 3061{
3097 struct drm_device *dev = crtc->dev; 3062 struct drm_device *dev = crtc->dev;
3098 struct drm_i915_private *dev_priv = dev->dev_private; 3063 struct drm_i915_private *dev_priv = to_i915(dev);
3099 int pipe = to_intel_crtc(crtc)->pipe; 3064 int pipe = to_intel_crtc(crtc)->pipe;
3100 3065
3101 I915_WRITE(PLANE_CTL(pipe, 0), 0); 3066 I915_WRITE(PLANE_CTL(pipe, 0), 0);
@@ -3118,7 +3083,7 @@ static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3118{ 3083{
3119 struct intel_crtc *crtc; 3084 struct intel_crtc *crtc;
3120 3085
3121 for_each_intel_crtc(dev_priv->dev, crtc) 3086 for_each_intel_crtc(&dev_priv->drm, crtc)
3122 intel_finish_page_flip_cs(dev_priv, crtc->pipe); 3087 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3123} 3088}
3124 3089
@@ -3152,12 +3117,12 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv)
3152 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) 3117 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3153 return; 3118 return;
3154 3119
3155 drm_modeset_lock_all(dev_priv->dev); 3120 drm_modeset_lock_all(&dev_priv->drm);
3156 /* 3121 /*
3157 * Disabling the crtcs gracefully seems nicer. Also the 3122 * Disabling the crtcs gracefully seems nicer. Also the
3158 * g33 docs say we should at least disable all the planes. 3123 * g33 docs say we should at least disable all the planes.
3159 */ 3124 */
3160 intel_display_suspend(dev_priv->dev); 3125 intel_display_suspend(&dev_priv->drm);
3161} 3126}
3162 3127
3163void intel_finish_reset(struct drm_i915_private *dev_priv) 3128void intel_finish_reset(struct drm_i915_private *dev_priv)
@@ -3184,7 +3149,7 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
3184 * FIXME: Atomic will make this obsolete since we won't schedule 3149 * FIXME: Atomic will make this obsolete since we won't schedule
3185 * CS-based flips (which might get lost in gpu resets) any more. 3150 * CS-based flips (which might get lost in gpu resets) any more.
3186 */ 3151 */
3187 intel_update_primary_planes(dev_priv->dev); 3152 intel_update_primary_planes(&dev_priv->drm);
3188 return; 3153 return;
3189 } 3154 }
3190 3155
@@ -3195,18 +3160,18 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
3195 intel_runtime_pm_disable_interrupts(dev_priv); 3160 intel_runtime_pm_disable_interrupts(dev_priv);
3196 intel_runtime_pm_enable_interrupts(dev_priv); 3161 intel_runtime_pm_enable_interrupts(dev_priv);
3197 3162
3198 intel_modeset_init_hw(dev_priv->dev); 3163 intel_modeset_init_hw(&dev_priv->drm);
3199 3164
3200 spin_lock_irq(&dev_priv->irq_lock); 3165 spin_lock_irq(&dev_priv->irq_lock);
3201 if (dev_priv->display.hpd_irq_setup) 3166 if (dev_priv->display.hpd_irq_setup)
3202 dev_priv->display.hpd_irq_setup(dev_priv); 3167 dev_priv->display.hpd_irq_setup(dev_priv);
3203 spin_unlock_irq(&dev_priv->irq_lock); 3168 spin_unlock_irq(&dev_priv->irq_lock);
3204 3169
3205 intel_display_resume(dev_priv->dev); 3170 intel_display_resume(&dev_priv->drm);
3206 3171
3207 intel_hpd_init(dev_priv); 3172 intel_hpd_init(dev_priv);
3208 3173
3209 drm_modeset_unlock_all(dev_priv->dev); 3174 drm_modeset_unlock_all(&dev_priv->drm);
3210} 3175}
3211 3176
3212static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) 3177static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
@@ -3231,7 +3196,7 @@ static void intel_update_pipe_config(struct intel_crtc *crtc,
3231 struct intel_crtc_state *old_crtc_state) 3196 struct intel_crtc_state *old_crtc_state)
3232{ 3197{
3233 struct drm_device *dev = crtc->base.dev; 3198 struct drm_device *dev = crtc->base.dev;
3234 struct drm_i915_private *dev_priv = dev->dev_private; 3199 struct drm_i915_private *dev_priv = to_i915(dev);
3235 struct intel_crtc_state *pipe_config = 3200 struct intel_crtc_state *pipe_config =
3236 to_intel_crtc_state(crtc->base.state); 3201 to_intel_crtc_state(crtc->base.state);
3237 3202
@@ -3272,7 +3237,7 @@ static void intel_update_pipe_config(struct intel_crtc *crtc,
3272static void intel_fdi_normal_train(struct drm_crtc *crtc) 3237static void intel_fdi_normal_train(struct drm_crtc *crtc)
3273{ 3238{
3274 struct drm_device *dev = crtc->dev; 3239 struct drm_device *dev = crtc->dev;
3275 struct drm_i915_private *dev_priv = dev->dev_private; 3240 struct drm_i915_private *dev_priv = to_i915(dev);
3276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3277 int pipe = intel_crtc->pipe; 3242 int pipe = intel_crtc->pipe;
3278 i915_reg_t reg; 3243 i915_reg_t reg;
@@ -3315,7 +3280,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
3315static void ironlake_fdi_link_train(struct drm_crtc *crtc) 3280static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3316{ 3281{
3317 struct drm_device *dev = crtc->dev; 3282 struct drm_device *dev = crtc->dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private; 3283 struct drm_i915_private *dev_priv = to_i915(dev);
3319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3320 int pipe = intel_crtc->pipe; 3285 int pipe = intel_crtc->pipe;
3321 i915_reg_t reg; 3286 i915_reg_t reg;
@@ -3416,7 +3381,7 @@ static const int snb_b_fdi_train_param[] = {
3416static void gen6_fdi_link_train(struct drm_crtc *crtc) 3381static void gen6_fdi_link_train(struct drm_crtc *crtc)
3417{ 3382{
3418 struct drm_device *dev = crtc->dev; 3383 struct drm_device *dev = crtc->dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private; 3384 struct drm_i915_private *dev_priv = to_i915(dev);
3420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3421 int pipe = intel_crtc->pipe; 3386 int pipe = intel_crtc->pipe;
3422 i915_reg_t reg; 3387 i915_reg_t reg;
@@ -3549,7 +3514,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
3549static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) 3514static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3550{ 3515{
3551 struct drm_device *dev = crtc->dev; 3516 struct drm_device *dev = crtc->dev;
3552 struct drm_i915_private *dev_priv = dev->dev_private; 3517 struct drm_i915_private *dev_priv = to_i915(dev);
3553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3554 int pipe = intel_crtc->pipe; 3519 int pipe = intel_crtc->pipe;
3555 i915_reg_t reg; 3520 i915_reg_t reg;
@@ -3668,7 +3633,7 @@ train_done:
3668static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) 3633static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3669{ 3634{
3670 struct drm_device *dev = intel_crtc->base.dev; 3635 struct drm_device *dev = intel_crtc->base.dev;
3671 struct drm_i915_private *dev_priv = dev->dev_private; 3636 struct drm_i915_private *dev_priv = to_i915(dev);
3672 int pipe = intel_crtc->pipe; 3637 int pipe = intel_crtc->pipe;
3673 i915_reg_t reg; 3638 i915_reg_t reg;
3674 u32 temp; 3639 u32 temp;
@@ -3705,7 +3670,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3705static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) 3670static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3706{ 3671{
3707 struct drm_device *dev = intel_crtc->base.dev; 3672 struct drm_device *dev = intel_crtc->base.dev;
3708 struct drm_i915_private *dev_priv = dev->dev_private; 3673 struct drm_i915_private *dev_priv = to_i915(dev);
3709 int pipe = intel_crtc->pipe; 3674 int pipe = intel_crtc->pipe;
3710 i915_reg_t reg; 3675 i915_reg_t reg;
3711 u32 temp; 3676 u32 temp;
@@ -3735,7 +3700,7 @@ static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3735static void ironlake_fdi_disable(struct drm_crtc *crtc) 3700static void ironlake_fdi_disable(struct drm_crtc *crtc)
3736{ 3701{
3737 struct drm_device *dev = crtc->dev; 3702 struct drm_device *dev = crtc->dev;
3738 struct drm_i915_private *dev_priv = dev->dev_private; 3703 struct drm_i915_private *dev_priv = to_i915(dev);
3739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3740 int pipe = intel_crtc->pipe; 3705 int pipe = intel_crtc->pipe;
3741 i915_reg_t reg; 3706 i915_reg_t reg;
@@ -3831,7 +3796,7 @@ static void page_flip_completed(struct intel_crtc *intel_crtc)
3831static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) 3796static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3832{ 3797{
3833 struct drm_device *dev = crtc->dev; 3798 struct drm_device *dev = crtc->dev;
3834 struct drm_i915_private *dev_priv = dev->dev_private; 3799 struct drm_i915_private *dev_priv = to_i915(dev);
3835 long ret; 3800 long ret;
3836 3801
3837 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); 3802 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
@@ -3994,7 +3959,7 @@ static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3994 enum pipe pch_transcoder) 3959 enum pipe pch_transcoder)
3995{ 3960{
3996 struct drm_device *dev = crtc->base.dev; 3961 struct drm_device *dev = crtc->base.dev;
3997 struct drm_i915_private *dev_priv = dev->dev_private; 3962 struct drm_i915_private *dev_priv = to_i915(dev);
3998 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; 3963 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3999 3964
4000 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), 3965 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
@@ -4016,7 +3981,7 @@ static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4016 3981
4017static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) 3982static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4018{ 3983{
4019 struct drm_i915_private *dev_priv = dev->dev_private; 3984 struct drm_i915_private *dev_priv = to_i915(dev);
4020 uint32_t temp; 3985 uint32_t temp;
4021 3986
4022 temp = I915_READ(SOUTH_CHICKEN1); 3987 temp = I915_READ(SOUTH_CHICKEN1);
@@ -4066,7 +4031,7 @@ intel_trans_dp_port_sel(struct drm_crtc *crtc)
4066 struct intel_encoder *encoder; 4031 struct intel_encoder *encoder;
4067 4032
4068 for_each_encoder_on_crtc(dev, crtc, encoder) { 4033 for_each_encoder_on_crtc(dev, crtc, encoder) {
4069 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || 4034 if (encoder->type == INTEL_OUTPUT_DP ||
4070 encoder->type == INTEL_OUTPUT_EDP) 4035 encoder->type == INTEL_OUTPUT_EDP)
4071 return enc_to_dig_port(&encoder->base)->port; 4036 return enc_to_dig_port(&encoder->base)->port;
4072 } 4037 }
@@ -4085,7 +4050,7 @@ intel_trans_dp_port_sel(struct drm_crtc *crtc)
4085static void ironlake_pch_enable(struct drm_crtc *crtc) 4050static void ironlake_pch_enable(struct drm_crtc *crtc)
4086{ 4051{
4087 struct drm_device *dev = crtc->dev; 4052 struct drm_device *dev = crtc->dev;
4088 struct drm_i915_private *dev_priv = dev->dev_private; 4053 struct drm_i915_private *dev_priv = to_i915(dev);
4089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4090 int pipe = intel_crtc->pipe; 4055 int pipe = intel_crtc->pipe;
4091 u32 temp; 4056 u32 temp;
@@ -4135,7 +4100,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
4135 intel_fdi_normal_train(crtc); 4100 intel_fdi_normal_train(crtc);
4136 4101
4137 /* For PCH DP, enable TRANS_DP_CTL */ 4102 /* For PCH DP, enable TRANS_DP_CTL */
4138 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { 4103 if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4139 const struct drm_display_mode *adjusted_mode = 4104 const struct drm_display_mode *adjusted_mode =
4140 &intel_crtc->config->base.adjusted_mode; 4105 &intel_crtc->config->base.adjusted_mode;
4141 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; 4106 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
@@ -4175,7 +4140,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
4175static void lpt_pch_enable(struct drm_crtc *crtc) 4140static void lpt_pch_enable(struct drm_crtc *crtc)
4176{ 4141{
4177 struct drm_device *dev = crtc->dev; 4142 struct drm_device *dev = crtc->dev;
4178 struct drm_i915_private *dev_priv = dev->dev_private; 4143 struct drm_i915_private *dev_priv = to_i915(dev);
4179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4180 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 4145 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4181 4146
@@ -4191,7 +4156,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
4191 4156
4192static void cpt_verify_modeset(struct drm_device *dev, int pipe) 4157static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4193{ 4158{
4194 struct drm_i915_private *dev_priv = dev->dev_private; 4159 struct drm_i915_private *dev_priv = to_i915(dev);
4195 i915_reg_t dslreg = PIPEDSL(pipe); 4160 i915_reg_t dslreg = PIPEDSL(pipe);
4196 u32 temp; 4161 u32 temp;
4197 4162
@@ -4369,7 +4334,7 @@ static void skylake_scaler_disable(struct intel_crtc *crtc)
4369static void skylake_pfit_enable(struct intel_crtc *crtc) 4334static void skylake_pfit_enable(struct intel_crtc *crtc)
4370{ 4335{
4371 struct drm_device *dev = crtc->base.dev; 4336 struct drm_device *dev = crtc->base.dev;
4372 struct drm_i915_private *dev_priv = dev->dev_private; 4337 struct drm_i915_private *dev_priv = to_i915(dev);
4373 int pipe = crtc->pipe; 4338 int pipe = crtc->pipe;
4374 struct intel_crtc_scaler_state *scaler_state = 4339 struct intel_crtc_scaler_state *scaler_state =
4375 &crtc->config->scaler_state; 4340 &crtc->config->scaler_state;
@@ -4397,7 +4362,7 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
4397static void ironlake_pfit_enable(struct intel_crtc *crtc) 4362static void ironlake_pfit_enable(struct intel_crtc *crtc)
4398{ 4363{
4399 struct drm_device *dev = crtc->base.dev; 4364 struct drm_device *dev = crtc->base.dev;
4400 struct drm_i915_private *dev_priv = dev->dev_private; 4365 struct drm_i915_private *dev_priv = to_i915(dev);
4401 int pipe = crtc->pipe; 4366 int pipe = crtc->pipe;
4402 4367
4403 if (crtc->config->pch_pfit.enabled) { 4368 if (crtc->config->pch_pfit.enabled) {
@@ -4418,7 +4383,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
4418void hsw_enable_ips(struct intel_crtc *crtc) 4383void hsw_enable_ips(struct intel_crtc *crtc)
4419{ 4384{
4420 struct drm_device *dev = crtc->base.dev; 4385 struct drm_device *dev = crtc->base.dev;
4421 struct drm_i915_private *dev_priv = dev->dev_private; 4386 struct drm_i915_private *dev_priv = to_i915(dev);
4422 4387
4423 if (!crtc->config->ips_enabled) 4388 if (!crtc->config->ips_enabled)
4424 return; 4389 return;
@@ -4446,7 +4411,9 @@ void hsw_enable_ips(struct intel_crtc *crtc)
4446 * and don't wait for vblanks until the end of crtc_enable, then 4411 * and don't wait for vblanks until the end of crtc_enable, then
4447 * the HW state readout code will complain that the expected 4412 * the HW state readout code will complain that the expected
4448 * IPS_CTL value is not the one we read. */ 4413 * IPS_CTL value is not the one we read. */
4449 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) 4414 if (intel_wait_for_register(dev_priv,
4415 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4416 50))
4450 DRM_ERROR("Timed out waiting for IPS enable\n"); 4417 DRM_ERROR("Timed out waiting for IPS enable\n");
4451 } 4418 }
4452} 4419}
@@ -4454,7 +4421,7 @@ void hsw_enable_ips(struct intel_crtc *crtc)
4454void hsw_disable_ips(struct intel_crtc *crtc) 4421void hsw_disable_ips(struct intel_crtc *crtc)
4455{ 4422{
4456 struct drm_device *dev = crtc->base.dev; 4423 struct drm_device *dev = crtc->base.dev;
4457 struct drm_i915_private *dev_priv = dev->dev_private; 4424 struct drm_i915_private *dev_priv = to_i915(dev);
4458 4425
4459 if (!crtc->config->ips_enabled) 4426 if (!crtc->config->ips_enabled)
4460 return; 4427 return;
@@ -4465,7 +4432,9 @@ void hsw_disable_ips(struct intel_crtc *crtc)
4465 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); 4432 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4466 mutex_unlock(&dev_priv->rps.hw_lock); 4433 mutex_unlock(&dev_priv->rps.hw_lock);
4467 /* wait for pcode to finish disabling IPS, which may take up to 42ms */ 4434 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4468 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) 4435 if (intel_wait_for_register(dev_priv,
4436 IPS_CTL, IPS_ENABLE, 0,
4437 42))
4469 DRM_ERROR("Timed out waiting for IPS disable\n"); 4438 DRM_ERROR("Timed out waiting for IPS disable\n");
4470 } else { 4439 } else {
4471 I915_WRITE(IPS_CTL, 0); 4440 I915_WRITE(IPS_CTL, 0);
@@ -4480,7 +4449,7 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4480{ 4449{
4481 if (intel_crtc->overlay) { 4450 if (intel_crtc->overlay) {
4482 struct drm_device *dev = intel_crtc->base.dev; 4451 struct drm_device *dev = intel_crtc->base.dev;
4483 struct drm_i915_private *dev_priv = dev->dev_private; 4452 struct drm_i915_private *dev_priv = to_i915(dev);
4484 4453
4485 mutex_lock(&dev->struct_mutex); 4454 mutex_lock(&dev->struct_mutex);
4486 dev_priv->mm.interruptible = false; 4455 dev_priv->mm.interruptible = false;
@@ -4508,7 +4477,7 @@ static void
4508intel_post_enable_primary(struct drm_crtc *crtc) 4477intel_post_enable_primary(struct drm_crtc *crtc)
4509{ 4478{
4510 struct drm_device *dev = crtc->dev; 4479 struct drm_device *dev = crtc->dev;
4511 struct drm_i915_private *dev_priv = dev->dev_private; 4480 struct drm_i915_private *dev_priv = to_i915(dev);
4512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4513 int pipe = intel_crtc->pipe; 4482 int pipe = intel_crtc->pipe;
4514 4483
@@ -4540,7 +4509,7 @@ static void
4540intel_pre_disable_primary(struct drm_crtc *crtc) 4509intel_pre_disable_primary(struct drm_crtc *crtc)
4541{ 4510{
4542 struct drm_device *dev = crtc->dev; 4511 struct drm_device *dev = crtc->dev;
4543 struct drm_i915_private *dev_priv = dev->dev_private; 4512 struct drm_i915_private *dev_priv = to_i915(dev);
4544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4545 int pipe = intel_crtc->pipe; 4514 int pipe = intel_crtc->pipe;
4546 4515
@@ -4567,7 +4536,7 @@ static void
4567intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) 4536intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4568{ 4537{
4569 struct drm_device *dev = crtc->dev; 4538 struct drm_device *dev = crtc->dev;
4570 struct drm_i915_private *dev_priv = dev->dev_private; 4539 struct drm_i915_private *dev_priv = to_i915(dev);
4571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4572 int pipe = intel_crtc->pipe; 4541 int pipe = intel_crtc->pipe;
4573 4542
@@ -4626,7 +4595,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4626{ 4595{
4627 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 4596 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4628 struct drm_device *dev = crtc->base.dev; 4597 struct drm_device *dev = crtc->base.dev;
4629 struct drm_i915_private *dev_priv = dev->dev_private; 4598 struct drm_i915_private *dev_priv = to_i915(dev);
4630 struct intel_crtc_state *pipe_config = 4599 struct intel_crtc_state *pipe_config =
4631 to_intel_crtc_state(crtc->base.state); 4600 to_intel_crtc_state(crtc->base.state);
4632 struct drm_atomic_state *old_state = old_crtc_state->base.state; 4601 struct drm_atomic_state *old_state = old_crtc_state->base.state;
@@ -4729,7 +4698,7 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask
4729static void ironlake_crtc_enable(struct drm_crtc *crtc) 4698static void ironlake_crtc_enable(struct drm_crtc *crtc)
4730{ 4699{
4731 struct drm_device *dev = crtc->dev; 4700 struct drm_device *dev = crtc->dev;
4732 struct drm_i915_private *dev_priv = dev->dev_private; 4701 struct drm_i915_private *dev_priv = to_i915(dev);
4733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4734 struct intel_encoder *encoder; 4703 struct intel_encoder *encoder;
4735 int pipe = intel_crtc->pipe; 4704 int pipe = intel_crtc->pipe;
@@ -4757,7 +4726,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
4757 if (intel_crtc->config->has_pch_encoder) 4726 if (intel_crtc->config->has_pch_encoder)
4758 intel_prepare_shared_dpll(intel_crtc); 4727 intel_prepare_shared_dpll(intel_crtc);
4759 4728
4760 if (intel_crtc->config->has_dp_encoder) 4729 if (intel_crtc_has_dp_encoder(intel_crtc->config))
4761 intel_dp_set_m_n(intel_crtc, M1_N1); 4730 intel_dp_set_m_n(intel_crtc, M1_N1);
4762 4731
4763 intel_set_pipe_timings(intel_crtc); 4732 intel_set_pipe_timings(intel_crtc);
@@ -4826,7 +4795,7 @@ static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4826static void haswell_crtc_enable(struct drm_crtc *crtc) 4795static void haswell_crtc_enable(struct drm_crtc *crtc)
4827{ 4796{
4828 struct drm_device *dev = crtc->dev; 4797 struct drm_device *dev = crtc->dev;
4829 struct drm_i915_private *dev_priv = dev->dev_private; 4798 struct drm_i915_private *dev_priv = to_i915(dev);
4830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4831 struct intel_encoder *encoder; 4800 struct intel_encoder *encoder;
4832 int pipe = intel_crtc->pipe, hsw_workaround_pipe; 4801 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
@@ -4848,10 +4817,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
4848 if (intel_crtc->config->shared_dpll) 4817 if (intel_crtc->config->shared_dpll)
4849 intel_enable_shared_dpll(intel_crtc); 4818 intel_enable_shared_dpll(intel_crtc);
4850 4819
4851 if (intel_crtc->config->has_dp_encoder) 4820 if (intel_crtc_has_dp_encoder(intel_crtc->config))
4852 intel_dp_set_m_n(intel_crtc, M1_N1); 4821 intel_dp_set_m_n(intel_crtc, M1_N1);
4853 4822
4854 if (!intel_crtc->config->has_dsi_encoder) 4823 if (!transcoder_is_dsi(cpu_transcoder))
4855 intel_set_pipe_timings(intel_crtc); 4824 intel_set_pipe_timings(intel_crtc);
4856 4825
4857 intel_set_pipe_src_size(intel_crtc); 4826 intel_set_pipe_src_size(intel_crtc);
@@ -4867,7 +4836,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
4867 &intel_crtc->config->fdi_m_n, NULL); 4836 &intel_crtc->config->fdi_m_n, NULL);
4868 } 4837 }
4869 4838
4870 if (!intel_crtc->config->has_dsi_encoder) 4839 if (!transcoder_is_dsi(cpu_transcoder))
4871 haswell_set_pipeconf(crtc); 4840 haswell_set_pipeconf(crtc);
4872 4841
4873 haswell_set_pipemisc(crtc); 4842 haswell_set_pipemisc(crtc);
@@ -4889,7 +4858,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
4889 if (intel_crtc->config->has_pch_encoder) 4858 if (intel_crtc->config->has_pch_encoder)
4890 dev_priv->display.fdi_link_train(crtc); 4859 dev_priv->display.fdi_link_train(crtc);
4891 4860
4892 if (!intel_crtc->config->has_dsi_encoder) 4861 if (!transcoder_is_dsi(cpu_transcoder))
4893 intel_ddi_enable_pipe_clock(intel_crtc); 4862 intel_ddi_enable_pipe_clock(intel_crtc);
4894 4863
4895 if (INTEL_INFO(dev)->gen >= 9) 4864 if (INTEL_INFO(dev)->gen >= 9)
@@ -4904,7 +4873,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
4904 intel_color_load_luts(&pipe_config->base); 4873 intel_color_load_luts(&pipe_config->base);
4905 4874
4906 intel_ddi_set_pipe_settings(crtc); 4875 intel_ddi_set_pipe_settings(crtc);
4907 if (!intel_crtc->config->has_dsi_encoder) 4876 if (!transcoder_is_dsi(cpu_transcoder))
4908 intel_ddi_enable_transcoder_func(crtc); 4877 intel_ddi_enable_transcoder_func(crtc);
4909 4878
4910 if (dev_priv->display.initial_watermarks != NULL) 4879 if (dev_priv->display.initial_watermarks != NULL)
@@ -4913,7 +4882,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
4913 intel_update_watermarks(crtc); 4882 intel_update_watermarks(crtc);
4914 4883
4915 /* XXX: Do the pipe assertions at the right place for BXT DSI. */ 4884 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4916 if (!intel_crtc->config->has_dsi_encoder) 4885 if (!transcoder_is_dsi(cpu_transcoder))
4917 intel_enable_pipe(intel_crtc); 4886 intel_enable_pipe(intel_crtc);
4918 4887
4919 if (intel_crtc->config->has_pch_encoder) 4888 if (intel_crtc->config->has_pch_encoder)
@@ -4950,7 +4919,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
4950static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) 4919static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4951{ 4920{
4952 struct drm_device *dev = crtc->base.dev; 4921 struct drm_device *dev = crtc->base.dev;
4953 struct drm_i915_private *dev_priv = dev->dev_private; 4922 struct drm_i915_private *dev_priv = to_i915(dev);
4954 int pipe = crtc->pipe; 4923 int pipe = crtc->pipe;
4955 4924
4956 /* To avoid upsetting the power well on haswell only disable the pfit if 4925 /* To avoid upsetting the power well on haswell only disable the pfit if
@@ -4965,7 +4934,7 @@ static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4965static void ironlake_crtc_disable(struct drm_crtc *crtc) 4934static void ironlake_crtc_disable(struct drm_crtc *crtc)
4966{ 4935{
4967 struct drm_device *dev = crtc->dev; 4936 struct drm_device *dev = crtc->dev;
4968 struct drm_i915_private *dev_priv = dev->dev_private; 4937 struct drm_i915_private *dev_priv = to_i915(dev);
4969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4970 struct intel_encoder *encoder; 4939 struct intel_encoder *encoder;
4971 int pipe = intel_crtc->pipe; 4940 int pipe = intel_crtc->pipe;
@@ -5028,7 +4997,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
5028static void haswell_crtc_disable(struct drm_crtc *crtc) 4997static void haswell_crtc_disable(struct drm_crtc *crtc)
5029{ 4998{
5030 struct drm_device *dev = crtc->dev; 4999 struct drm_device *dev = crtc->dev;
5031 struct drm_i915_private *dev_priv = dev->dev_private; 5000 struct drm_i915_private *dev_priv = to_i915(dev);
5032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5033 struct intel_encoder *encoder; 5002 struct intel_encoder *encoder;
5034 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 5003 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
@@ -5046,13 +5015,13 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
5046 assert_vblank_disabled(crtc); 5015 assert_vblank_disabled(crtc);
5047 5016
5048 /* XXX: Do the pipe assertions at the right place for BXT DSI. */ 5017 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5049 if (!intel_crtc->config->has_dsi_encoder) 5018 if (!transcoder_is_dsi(cpu_transcoder))
5050 intel_disable_pipe(intel_crtc); 5019 intel_disable_pipe(intel_crtc);
5051 5020
5052 if (intel_crtc->config->dp_encoder_is_mst) 5021 if (intel_crtc->config->dp_encoder_is_mst)
5053 intel_ddi_set_vc_payload_alloc(crtc, false); 5022 intel_ddi_set_vc_payload_alloc(crtc, false);
5054 5023
5055 if (!intel_crtc->config->has_dsi_encoder) 5024 if (!transcoder_is_dsi(cpu_transcoder))
5056 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); 5025 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5057 5026
5058 if (INTEL_INFO(dev)->gen >= 9) 5027 if (INTEL_INFO(dev)->gen >= 9)
@@ -5060,7 +5029,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
5060 else 5029 else
5061 ironlake_pfit_disable(intel_crtc, false); 5030 ironlake_pfit_disable(intel_crtc, false);
5062 5031
5063 if (!intel_crtc->config->has_dsi_encoder) 5032 if (!transcoder_is_dsi(cpu_transcoder))
5064 intel_ddi_disable_pipe_clock(intel_crtc); 5033 intel_ddi_disable_pipe_clock(intel_crtc);
5065 5034
5066 for_each_encoder_on_crtc(dev, crtc, encoder) 5035 for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -5080,7 +5049,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
5080static void i9xx_pfit_enable(struct intel_crtc *crtc) 5049static void i9xx_pfit_enable(struct intel_crtc *crtc)
5081{ 5050{
5082 struct drm_device *dev = crtc->base.dev; 5051 struct drm_device *dev = crtc->base.dev;
5083 struct drm_i915_private *dev_priv = dev->dev_private; 5052 struct drm_i915_private *dev_priv = to_i915(dev);
5084 struct intel_crtc_state *pipe_config = crtc->config; 5053 struct intel_crtc_state *pipe_config = crtc->config;
5085 5054
5086 if (!pipe_config->gmch_pfit.control) 5055 if (!pipe_config->gmch_pfit.control)
@@ -5150,7 +5119,7 @@ intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5150 case INTEL_OUTPUT_UNKNOWN: 5119 case INTEL_OUTPUT_UNKNOWN:
5151 /* Only DDI platforms should ever use this output type */ 5120 /* Only DDI platforms should ever use this output type */
5152 WARN_ON_ONCE(!HAS_DDI(dev)); 5121 WARN_ON_ONCE(!HAS_DDI(dev));
5153 case INTEL_OUTPUT_DISPLAYPORT: 5122 case INTEL_OUTPUT_DP:
5154 case INTEL_OUTPUT_HDMI: 5123 case INTEL_OUTPUT_HDMI:
5155 case INTEL_OUTPUT_EDP: 5124 case INTEL_OUTPUT_EDP:
5156 intel_dig_port = enc_to_dig_port(&intel_encoder->base); 5125 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
@@ -5184,7 +5153,7 @@ intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5184 * run the DP detection too. 5153 * run the DP detection too.
5185 */ 5154 */
5186 WARN_ON_ONCE(!HAS_DDI(dev)); 5155 WARN_ON_ONCE(!HAS_DDI(dev));
5187 case INTEL_OUTPUT_DISPLAYPORT: 5156 case INTEL_OUTPUT_DP:
5188 case INTEL_OUTPUT_EDP: 5157 case INTEL_OUTPUT_EDP:
5189 intel_dig_port = enc_to_dig_port(&intel_encoder->base); 5158 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5190 return port_to_aux_power_domain(intel_dig_port->port); 5159 return port_to_aux_power_domain(intel_dig_port->port);
@@ -5232,7 +5201,7 @@ static unsigned long
5232modeset_get_crtc_power_domains(struct drm_crtc *crtc, 5201modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5233 struct intel_crtc_state *crtc_state) 5202 struct intel_crtc_state *crtc_state)
5234{ 5203{
5235 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 5204 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5237 enum intel_display_power_domain domain; 5206 enum intel_display_power_domain domain;
5238 unsigned long domains, new_domains, old_domains; 5207 unsigned long domains, new_domains, old_domains;
@@ -5277,7 +5246,7 @@ static int skl_calc_cdclk(int max_pixclk, int vco);
5277 5246
5278static void intel_update_max_cdclk(struct drm_device *dev) 5247static void intel_update_max_cdclk(struct drm_device *dev)
5279{ 5248{
5280 struct drm_i915_private *dev_priv = dev->dev_private; 5249 struct drm_i915_private *dev_priv = to_i915(dev);
5281 5250
5282 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 5251 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5283 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 5252 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
@@ -5338,7 +5307,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
5338 5307
5339static void intel_update_cdclk(struct drm_device *dev) 5308static void intel_update_cdclk(struct drm_device *dev)
5340{ 5309{
5341 struct drm_i915_private *dev_priv = dev->dev_private; 5310 struct drm_i915_private *dev_priv = to_i915(dev);
5342 5311
5343 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); 5312 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5344 5313
@@ -5395,7 +5364,9 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5395 I915_WRITE(BXT_DE_PLL_ENABLE, 0); 5364 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5396 5365
5397 /* Timeout 200us */ 5366 /* Timeout 200us */
5398 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) 5367 if (intel_wait_for_register(dev_priv,
5368 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5369 1))
5399 DRM_ERROR("timeout waiting for DE PLL unlock\n"); 5370 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5400 5371
5401 dev_priv->cdclk_pll.vco = 0; 5372 dev_priv->cdclk_pll.vco = 0;
@@ -5414,7 +5385,11 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5414 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 5385 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5415 5386
5416 /* Timeout 200us */ 5387 /* Timeout 200us */
5417 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) 5388 if (intel_wait_for_register(dev_priv,
5389 BXT_DE_PLL_ENABLE,
5390 BXT_DE_PLL_LOCK,
5391 BXT_DE_PLL_LOCK,
5392 1))
5418 DRM_ERROR("timeout waiting for DE PLL lock\n"); 5393 DRM_ERROR("timeout waiting for DE PLL lock\n");
5419 5394
5420 dev_priv->cdclk_pll.vco = vco; 5395 dev_priv->cdclk_pll.vco = vco;
@@ -5495,14 +5470,14 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5495 return; 5470 return;
5496 } 5471 }
5497 5472
5498 intel_update_cdclk(dev_priv->dev); 5473 intel_update_cdclk(&dev_priv->drm);
5499} 5474}
5500 5475
5501static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 5476static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
5502{ 5477{
5503 u32 cdctl, expected; 5478 u32 cdctl, expected;
5504 5479
5505 intel_update_cdclk(dev_priv->dev); 5480 intel_update_cdclk(&dev_priv->drm);
5506 5481
5507 if (dev_priv->cdclk_pll.vco == 0 || 5482 if (dev_priv->cdclk_pll.vco == 0 ||
5508 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) 5483 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
@@ -5635,7 +5610,7 @@ void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5635 dev_priv->skl_preferred_vco_freq = vco; 5610 dev_priv->skl_preferred_vco_freq = vco;
5636 5611
5637 if (changed) 5612 if (changed)
5638 intel_update_max_cdclk(dev_priv->dev); 5613 intel_update_max_cdclk(&dev_priv->drm);
5639} 5614}
5640 5615
5641static void 5616static void
@@ -5677,7 +5652,9 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5677 5652
5678 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); 5653 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5679 5654
5680 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) 5655 if (intel_wait_for_register(dev_priv,
5656 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
5657 5))
5681 DRM_ERROR("DPLL0 not locked\n"); 5658 DRM_ERROR("DPLL0 not locked\n");
5682 5659
5683 dev_priv->cdclk_pll.vco = vco; 5660 dev_priv->cdclk_pll.vco = vco;
@@ -5690,7 +5667,9 @@ static void
5690skl_dpll0_disable(struct drm_i915_private *dev_priv) 5667skl_dpll0_disable(struct drm_i915_private *dev_priv)
5691{ 5668{
5692 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); 5669 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5693 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) 5670 if (intel_wait_for_register(dev_priv,
5671 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
5672 1))
5694 DRM_ERROR("Couldn't disable DPLL0\n"); 5673 DRM_ERROR("Couldn't disable DPLL0\n");
5695 5674
5696 dev_priv->cdclk_pll.vco = 0; 5675 dev_priv->cdclk_pll.vco = 0;
@@ -5725,7 +5704,7 @@ static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5725 5704
5726static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) 5705static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5727{ 5706{
5728 struct drm_device *dev = dev_priv->dev; 5707 struct drm_device *dev = &dev_priv->drm;
5729 u32 freq_select, pcu_ack; 5708 u32 freq_select, pcu_ack;
5730 5709
5731 WARN_ON((cdclk == 24000) != (vco == 0)); 5710 WARN_ON((cdclk == 24000) != (vco == 0));
@@ -5823,7 +5802,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5823 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 5802 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5824 goto sanitize; 5803 goto sanitize;
5825 5804
5826 intel_update_cdclk(dev_priv->dev); 5805 intel_update_cdclk(&dev_priv->drm);
5827 /* Is PLL enabled and locked ? */ 5806 /* Is PLL enabled and locked ? */
5828 if (dev_priv->cdclk_pll.vco == 0 || 5807 if (dev_priv->cdclk_pll.vco == 0 ||
5829 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) 5808 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
@@ -5854,7 +5833,7 @@ sanitize:
5854/* Adjust CDclk dividers to allow high res or save power if possible */ 5833/* Adjust CDclk dividers to allow high res or save power if possible */
5855static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) 5834static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5856{ 5835{
5857 struct drm_i915_private *dev_priv = dev->dev_private; 5836 struct drm_i915_private *dev_priv = to_i915(dev);
5858 u32 val, cmd; 5837 u32 val, cmd;
5859 5838
5860 WARN_ON(dev_priv->display.get_display_clock_speed(dev) 5839 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
@@ -5919,7 +5898,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5919 5898
5920static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) 5899static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5921{ 5900{
5922 struct drm_i915_private *dev_priv = dev->dev_private; 5901 struct drm_i915_private *dev_priv = to_i915(dev);
5923 u32 val, cmd; 5902 u32 val, cmd;
5924 5903
5925 WARN_ON(dev_priv->display.get_display_clock_speed(dev) 5904 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
@@ -6007,7 +5986,7 @@ static int intel_mode_max_pixclk(struct drm_device *dev,
6007 struct drm_atomic_state *state) 5986 struct drm_atomic_state *state)
6008{ 5987{
6009 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 5988 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6010 struct drm_i915_private *dev_priv = dev->dev_private; 5989 struct drm_i915_private *dev_priv = to_i915(dev);
6011 struct drm_crtc *crtc; 5990 struct drm_crtc *crtc;
6012 struct drm_crtc_state *crtc_state; 5991 struct drm_crtc_state *crtc_state;
6013 unsigned max_pixclk = 0, i; 5992 unsigned max_pixclk = 0, i;
@@ -6034,7 +6013,7 @@ static int intel_mode_max_pixclk(struct drm_device *dev,
6034static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) 6013static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6035{ 6014{
6036 struct drm_device *dev = state->dev; 6015 struct drm_device *dev = state->dev;
6037 struct drm_i915_private *dev_priv = dev->dev_private; 6016 struct drm_i915_private *dev_priv = to_i915(dev);
6038 int max_pixclk = intel_mode_max_pixclk(dev, state); 6017 int max_pixclk = intel_mode_max_pixclk(dev, state);
6039 struct intel_atomic_state *intel_state = 6018 struct intel_atomic_state *intel_state =
6040 to_intel_atomic_state(state); 6019 to_intel_atomic_state(state);
@@ -6102,7 +6081,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6102static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) 6081static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6103{ 6082{
6104 struct drm_device *dev = old_state->dev; 6083 struct drm_device *dev = old_state->dev;
6105 struct drm_i915_private *dev_priv = dev->dev_private; 6084 struct drm_i915_private *dev_priv = to_i915(dev);
6106 struct intel_atomic_state *old_intel_state = 6085 struct intel_atomic_state *old_intel_state =
6107 to_intel_atomic_state(old_state); 6086 to_intel_atomic_state(old_state);
6108 unsigned req_cdclk = old_intel_state->dev_cdclk; 6087 unsigned req_cdclk = old_intel_state->dev_cdclk;
@@ -6141,14 +6120,14 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
6141 if (WARN_ON(intel_crtc->active)) 6120 if (WARN_ON(intel_crtc->active))
6142 return; 6121 return;
6143 6122
6144 if (intel_crtc->config->has_dp_encoder) 6123 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6145 intel_dp_set_m_n(intel_crtc, M1_N1); 6124 intel_dp_set_m_n(intel_crtc, M1_N1);
6146 6125
6147 intel_set_pipe_timings(intel_crtc); 6126 intel_set_pipe_timings(intel_crtc);
6148 intel_set_pipe_src_size(intel_crtc); 6127 intel_set_pipe_src_size(intel_crtc);
6149 6128
6150 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { 6129 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6151 struct drm_i915_private *dev_priv = dev->dev_private; 6130 struct drm_i915_private *dev_priv = to_i915(dev);
6152 6131
6153 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); 6132 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6154 I915_WRITE(CHV_CANVAS(pipe), 0); 6133 I915_WRITE(CHV_CANVAS(pipe), 0);
@@ -6193,7 +6172,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
6193static void i9xx_set_pll_dividers(struct intel_crtc *crtc) 6172static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6194{ 6173{
6195 struct drm_device *dev = crtc->base.dev; 6174 struct drm_device *dev = crtc->base.dev;
6196 struct drm_i915_private *dev_priv = dev->dev_private; 6175 struct drm_i915_private *dev_priv = to_i915(dev);
6197 6176
6198 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); 6177 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6199 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); 6178 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
@@ -6214,7 +6193,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
6214 6193
6215 i9xx_set_pll_dividers(intel_crtc); 6194 i9xx_set_pll_dividers(intel_crtc);
6216 6195
6217 if (intel_crtc->config->has_dp_encoder) 6196 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6218 intel_dp_set_m_n(intel_crtc, M1_N1); 6197 intel_dp_set_m_n(intel_crtc, M1_N1);
6219 6198
6220 intel_set_pipe_timings(intel_crtc); 6199 intel_set_pipe_timings(intel_crtc);
@@ -6250,7 +6229,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
6250static void i9xx_pfit_disable(struct intel_crtc *crtc) 6229static void i9xx_pfit_disable(struct intel_crtc *crtc)
6251{ 6230{
6252 struct drm_device *dev = crtc->base.dev; 6231 struct drm_device *dev = crtc->base.dev;
6253 struct drm_i915_private *dev_priv = dev->dev_private; 6232 struct drm_i915_private *dev_priv = to_i915(dev);
6254 6233
6255 if (!crtc->config->gmch_pfit.control) 6234 if (!crtc->config->gmch_pfit.control)
6256 return; 6235 return;
@@ -6265,7 +6244,7 @@ static void i9xx_pfit_disable(struct intel_crtc *crtc)
6265static void i9xx_crtc_disable(struct drm_crtc *crtc) 6244static void i9xx_crtc_disable(struct drm_crtc *crtc)
6266{ 6245{
6267 struct drm_device *dev = crtc->dev; 6246 struct drm_device *dev = crtc->dev;
6268 struct drm_i915_private *dev_priv = dev->dev_private; 6247 struct drm_i915_private *dev_priv = to_i915(dev);
6269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6270 struct intel_encoder *encoder; 6249 struct intel_encoder *encoder;
6271 int pipe = intel_crtc->pipe; 6250 int pipe = intel_crtc->pipe;
@@ -6291,7 +6270,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
6291 if (encoder->post_disable) 6270 if (encoder->post_disable)
6292 encoder->post_disable(encoder); 6271 encoder->post_disable(encoder);
6293 6272
6294 if (!intel_crtc->config->has_dsi_encoder) { 6273 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6295 if (IS_CHERRYVIEW(dev)) 6274 if (IS_CHERRYVIEW(dev))
6296 chv_disable_pll(dev_priv, pipe); 6275 chv_disable_pll(dev_priv, pipe);
6297 else if (IS_VALLEYVIEW(dev)) 6276 else if (IS_VALLEYVIEW(dev))
@@ -6609,7 +6588,7 @@ static void hsw_compute_ips_config(struct intel_crtc *crtc,
6609 struct intel_crtc_state *pipe_config) 6588 struct intel_crtc_state *pipe_config)
6610{ 6589{
6611 struct drm_device *dev = crtc->base.dev; 6590 struct drm_device *dev = crtc->base.dev;
6612 struct drm_i915_private *dev_priv = dev->dev_private; 6591 struct drm_i915_private *dev_priv = to_i915(dev);
6613 6592
6614 pipe_config->ips_enabled = i915.enable_ips && 6593 pipe_config->ips_enabled = i915.enable_ips &&
6615 hsw_crtc_supports_ips(crtc) && 6594 hsw_crtc_supports_ips(crtc) &&
@@ -6629,7 +6608,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
6629 struct intel_crtc_state *pipe_config) 6608 struct intel_crtc_state *pipe_config)
6630{ 6609{
6631 struct drm_device *dev = crtc->base.dev; 6610 struct drm_device *dev = crtc->base.dev;
6632 struct drm_i915_private *dev_priv = dev->dev_private; 6611 struct drm_i915_private *dev_priv = to_i915(dev);
6633 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 6612 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6634 int clock_limit = dev_priv->max_dotclk_freq; 6613 int clock_limit = dev_priv->max_dotclk_freq;
6635 6614
@@ -6660,7 +6639,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
6660 * - LVDS dual channel mode 6639 * - LVDS dual channel mode
6661 * - Double wide pipe 6640 * - Double wide pipe
6662 */ 6641 */
6663 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && 6642 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6664 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) 6643 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6665 pipe_config->pipe_src_w &= ~1; 6644 pipe_config->pipe_src_w &= ~1;
6666 6645
@@ -6779,7 +6758,7 @@ static int broxton_get_display_clock_speed(struct drm_device *dev)
6779 6758
6780static int broadwell_get_display_clock_speed(struct drm_device *dev) 6759static int broadwell_get_display_clock_speed(struct drm_device *dev)
6781{ 6760{
6782 struct drm_i915_private *dev_priv = dev->dev_private; 6761 struct drm_i915_private *dev_priv = to_i915(dev);
6783 uint32_t lcpll = I915_READ(LCPLL_CTL); 6762 uint32_t lcpll = I915_READ(LCPLL_CTL);
6784 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 6763 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6785 6764
@@ -6799,7 +6778,7 @@ static int broadwell_get_display_clock_speed(struct drm_device *dev)
6799 6778
6800static int haswell_get_display_clock_speed(struct drm_device *dev) 6779static int haswell_get_display_clock_speed(struct drm_device *dev)
6801{ 6780{
6802 struct drm_i915_private *dev_priv = dev->dev_private; 6781 struct drm_i915_private *dev_priv = to_i915(dev);
6803 uint32_t lcpll = I915_READ(LCPLL_CTL); 6782 uint32_t lcpll = I915_READ(LCPLL_CTL);
6804 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 6783 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6805 6784
@@ -6933,7 +6912,7 @@ static int i830_get_display_clock_speed(struct drm_device *dev)
6933 6912
6934static unsigned int intel_hpll_vco(struct drm_device *dev) 6913static unsigned int intel_hpll_vco(struct drm_device *dev)
6935{ 6914{
6936 struct drm_i915_private *dev_priv = dev->dev_private; 6915 struct drm_i915_private *dev_priv = to_i915(dev);
6937 static const unsigned int blb_vco[8] = { 6916 static const unsigned int blb_vco[8] = {
6938 [0] = 3200000, 6917 [0] = 3200000,
6939 [1] = 4000000, 6918 [1] = 4000000,
@@ -7171,7 +7150,7 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7171 crtc_state->dpll_hw_state.fp0 = fp; 7150 crtc_state->dpll_hw_state.fp0 = fp;
7172 7151
7173 crtc->lowfreq_avail = false; 7152 crtc->lowfreq_avail = false;
7174 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && 7153 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7175 reduced_clock) { 7154 reduced_clock) {
7176 crtc_state->dpll_hw_state.fp1 = fp2; 7155 crtc_state->dpll_hw_state.fp1 = fp2;
7177 crtc->lowfreq_avail = true; 7156 crtc->lowfreq_avail = true;
@@ -7213,7 +7192,7 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7213 struct intel_link_m_n *m_n) 7192 struct intel_link_m_n *m_n)
7214{ 7193{
7215 struct drm_device *dev = crtc->base.dev; 7194 struct drm_device *dev = crtc->base.dev;
7216 struct drm_i915_private *dev_priv = dev->dev_private; 7195 struct drm_i915_private *dev_priv = to_i915(dev);
7217 int pipe = crtc->pipe; 7196 int pipe = crtc->pipe;
7218 7197
7219 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); 7198 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
@@ -7227,7 +7206,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7227 struct intel_link_m_n *m2_n2) 7206 struct intel_link_m_n *m2_n2)
7228{ 7207{
7229 struct drm_device *dev = crtc->base.dev; 7208 struct drm_device *dev = crtc->base.dev;
7230 struct drm_i915_private *dev_priv = dev->dev_private; 7209 struct drm_i915_private *dev_priv = to_i915(dev);
7231 int pipe = crtc->pipe; 7210 int pipe = crtc->pipe;
7232 enum transcoder transcoder = crtc->config->cpu_transcoder; 7211 enum transcoder transcoder = crtc->config->cpu_transcoder;
7233 7212
@@ -7290,7 +7269,7 @@ static void vlv_compute_dpll(struct intel_crtc *crtc,
7290 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 7269 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7291 7270
7292 /* DPLL not used with DSI, but still need the rest set up */ 7271 /* DPLL not used with DSI, but still need the rest set up */
7293 if (!pipe_config->has_dsi_encoder) 7272 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7294 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | 7273 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7295 DPLL_EXT_BUFFER_ENABLE_VLV; 7274 DPLL_EXT_BUFFER_ENABLE_VLV;
7296 7275
@@ -7307,7 +7286,7 @@ static void chv_compute_dpll(struct intel_crtc *crtc,
7307 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 7286 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7308 7287
7309 /* DPLL not used with DSI, but still need the rest set up */ 7288 /* DPLL not used with DSI, but still need the rest set up */
7310 if (!pipe_config->has_dsi_encoder) 7289 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7311 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; 7290 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7312 7291
7313 pipe_config->dpll_hw_state.dpll_md = 7292 pipe_config->dpll_hw_state.dpll_md =
@@ -7318,7 +7297,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
7318 const struct intel_crtc_state *pipe_config) 7297 const struct intel_crtc_state *pipe_config)
7319{ 7298{
7320 struct drm_device *dev = crtc->base.dev; 7299 struct drm_device *dev = crtc->base.dev;
7321 struct drm_i915_private *dev_priv = dev->dev_private; 7300 struct drm_i915_private *dev_priv = to_i915(dev);
7322 enum pipe pipe = crtc->pipe; 7301 enum pipe pipe = crtc->pipe;
7323 u32 mdiv; 7302 u32 mdiv;
7324 u32 bestn, bestm1, bestm2, bestp1, bestp2; 7303 u32 bestn, bestm1, bestm2, bestp1, bestp2;
@@ -7377,15 +7356,15 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
7377 7356
7378 /* Set HBR and RBR LPF coefficients */ 7357 /* Set HBR and RBR LPF coefficients */
7379 if (pipe_config->port_clock == 162000 || 7358 if (pipe_config->port_clock == 162000 ||
7380 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || 7359 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7381 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) 7360 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7382 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 7361 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7383 0x009f0003); 7362 0x009f0003);
7384 else 7363 else
7385 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 7364 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7386 0x00d0000f); 7365 0x00d0000f);
7387 7366
7388 if (pipe_config->has_dp_encoder) { 7367 if (intel_crtc_has_dp_encoder(pipe_config)) {
7389 /* Use SSC source */ 7368 /* Use SSC source */
7390 if (pipe == PIPE_A) 7369 if (pipe == PIPE_A)
7391 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 7370 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
@@ -7405,8 +7384,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
7405 7384
7406 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); 7385 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7407 coreclk = (coreclk & 0x0000ff00) | 0x01c00000; 7386 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 7387 if (intel_crtc_has_dp_encoder(crtc->config))
7409 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7410 coreclk |= 0x01000000; 7388 coreclk |= 0x01000000;
7411 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); 7389 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7412 7390
@@ -7418,7 +7396,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
7418 const struct intel_crtc_state *pipe_config) 7396 const struct intel_crtc_state *pipe_config)
7419{ 7397{
7420 struct drm_device *dev = crtc->base.dev; 7398 struct drm_device *dev = crtc->base.dev;
7421 struct drm_i915_private *dev_priv = dev->dev_private; 7399 struct drm_i915_private *dev_priv = to_i915(dev);
7422 enum pipe pipe = crtc->pipe; 7400 enum pipe pipe = crtc->pipe;
7423 enum dpio_channel port = vlv_pipe_to_channel(pipe); 7401 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7424 u32 loopfilter, tribuf_calcntr; 7402 u32 loopfilter, tribuf_calcntr;
@@ -7580,19 +7558,15 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
7580 struct dpll *reduced_clock) 7558 struct dpll *reduced_clock)
7581{ 7559{
7582 struct drm_device *dev = crtc->base.dev; 7560 struct drm_device *dev = crtc->base.dev;
7583 struct drm_i915_private *dev_priv = dev->dev_private; 7561 struct drm_i915_private *dev_priv = to_i915(dev);
7584 u32 dpll; 7562 u32 dpll;
7585 bool is_sdvo;
7586 struct dpll *clock = &crtc_state->dpll; 7563 struct dpll *clock = &crtc_state->dpll;
7587 7564
7588 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); 7565 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7589 7566
7590 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7591 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7592
7593 dpll = DPLL_VGA_MODE_DIS; 7567 dpll = DPLL_VGA_MODE_DIS;
7594 7568
7595 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) 7569 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7596 dpll |= DPLLB_MODE_LVDS; 7570 dpll |= DPLLB_MODE_LVDS;
7597 else 7571 else
7598 dpll |= DPLLB_MODE_DAC_SERIAL; 7572 dpll |= DPLLB_MODE_DAC_SERIAL;
@@ -7602,10 +7576,11 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
7602 << SDVO_MULTIPLIER_SHIFT_HIRES; 7576 << SDVO_MULTIPLIER_SHIFT_HIRES;
7603 } 7577 }
7604 7578
7605 if (is_sdvo) 7579 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7580 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7606 dpll |= DPLL_SDVO_HIGH_SPEED; 7581 dpll |= DPLL_SDVO_HIGH_SPEED;
7607 7582
7608 if (crtc_state->has_dp_encoder) 7583 if (intel_crtc_has_dp_encoder(crtc_state))
7609 dpll |= DPLL_SDVO_HIGH_SPEED; 7584 dpll |= DPLL_SDVO_HIGH_SPEED;
7610 7585
7611 /* compute bitmask from p1 value */ 7586 /* compute bitmask from p1 value */
@@ -7635,7 +7610,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
7635 7610
7636 if (crtc_state->sdvo_tv_clock) 7611 if (crtc_state->sdvo_tv_clock)
7637 dpll |= PLL_REF_INPUT_TVCLKINBC; 7612 dpll |= PLL_REF_INPUT_TVCLKINBC;
7638 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && 7613 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7639 intel_panel_use_ssc(dev_priv)) 7614 intel_panel_use_ssc(dev_priv))
7640 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 7615 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7641 else 7616 else
@@ -7656,7 +7631,7 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
7656 struct dpll *reduced_clock) 7631 struct dpll *reduced_clock)
7657{ 7632{
7658 struct drm_device *dev = crtc->base.dev; 7633 struct drm_device *dev = crtc->base.dev;
7659 struct drm_i915_private *dev_priv = dev->dev_private; 7634 struct drm_i915_private *dev_priv = to_i915(dev);
7660 u32 dpll; 7635 u32 dpll;
7661 struct dpll *clock = &crtc_state->dpll; 7636 struct dpll *clock = &crtc_state->dpll;
7662 7637
@@ -7664,7 +7639,7 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
7664 7639
7665 dpll = DPLL_VGA_MODE_DIS; 7640 dpll = DPLL_VGA_MODE_DIS;
7666 7641
7667 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { 7642 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7668 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 7643 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7669 } else { 7644 } else {
7670 if (clock->p1 == 2) 7645 if (clock->p1 == 2)
@@ -7675,10 +7650,10 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
7675 dpll |= PLL_P2_DIVIDE_BY_4; 7650 dpll |= PLL_P2_DIVIDE_BY_4;
7676 } 7651 }
7677 7652
7678 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) 7653 if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7679 dpll |= DPLL_DVO_2X_MODE; 7654 dpll |= DPLL_DVO_2X_MODE;
7680 7655
7681 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && 7656 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7682 intel_panel_use_ssc(dev_priv)) 7657 intel_panel_use_ssc(dev_priv))
7683 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 7658 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7684 else 7659 else
@@ -7691,7 +7666,7 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
7691static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) 7666static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7692{ 7667{
7693 struct drm_device *dev = intel_crtc->base.dev; 7668 struct drm_device *dev = intel_crtc->base.dev;
7694 struct drm_i915_private *dev_priv = dev->dev_private; 7669 struct drm_i915_private *dev_priv = to_i915(dev);
7695 enum pipe pipe = intel_crtc->pipe; 7670 enum pipe pipe = intel_crtc->pipe;
7696 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 7671 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7697 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 7672 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
@@ -7708,7 +7683,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7708 crtc_vtotal -= 1; 7683 crtc_vtotal -= 1;
7709 crtc_vblank_end -= 1; 7684 crtc_vblank_end -= 1;
7710 7685
7711 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) 7686 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7712 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 7687 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7713 else 7688 else
7714 vsyncshift = adjusted_mode->crtc_hsync_start - 7689 vsyncshift = adjusted_mode->crtc_hsync_start -
@@ -7753,7 +7728,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7753static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) 7728static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7754{ 7729{
7755 struct drm_device *dev = intel_crtc->base.dev; 7730 struct drm_device *dev = intel_crtc->base.dev;
7756 struct drm_i915_private *dev_priv = dev->dev_private; 7731 struct drm_i915_private *dev_priv = to_i915(dev);
7757 enum pipe pipe = intel_crtc->pipe; 7732 enum pipe pipe = intel_crtc->pipe;
7758 7733
7759 /* pipesrc controls the size that is scaled from, which should 7734 /* pipesrc controls the size that is scaled from, which should
@@ -7768,7 +7743,7 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
7768 struct intel_crtc_state *pipe_config) 7743 struct intel_crtc_state *pipe_config)
7769{ 7744{
7770 struct drm_device *dev = crtc->base.dev; 7745 struct drm_device *dev = crtc->base.dev;
7771 struct drm_i915_private *dev_priv = dev->dev_private; 7746 struct drm_i915_private *dev_priv = to_i915(dev);
7772 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 7747 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7773 uint32_t tmp; 7748 uint32_t tmp;
7774 7749
@@ -7803,7 +7778,7 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7803 struct intel_crtc_state *pipe_config) 7778 struct intel_crtc_state *pipe_config)
7804{ 7779{
7805 struct drm_device *dev = crtc->base.dev; 7780 struct drm_device *dev = crtc->base.dev;
7806 struct drm_i915_private *dev_priv = dev->dev_private; 7781 struct drm_i915_private *dev_priv = to_i915(dev);
7807 u32 tmp; 7782 u32 tmp;
7808 7783
7809 tmp = I915_READ(PIPESRC(crtc->pipe)); 7784 tmp = I915_READ(PIPESRC(crtc->pipe));
@@ -7841,7 +7816,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7841static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) 7816static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7842{ 7817{
7843 struct drm_device *dev = intel_crtc->base.dev; 7818 struct drm_device *dev = intel_crtc->base.dev;
7844 struct drm_i915_private *dev_priv = dev->dev_private; 7819 struct drm_i915_private *dev_priv = to_i915(dev);
7845 uint32_t pipeconf; 7820 uint32_t pipeconf;
7846 7821
7847 pipeconf = 0; 7822 pipeconf = 0;
@@ -7887,7 +7862,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7887 7862
7888 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 7863 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7889 if (INTEL_INFO(dev)->gen < 4 || 7864 if (INTEL_INFO(dev)->gen < 4 ||
7890 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) 7865 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7891 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 7866 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7892 else 7867 else
7893 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 7868 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
@@ -7906,21 +7881,21 @@ static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7906 struct intel_crtc_state *crtc_state) 7881 struct intel_crtc_state *crtc_state)
7907{ 7882{
7908 struct drm_device *dev = crtc->base.dev; 7883 struct drm_device *dev = crtc->base.dev;
7909 struct drm_i915_private *dev_priv = dev->dev_private; 7884 struct drm_i915_private *dev_priv = to_i915(dev);
7910 const struct intel_limit *limit; 7885 const struct intel_limit *limit;
7911 int refclk = 48000; 7886 int refclk = 48000;
7912 7887
7913 memset(&crtc_state->dpll_hw_state, 0, 7888 memset(&crtc_state->dpll_hw_state, 0,
7914 sizeof(crtc_state->dpll_hw_state)); 7889 sizeof(crtc_state->dpll_hw_state));
7915 7890
7916 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { 7891 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7917 if (intel_panel_use_ssc(dev_priv)) { 7892 if (intel_panel_use_ssc(dev_priv)) {
7918 refclk = dev_priv->vbt.lvds_ssc_freq; 7893 refclk = dev_priv->vbt.lvds_ssc_freq;
7919 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); 7894 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7920 } 7895 }
7921 7896
7922 limit = &intel_limits_i8xx_lvds; 7897 limit = &intel_limits_i8xx_lvds;
7923 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) { 7898 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7924 limit = &intel_limits_i8xx_dvo; 7899 limit = &intel_limits_i8xx_dvo;
7925 } else { 7900 } else {
7926 limit = &intel_limits_i8xx_dac; 7901 limit = &intel_limits_i8xx_dac;
@@ -7942,14 +7917,14 @@ static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7942 struct intel_crtc_state *crtc_state) 7917 struct intel_crtc_state *crtc_state)
7943{ 7918{
7944 struct drm_device *dev = crtc->base.dev; 7919 struct drm_device *dev = crtc->base.dev;
7945 struct drm_i915_private *dev_priv = dev->dev_private; 7920 struct drm_i915_private *dev_priv = to_i915(dev);
7946 const struct intel_limit *limit; 7921 const struct intel_limit *limit;
7947 int refclk = 96000; 7922 int refclk = 96000;
7948 7923
7949 memset(&crtc_state->dpll_hw_state, 0, 7924 memset(&crtc_state->dpll_hw_state, 0,
7950 sizeof(crtc_state->dpll_hw_state)); 7925 sizeof(crtc_state->dpll_hw_state));
7951 7926
7952 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { 7927 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7953 if (intel_panel_use_ssc(dev_priv)) { 7928 if (intel_panel_use_ssc(dev_priv)) {
7954 refclk = dev_priv->vbt.lvds_ssc_freq; 7929 refclk = dev_priv->vbt.lvds_ssc_freq;
7955 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); 7930 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
@@ -7959,10 +7934,10 @@ static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7959 limit = &intel_limits_g4x_dual_channel_lvds; 7934 limit = &intel_limits_g4x_dual_channel_lvds;
7960 else 7935 else
7961 limit = &intel_limits_g4x_single_channel_lvds; 7936 limit = &intel_limits_g4x_single_channel_lvds;
7962 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || 7937 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7963 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 7938 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7964 limit = &intel_limits_g4x_hdmi; 7939 limit = &intel_limits_g4x_hdmi;
7965 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { 7940 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7966 limit = &intel_limits_g4x_sdvo; 7941 limit = &intel_limits_g4x_sdvo;
7967 } else { 7942 } else {
7968 /* The option is for other outputs */ 7943 /* The option is for other outputs */
@@ -7985,14 +7960,14 @@ static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7985 struct intel_crtc_state *crtc_state) 7960 struct intel_crtc_state *crtc_state)
7986{ 7961{
7987 struct drm_device *dev = crtc->base.dev; 7962 struct drm_device *dev = crtc->base.dev;
7988 struct drm_i915_private *dev_priv = dev->dev_private; 7963 struct drm_i915_private *dev_priv = to_i915(dev);
7989 const struct intel_limit *limit; 7964 const struct intel_limit *limit;
7990 int refclk = 96000; 7965 int refclk = 96000;
7991 7966
7992 memset(&crtc_state->dpll_hw_state, 0, 7967 memset(&crtc_state->dpll_hw_state, 0,
7993 sizeof(crtc_state->dpll_hw_state)); 7968 sizeof(crtc_state->dpll_hw_state));
7994 7969
7995 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { 7970 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7996 if (intel_panel_use_ssc(dev_priv)) { 7971 if (intel_panel_use_ssc(dev_priv)) {
7997 refclk = dev_priv->vbt.lvds_ssc_freq; 7972 refclk = dev_priv->vbt.lvds_ssc_freq;
7998 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); 7973 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
@@ -8019,14 +7994,14 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8019 struct intel_crtc_state *crtc_state) 7994 struct intel_crtc_state *crtc_state)
8020{ 7995{
8021 struct drm_device *dev = crtc->base.dev; 7996 struct drm_device *dev = crtc->base.dev;
8022 struct drm_i915_private *dev_priv = dev->dev_private; 7997 struct drm_i915_private *dev_priv = to_i915(dev);
8023 const struct intel_limit *limit; 7998 const struct intel_limit *limit;
8024 int refclk = 96000; 7999 int refclk = 96000;
8025 8000
8026 memset(&crtc_state->dpll_hw_state, 0, 8001 memset(&crtc_state->dpll_hw_state, 0,
8027 sizeof(crtc_state->dpll_hw_state)); 8002 sizeof(crtc_state->dpll_hw_state));
8028 8003
8029 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { 8004 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8030 if (intel_panel_use_ssc(dev_priv)) { 8005 if (intel_panel_use_ssc(dev_priv)) {
8031 refclk = dev_priv->vbt.lvds_ssc_freq; 8006 refclk = dev_priv->vbt.lvds_ssc_freq;
8032 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); 8007 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
@@ -8095,7 +8070,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8095 struct intel_crtc_state *pipe_config) 8070 struct intel_crtc_state *pipe_config)
8096{ 8071{
8097 struct drm_device *dev = crtc->base.dev; 8072 struct drm_device *dev = crtc->base.dev;
8098 struct drm_i915_private *dev_priv = dev->dev_private; 8073 struct drm_i915_private *dev_priv = to_i915(dev);
8099 uint32_t tmp; 8074 uint32_t tmp;
8100 8075
8101 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) 8076 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
@@ -8122,7 +8097,7 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8122 struct intel_crtc_state *pipe_config) 8097 struct intel_crtc_state *pipe_config)
8123{ 8098{
8124 struct drm_device *dev = crtc->base.dev; 8099 struct drm_device *dev = crtc->base.dev;
8125 struct drm_i915_private *dev_priv = dev->dev_private; 8100 struct drm_i915_private *dev_priv = to_i915(dev);
8126 int pipe = pipe_config->cpu_transcoder; 8101 int pipe = pipe_config->cpu_transcoder;
8127 struct dpll clock; 8102 struct dpll clock;
8128 u32 mdiv; 8103 u32 mdiv;
@@ -8150,7 +8125,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8150 struct intel_initial_plane_config *plane_config) 8125 struct intel_initial_plane_config *plane_config)
8151{ 8126{
8152 struct drm_device *dev = crtc->base.dev; 8127 struct drm_device *dev = crtc->base.dev;
8153 struct drm_i915_private *dev_priv = dev->dev_private; 8128 struct drm_i915_private *dev_priv = to_i915(dev);
8154 u32 val, base, offset; 8129 u32 val, base, offset;
8155 int pipe = crtc->pipe, plane = crtc->plane; 8130 int pipe = crtc->pipe, plane = crtc->plane;
8156 int fourcc, pixel_format; 8131 int fourcc, pixel_format;
@@ -8218,7 +8193,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
8218 struct intel_crtc_state *pipe_config) 8193 struct intel_crtc_state *pipe_config)
8219{ 8194{
8220 struct drm_device *dev = crtc->base.dev; 8195 struct drm_device *dev = crtc->base.dev;
8221 struct drm_i915_private *dev_priv = dev->dev_private; 8196 struct drm_i915_private *dev_priv = to_i915(dev);
8222 int pipe = pipe_config->cpu_transcoder; 8197 int pipe = pipe_config->cpu_transcoder;
8223 enum dpio_channel port = vlv_pipe_to_channel(pipe); 8198 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8224 struct dpll clock; 8199 struct dpll clock;
@@ -8252,7 +8227,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8252 struct intel_crtc_state *pipe_config) 8227 struct intel_crtc_state *pipe_config)
8253{ 8228{
8254 struct drm_device *dev = crtc->base.dev; 8229 struct drm_device *dev = crtc->base.dev;
8255 struct drm_i915_private *dev_priv = dev->dev_private; 8230 struct drm_i915_private *dev_priv = to_i915(dev);
8256 enum intel_display_power_domain power_domain; 8231 enum intel_display_power_domain power_domain;
8257 uint32_t tmp; 8232 uint32_t tmp;
8258 bool ret; 8233 bool ret;
@@ -8363,7 +8338,7 @@ out:
8363 8338
8364static void ironlake_init_pch_refclk(struct drm_device *dev) 8339static void ironlake_init_pch_refclk(struct drm_device *dev)
8365{ 8340{
8366 struct drm_i915_private *dev_priv = dev->dev_private; 8341 struct drm_i915_private *dev_priv = to_i915(dev);
8367 struct intel_encoder *encoder; 8342 struct intel_encoder *encoder;
8368 int i; 8343 int i;
8369 u32 val, final; 8344 u32 val, final;
@@ -8537,16 +8512,16 @@ static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8537 tmp |= FDI_MPHY_IOSFSB_RESET_CTL; 8512 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8538 I915_WRITE(SOUTH_CHICKEN2, tmp); 8513 I915_WRITE(SOUTH_CHICKEN2, tmp);
8539 8514
8540 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & 8515 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8541 FDI_MPHY_IOSFSB_RESET_STATUS, 100)) 8516 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8542 DRM_ERROR("FDI mPHY reset assert timeout\n"); 8517 DRM_ERROR("FDI mPHY reset assert timeout\n");
8543 8518
8544 tmp = I915_READ(SOUTH_CHICKEN2); 8519 tmp = I915_READ(SOUTH_CHICKEN2);
8545 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; 8520 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8546 I915_WRITE(SOUTH_CHICKEN2, tmp); 8521 I915_WRITE(SOUTH_CHICKEN2, tmp);
8547 8522
8548 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & 8523 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8549 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) 8524 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8550 DRM_ERROR("FDI mPHY reset de-assert timeout\n"); 8525 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8551} 8526}
8552 8527
@@ -8634,7 +8609,7 @@ static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8634static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, 8609static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8635 bool with_fdi) 8610 bool with_fdi)
8636{ 8611{
8637 struct drm_i915_private *dev_priv = dev->dev_private; 8612 struct drm_i915_private *dev_priv = to_i915(dev);
8638 uint32_t reg, tmp; 8613 uint32_t reg, tmp;
8639 8614
8640 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) 8615 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
@@ -8673,7 +8648,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8673/* Sequence to disable CLKOUT_DP */ 8648/* Sequence to disable CLKOUT_DP */
8674static void lpt_disable_clkout_dp(struct drm_device *dev) 8649static void lpt_disable_clkout_dp(struct drm_device *dev)
8675{ 8650{
8676 struct drm_i915_private *dev_priv = dev->dev_private; 8651 struct drm_i915_private *dev_priv = to_i915(dev);
8677 uint32_t reg, tmp; 8652 uint32_t reg, tmp;
8678 8653
8679 mutex_lock(&dev_priv->sb_lock); 8654 mutex_lock(&dev_priv->sb_lock);
@@ -8794,7 +8769,7 @@ void intel_init_pch_refclk(struct drm_device *dev)
8794 8769
8795static void ironlake_set_pipeconf(struct drm_crtc *crtc) 8770static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8796{ 8771{
8797 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 8772 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 8773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8799 int pipe = intel_crtc->pipe; 8774 int pipe = intel_crtc->pipe;
8800 uint32_t val; 8775 uint32_t val;
@@ -8836,7 +8811,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8836 8811
8837static void haswell_set_pipeconf(struct drm_crtc *crtc) 8812static void haswell_set_pipeconf(struct drm_crtc *crtc)
8838{ 8813{
8839 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 8814 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 8815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8841 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 8816 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8842 u32 val = 0; 8817 u32 val = 0;
@@ -8855,7 +8830,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
8855 8830
8856static void haswell_set_pipemisc(struct drm_crtc *crtc) 8831static void haswell_set_pipemisc(struct drm_crtc *crtc)
8857{ 8832{
8858 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 8833 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 8834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8860 8835
8861 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { 8836 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
@@ -8908,37 +8883,13 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8908{ 8883{
8909 struct drm_crtc *crtc = &intel_crtc->base; 8884 struct drm_crtc *crtc = &intel_crtc->base;
8910 struct drm_device *dev = crtc->dev; 8885 struct drm_device *dev = crtc->dev;
8911 struct drm_i915_private *dev_priv = dev->dev_private; 8886 struct drm_i915_private *dev_priv = to_i915(dev);
8912 struct drm_atomic_state *state = crtc_state->base.state;
8913 struct drm_connector *connector;
8914 struct drm_connector_state *connector_state;
8915 struct intel_encoder *encoder;
8916 u32 dpll, fp, fp2; 8887 u32 dpll, fp, fp2;
8917 int factor, i; 8888 int factor;
8918 bool is_lvds = false, is_sdvo = false;
8919
8920 for_each_connector_in_state(state, connector, connector_state, i) {
8921 if (connector_state->crtc != crtc_state->base.crtc)
8922 continue;
8923
8924 encoder = to_intel_encoder(connector_state->best_encoder);
8925
8926 switch (encoder->type) {
8927 case INTEL_OUTPUT_LVDS:
8928 is_lvds = true;
8929 break;
8930 case INTEL_OUTPUT_SDVO:
8931 case INTEL_OUTPUT_HDMI:
8932 is_sdvo = true;
8933 break;
8934 default:
8935 break;
8936 }
8937 }
8938 8889
8939 /* Enable autotuning of the PLL clock (if permissible) */ 8890 /* Enable autotuning of the PLL clock (if permissible) */
8940 factor = 21; 8891 factor = 21;
8941 if (is_lvds) { 8892 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8942 if ((intel_panel_use_ssc(dev_priv) && 8893 if ((intel_panel_use_ssc(dev_priv) &&
8943 dev_priv->vbt.lvds_ssc_freq == 100000) || 8894 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8944 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) 8895 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
@@ -8962,7 +8913,7 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8962 8913
8963 dpll = 0; 8914 dpll = 0;
8964 8915
8965 if (is_lvds) 8916 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8966 dpll |= DPLLB_MODE_LVDS; 8917 dpll |= DPLLB_MODE_LVDS;
8967 else 8918 else
8968 dpll |= DPLLB_MODE_DAC_SERIAL; 8919 dpll |= DPLLB_MODE_DAC_SERIAL;
@@ -8970,9 +8921,11 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8970 dpll |= (crtc_state->pixel_multiplier - 1) 8921 dpll |= (crtc_state->pixel_multiplier - 1)
8971 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 8922 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8972 8923
8973 if (is_sdvo) 8924 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8925 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8974 dpll |= DPLL_SDVO_HIGH_SPEED; 8926 dpll |= DPLL_SDVO_HIGH_SPEED;
8975 if (crtc_state->has_dp_encoder) 8927
8928 if (intel_crtc_has_dp_encoder(crtc_state))
8976 dpll |= DPLL_SDVO_HIGH_SPEED; 8929 dpll |= DPLL_SDVO_HIGH_SPEED;
8977 8930
8978 /* compute bitmask from p1 value */ 8931 /* compute bitmask from p1 value */
@@ -8995,7 +8948,8 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8995 break; 8948 break;
8996 } 8949 }
8997 8950
8998 if (is_lvds && intel_panel_use_ssc(dev_priv)) 8951 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8952 intel_panel_use_ssc(dev_priv))
8999 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 8953 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9000 else 8954 else
9001 dpll |= PLL_REF_INPUT_DREFCLK; 8955 dpll |= PLL_REF_INPUT_DREFCLK;
@@ -9011,7 +8965,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9011 struct intel_crtc_state *crtc_state) 8965 struct intel_crtc_state *crtc_state)
9012{ 8966{
9013 struct drm_device *dev = crtc->base.dev; 8967 struct drm_device *dev = crtc->base.dev;
9014 struct drm_i915_private *dev_priv = dev->dev_private; 8968 struct drm_i915_private *dev_priv = to_i915(dev);
9015 struct dpll reduced_clock; 8969 struct dpll reduced_clock;
9016 bool has_reduced_clock = false; 8970 bool has_reduced_clock = false;
9017 struct intel_shared_dpll *pll; 8971 struct intel_shared_dpll *pll;
@@ -9027,7 +8981,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9027 if (!crtc_state->has_pch_encoder) 8981 if (!crtc_state->has_pch_encoder)
9028 return 0; 8982 return 0;
9029 8983
9030 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { 8984 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9031 if (intel_panel_use_ssc(dev_priv)) { 8985 if (intel_panel_use_ssc(dev_priv)) {
9032 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", 8986 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9033 dev_priv->vbt.lvds_ssc_freq); 8987 dev_priv->vbt.lvds_ssc_freq);
@@ -9066,7 +9020,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9066 return -EINVAL; 9020 return -EINVAL;
9067 } 9021 }
9068 9022
9069 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && 9023 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9070 has_reduced_clock) 9024 has_reduced_clock)
9071 crtc->lowfreq_avail = true; 9025 crtc->lowfreq_avail = true;
9072 9026
@@ -9077,7 +9031,7 @@ static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9077 struct intel_link_m_n *m_n) 9031 struct intel_link_m_n *m_n)
9078{ 9032{
9079 struct drm_device *dev = crtc->base.dev; 9033 struct drm_device *dev = crtc->base.dev;
9080 struct drm_i915_private *dev_priv = dev->dev_private; 9034 struct drm_i915_private *dev_priv = to_i915(dev);
9081 enum pipe pipe = crtc->pipe; 9035 enum pipe pipe = crtc->pipe;
9082 9036
9083 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); 9037 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
@@ -9095,7 +9049,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9095 struct intel_link_m_n *m2_n2) 9049 struct intel_link_m_n *m2_n2)
9096{ 9050{
9097 struct drm_device *dev = crtc->base.dev; 9051 struct drm_device *dev = crtc->base.dev;
9098 struct drm_i915_private *dev_priv = dev->dev_private; 9052 struct drm_i915_private *dev_priv = to_i915(dev);
9099 enum pipe pipe = crtc->pipe; 9053 enum pipe pipe = crtc->pipe;
9100 9054
9101 if (INTEL_INFO(dev)->gen >= 5) { 9055 if (INTEL_INFO(dev)->gen >= 5) {
@@ -9153,7 +9107,7 @@ static void skylake_get_pfit_config(struct intel_crtc *crtc,
9153 struct intel_crtc_state *pipe_config) 9107 struct intel_crtc_state *pipe_config)
9154{ 9108{
9155 struct drm_device *dev = crtc->base.dev; 9109 struct drm_device *dev = crtc->base.dev;
9156 struct drm_i915_private *dev_priv = dev->dev_private; 9110 struct drm_i915_private *dev_priv = to_i915(dev);
9157 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; 9111 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9158 uint32_t ps_ctrl = 0; 9112 uint32_t ps_ctrl = 0;
9159 int id = -1; 9113 int id = -1;
@@ -9184,7 +9138,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
9184 struct intel_initial_plane_config *plane_config) 9138 struct intel_initial_plane_config *plane_config)
9185{ 9139{
9186 struct drm_device *dev = crtc->base.dev; 9140 struct drm_device *dev = crtc->base.dev;
9187 struct drm_i915_private *dev_priv = dev->dev_private; 9141 struct drm_i915_private *dev_priv = to_i915(dev);
9188 u32 val, base, offset, stride_mult, tiling; 9142 u32 val, base, offset, stride_mult, tiling;
9189 int pipe = crtc->pipe; 9143 int pipe = crtc->pipe;
9190 int fourcc, pixel_format; 9144 int fourcc, pixel_format;
@@ -9267,7 +9221,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9267 struct intel_crtc_state *pipe_config) 9221 struct intel_crtc_state *pipe_config)
9268{ 9222{
9269 struct drm_device *dev = crtc->base.dev; 9223 struct drm_device *dev = crtc->base.dev;
9270 struct drm_i915_private *dev_priv = dev->dev_private; 9224 struct drm_i915_private *dev_priv = to_i915(dev);
9271 uint32_t tmp; 9225 uint32_t tmp;
9272 9226
9273 tmp = I915_READ(PF_CTL(crtc->pipe)); 9227 tmp = I915_READ(PF_CTL(crtc->pipe));
@@ -9292,7 +9246,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9292 struct intel_initial_plane_config *plane_config) 9246 struct intel_initial_plane_config *plane_config)
9293{ 9247{
9294 struct drm_device *dev = crtc->base.dev; 9248 struct drm_device *dev = crtc->base.dev;
9295 struct drm_i915_private *dev_priv = dev->dev_private; 9249 struct drm_i915_private *dev_priv = to_i915(dev);
9296 u32 val, base, offset; 9250 u32 val, base, offset;
9297 int pipe = crtc->pipe; 9251 int pipe = crtc->pipe;
9298 int fourcc, pixel_format; 9252 int fourcc, pixel_format;
@@ -9360,7 +9314,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9360 struct intel_crtc_state *pipe_config) 9314 struct intel_crtc_state *pipe_config)
9361{ 9315{
9362 struct drm_device *dev = crtc->base.dev; 9316 struct drm_device *dev = crtc->base.dev;
9363 struct drm_i915_private *dev_priv = dev->dev_private; 9317 struct drm_i915_private *dev_priv = to_i915(dev);
9364 enum intel_display_power_domain power_domain; 9318 enum intel_display_power_domain power_domain;
9365 uint32_t tmp; 9319 uint32_t tmp;
9366 bool ret; 9320 bool ret;
@@ -9455,7 +9409,7 @@ out:
9455 9409
9456static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) 9410static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9457{ 9411{
9458 struct drm_device *dev = dev_priv->dev; 9412 struct drm_device *dev = &dev_priv->drm;
9459 struct intel_crtc *crtc; 9413 struct intel_crtc *crtc;
9460 9414
9461 for_each_intel_crtc(dev, crtc) 9415 for_each_intel_crtc(dev, crtc)
@@ -9489,7 +9443,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9489 9443
9490static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) 9444static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9491{ 9445{
9492 struct drm_device *dev = dev_priv->dev; 9446 struct drm_device *dev = &dev_priv->drm;
9493 9447
9494 if (IS_HASWELL(dev)) 9448 if (IS_HASWELL(dev))
9495 return I915_READ(D_COMP_HSW); 9449 return I915_READ(D_COMP_HSW);
@@ -9499,7 +9453,7 @@ static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9499 9453
9500static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) 9454static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9501{ 9455{
9502 struct drm_device *dev = dev_priv->dev; 9456 struct drm_device *dev = &dev_priv->drm;
9503 9457
9504 if (IS_HASWELL(dev)) { 9458 if (IS_HASWELL(dev)) {
9505 mutex_lock(&dev_priv->rps.hw_lock); 9459 mutex_lock(&dev_priv->rps.hw_lock);
@@ -9534,8 +9488,8 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9534 val |= LCPLL_CD_SOURCE_FCLK; 9488 val |= LCPLL_CD_SOURCE_FCLK;
9535 I915_WRITE(LCPLL_CTL, val); 9489 I915_WRITE(LCPLL_CTL, val);
9536 9490
9537 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & 9491 if (wait_for_us(I915_READ(LCPLL_CTL) &
9538 LCPLL_CD_SOURCE_FCLK_DONE, 1)) 9492 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9539 DRM_ERROR("Switching to FCLK failed\n"); 9493 DRM_ERROR("Switching to FCLK failed\n");
9540 9494
9541 val = I915_READ(LCPLL_CTL); 9495 val = I915_READ(LCPLL_CTL);
@@ -9545,7 +9499,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9545 I915_WRITE(LCPLL_CTL, val); 9499 I915_WRITE(LCPLL_CTL, val);
9546 POSTING_READ(LCPLL_CTL); 9500 POSTING_READ(LCPLL_CTL);
9547 9501
9548 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) 9502 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9549 DRM_ERROR("LCPLL still locked\n"); 9503 DRM_ERROR("LCPLL still locked\n");
9550 9504
9551 val = hsw_read_dcomp(dev_priv); 9505 val = hsw_read_dcomp(dev_priv);
@@ -9600,7 +9554,9 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9600 val &= ~LCPLL_PLL_DISABLE; 9554 val &= ~LCPLL_PLL_DISABLE;
9601 I915_WRITE(LCPLL_CTL, val); 9555 I915_WRITE(LCPLL_CTL, val);
9602 9556
9603 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) 9557 if (intel_wait_for_register(dev_priv,
9558 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
9559 5))
9604 DRM_ERROR("LCPLL not locked yet\n"); 9560 DRM_ERROR("LCPLL not locked yet\n");
9605 9561
9606 if (val & LCPLL_CD_SOURCE_FCLK) { 9562 if (val & LCPLL_CD_SOURCE_FCLK) {
@@ -9608,13 +9564,13 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9608 val &= ~LCPLL_CD_SOURCE_FCLK; 9564 val &= ~LCPLL_CD_SOURCE_FCLK;
9609 I915_WRITE(LCPLL_CTL, val); 9565 I915_WRITE(LCPLL_CTL, val);
9610 9566
9611 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & 9567 if (wait_for_us((I915_READ(LCPLL_CTL) &
9612 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 9568 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9613 DRM_ERROR("Switching back to LCPLL failed\n"); 9569 DRM_ERROR("Switching back to LCPLL failed\n");
9614 } 9570 }
9615 9571
9616 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 9572 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9617 intel_update_cdclk(dev_priv->dev); 9573 intel_update_cdclk(&dev_priv->drm);
9618} 9574}
9619 9575
9620/* 9576/*
@@ -9642,7 +9598,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9642 */ 9598 */
9643void hsw_enable_pc8(struct drm_i915_private *dev_priv) 9599void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9644{ 9600{
9645 struct drm_device *dev = dev_priv->dev; 9601 struct drm_device *dev = &dev_priv->drm;
9646 uint32_t val; 9602 uint32_t val;
9647 9603
9648 DRM_DEBUG_KMS("Enabling package C8+\n"); 9604 DRM_DEBUG_KMS("Enabling package C8+\n");
@@ -9659,7 +9615,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9659 9615
9660void hsw_disable_pc8(struct drm_i915_private *dev_priv) 9616void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9661{ 9617{
9662 struct drm_device *dev = dev_priv->dev; 9618 struct drm_device *dev = &dev_priv->drm;
9663 uint32_t val; 9619 uint32_t val;
9664 9620
9665 DRM_DEBUG_KMS("Disabling package C8+\n"); 9621 DRM_DEBUG_KMS("Disabling package C8+\n");
@@ -9688,7 +9644,7 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9688static int ilk_max_pixel_rate(struct drm_atomic_state *state) 9644static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9689{ 9645{
9690 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 9646 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9691 struct drm_i915_private *dev_priv = state->dev->dev_private; 9647 struct drm_i915_private *dev_priv = to_i915(state->dev);
9692 struct drm_crtc *crtc; 9648 struct drm_crtc *crtc;
9693 struct drm_crtc_state *cstate; 9649 struct drm_crtc_state *cstate;
9694 struct intel_crtc_state *crtc_state; 9650 struct intel_crtc_state *crtc_state;
@@ -9724,7 +9680,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9724 9680
9725static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) 9681static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9726{ 9682{
9727 struct drm_i915_private *dev_priv = dev->dev_private; 9683 struct drm_i915_private *dev_priv = to_i915(dev);
9728 uint32_t val, data; 9684 uint32_t val, data;
9729 int ret; 9685 int ret;
9730 9686
@@ -9893,10 +9849,7 @@ static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9893static int haswell_crtc_compute_clock(struct intel_crtc *crtc, 9849static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9894 struct intel_crtc_state *crtc_state) 9850 struct intel_crtc_state *crtc_state)
9895{ 9851{
9896 struct intel_encoder *intel_encoder = 9852 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9897 intel_ddi_get_crtc_new_encoder(crtc_state);
9898
9899 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9900 if (!intel_ddi_pll_select(crtc, crtc_state)) 9853 if (!intel_ddi_pll_select(crtc, crtc_state))
9901 return -EINVAL; 9854 return -EINVAL;
9902 } 9855 }
@@ -10006,7 +9959,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10006 unsigned long *power_domain_mask) 9959 unsigned long *power_domain_mask)
10007{ 9960{
10008 struct drm_device *dev = crtc->base.dev; 9961 struct drm_device *dev = crtc->base.dev;
10009 struct drm_i915_private *dev_priv = dev->dev_private; 9962 struct drm_i915_private *dev_priv = to_i915(dev);
10010 enum intel_display_power_domain power_domain; 9963 enum intel_display_power_domain power_domain;
10011 u32 tmp; 9964 u32 tmp;
10012 9965
@@ -10057,14 +10010,12 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10057 unsigned long *power_domain_mask) 10010 unsigned long *power_domain_mask)
10058{ 10011{
10059 struct drm_device *dev = crtc->base.dev; 10012 struct drm_device *dev = crtc->base.dev;
10060 struct drm_i915_private *dev_priv = dev->dev_private; 10013 struct drm_i915_private *dev_priv = to_i915(dev);
10061 enum intel_display_power_domain power_domain; 10014 enum intel_display_power_domain power_domain;
10062 enum port port; 10015 enum port port;
10063 enum transcoder cpu_transcoder; 10016 enum transcoder cpu_transcoder;
10064 u32 tmp; 10017 u32 tmp;
10065 10018
10066 pipe_config->has_dsi_encoder = false;
10067
10068 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 10019 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10069 if (port == PORT_A) 10020 if (port == PORT_A)
10070 cpu_transcoder = TRANSCODER_DSI_A; 10021 cpu_transcoder = TRANSCODER_DSI_A;
@@ -10096,18 +10047,17 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10096 continue; 10047 continue;
10097 10048
10098 pipe_config->cpu_transcoder = cpu_transcoder; 10049 pipe_config->cpu_transcoder = cpu_transcoder;
10099 pipe_config->has_dsi_encoder = true;
10100 break; 10050 break;
10101 } 10051 }
10102 10052
10103 return pipe_config->has_dsi_encoder; 10053 return transcoder_is_dsi(pipe_config->cpu_transcoder);
10104} 10054}
10105 10055
10106static void haswell_get_ddi_port_state(struct intel_crtc *crtc, 10056static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10107 struct intel_crtc_state *pipe_config) 10057 struct intel_crtc_state *pipe_config)
10108{ 10058{
10109 struct drm_device *dev = crtc->base.dev; 10059 struct drm_device *dev = crtc->base.dev;
10110 struct drm_i915_private *dev_priv = dev->dev_private; 10060 struct drm_i915_private *dev_priv = to_i915(dev);
10111 struct intel_shared_dpll *pll; 10061 struct intel_shared_dpll *pll;
10112 enum port port; 10062 enum port port;
10113 uint32_t tmp; 10063 uint32_t tmp;
@@ -10150,7 +10100,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10150 struct intel_crtc_state *pipe_config) 10100 struct intel_crtc_state *pipe_config)
10151{ 10101{
10152 struct drm_device *dev = crtc->base.dev; 10102 struct drm_device *dev = crtc->base.dev;
10153 struct drm_i915_private *dev_priv = dev->dev_private; 10103 struct drm_i915_private *dev_priv = to_i915(dev);
10154 enum intel_display_power_domain power_domain; 10104 enum intel_display_power_domain power_domain;
10155 unsigned long power_domain_mask; 10105 unsigned long power_domain_mask;
10156 bool active; 10106 bool active;
@@ -10164,18 +10114,16 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10164 10114
10165 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); 10115 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10166 10116
10167 if (IS_BROXTON(dev_priv)) { 10117 if (IS_BROXTON(dev_priv) &&
10168 bxt_get_dsi_transcoder_state(crtc, pipe_config, 10118 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10169 &power_domain_mask); 10119 WARN_ON(active);
10170 WARN_ON(active && pipe_config->has_dsi_encoder); 10120 active = true;
10171 if (pipe_config->has_dsi_encoder)
10172 active = true;
10173 } 10121 }
10174 10122
10175 if (!active) 10123 if (!active)
10176 goto out; 10124 goto out;
10177 10125
10178 if (!pipe_config->has_dsi_encoder) { 10126 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10179 haswell_get_ddi_port_state(crtc, pipe_config); 10127 haswell_get_ddi_port_state(crtc, pipe_config);
10180 intel_get_pipe_timings(crtc, pipe_config); 10128 intel_get_pipe_timings(crtc, pipe_config);
10181 } 10129 }
@@ -10226,7 +10174,7 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10226 const struct intel_plane_state *plane_state) 10174 const struct intel_plane_state *plane_state)
10227{ 10175{
10228 struct drm_device *dev = crtc->dev; 10176 struct drm_device *dev = crtc->dev;
10229 struct drm_i915_private *dev_priv = dev->dev_private; 10177 struct drm_i915_private *dev_priv = to_i915(dev);
10230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10231 uint32_t cntl = 0, size = 0; 10179 uint32_t cntl = 0, size = 0;
10232 10180
@@ -10289,7 +10237,7 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10289 const struct intel_plane_state *plane_state) 10237 const struct intel_plane_state *plane_state)
10290{ 10238{
10291 struct drm_device *dev = crtc->dev; 10239 struct drm_device *dev = crtc->dev;
10292 struct drm_i915_private *dev_priv = dev->dev_private; 10240 struct drm_i915_private *dev_priv = to_i915(dev);
10293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10294 int pipe = intel_crtc->pipe; 10242 int pipe = intel_crtc->pipe;
10295 uint32_t cntl = 0; 10243 uint32_t cntl = 0;
@@ -10337,7 +10285,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10337 const struct intel_plane_state *plane_state) 10285 const struct intel_plane_state *plane_state)
10338{ 10286{
10339 struct drm_device *dev = crtc->dev; 10287 struct drm_device *dev = crtc->dev;
10340 struct drm_i915_private *dev_priv = dev->dev_private; 10288 struct drm_i915_private *dev_priv = to_i915(dev);
10341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10342 int pipe = intel_crtc->pipe; 10290 int pipe = intel_crtc->pipe;
10343 u32 base = intel_crtc->cursor_addr; 10291 u32 base = intel_crtc->cursor_addr;
@@ -10504,7 +10452,7 @@ mode_fits_in_fbdev(struct drm_device *dev,
10504 struct drm_display_mode *mode) 10452 struct drm_display_mode *mode)
10505{ 10453{
10506#ifdef CONFIG_DRM_FBDEV_EMULATION 10454#ifdef CONFIG_DRM_FBDEV_EMULATION
10507 struct drm_i915_private *dev_priv = dev->dev_private; 10455 struct drm_i915_private *dev_priv = to_i915(dev);
10508 struct drm_i915_gem_object *obj; 10456 struct drm_i915_gem_object *obj;
10509 struct drm_framebuffer *fb; 10457 struct drm_framebuffer *fb;
10510 10458
@@ -10774,7 +10722,7 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
10774static int i9xx_pll_refclk(struct drm_device *dev, 10722static int i9xx_pll_refclk(struct drm_device *dev,
10775 const struct intel_crtc_state *pipe_config) 10723 const struct intel_crtc_state *pipe_config)
10776{ 10724{
10777 struct drm_i915_private *dev_priv = dev->dev_private; 10725 struct drm_i915_private *dev_priv = to_i915(dev);
10778 u32 dpll = pipe_config->dpll_hw_state.dpll; 10726 u32 dpll = pipe_config->dpll_hw_state.dpll;
10779 10727
10780 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 10728 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
@@ -10792,7 +10740,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10792 struct intel_crtc_state *pipe_config) 10740 struct intel_crtc_state *pipe_config)
10793{ 10741{
10794 struct drm_device *dev = crtc->base.dev; 10742 struct drm_device *dev = crtc->base.dev;
10795 struct drm_i915_private *dev_priv = dev->dev_private; 10743 struct drm_i915_private *dev_priv = to_i915(dev);
10796 int pipe = pipe_config->cpu_transcoder; 10744 int pipe = pipe_config->cpu_transcoder;
10797 u32 dpll = pipe_config->dpll_hw_state.dpll; 10745 u32 dpll = pipe_config->dpll_hw_state.dpll;
10798 u32 fp; 10746 u32 fp;
@@ -10918,7 +10866,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10918struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 10866struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10919 struct drm_crtc *crtc) 10867 struct drm_crtc *crtc)
10920{ 10868{
10921 struct drm_i915_private *dev_priv = dev->dev_private; 10869 struct drm_i915_private *dev_priv = to_i915(dev);
10922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10923 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 10871 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10924 struct drm_display_mode *mode; 10872 struct drm_display_mode *mode;
@@ -10970,31 +10918,6 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10970 return mode; 10918 return mode;
10971} 10919}
10972 10920
10973void intel_mark_busy(struct drm_i915_private *dev_priv)
10974{
10975 if (dev_priv->mm.busy)
10976 return;
10977
10978 intel_runtime_pm_get(dev_priv);
10979 i915_update_gfx_val(dev_priv);
10980 if (INTEL_GEN(dev_priv) >= 6)
10981 gen6_rps_busy(dev_priv);
10982 dev_priv->mm.busy = true;
10983}
10984
10985void intel_mark_idle(struct drm_i915_private *dev_priv)
10986{
10987 if (!dev_priv->mm.busy)
10988 return;
10989
10990 dev_priv->mm.busy = false;
10991
10992 if (INTEL_GEN(dev_priv) >= 6)
10993 gen6_rps_idle(dev_priv);
10994
10995 intel_runtime_pm_put(dev_priv);
10996}
10997
10998static void intel_crtc_destroy(struct drm_crtc *crtc) 10921static void intel_crtc_destroy(struct drm_crtc *crtc)
10999{ 10922{
11000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -11056,7 +10979,7 @@ static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11056 struct intel_flip_work *work) 10979 struct intel_flip_work *work)
11057{ 10980{
11058 struct drm_device *dev = crtc->base.dev; 10981 struct drm_device *dev = crtc->base.dev;
11059 struct drm_i915_private *dev_priv = dev->dev_private; 10982 struct drm_i915_private *dev_priv = to_i915(dev);
11060 unsigned reset_counter; 10983 unsigned reset_counter;
11061 10984
11062 reset_counter = i915_reset_counter(&dev_priv->gpu_error); 10985 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
@@ -11132,7 +11055,7 @@ static bool pageflip_finished(struct intel_crtc *crtc,
11132 11055
11133void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) 11056void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11134{ 11057{
11135 struct drm_device *dev = dev_priv->dev; 11058 struct drm_device *dev = &dev_priv->drm;
11136 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 11059 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11138 struct intel_flip_work *work; 11061 struct intel_flip_work *work;
@@ -11159,7 +11082,7 @@ void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11159 11082
11160void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) 11083void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11161{ 11084{
11162 struct drm_device *dev = dev_priv->dev; 11085 struct drm_device *dev = &dev_priv->drm;
11163 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 11086 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11165 struct intel_flip_work *work; 11088 struct intel_flip_work *work;
@@ -11267,7 +11190,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
11267 uint32_t flags) 11190 uint32_t flags)
11268{ 11191{
11269 struct intel_engine_cs *engine = req->engine; 11192 struct intel_engine_cs *engine = req->engine;
11270 struct drm_i915_private *dev_priv = dev->dev_private; 11193 struct drm_i915_private *dev_priv = to_i915(dev);
11271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11272 uint32_t pf, pipesrc; 11195 uint32_t pf, pipesrc;
11273 int ret; 11196 int ret;
@@ -11305,7 +11228,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
11305 uint32_t flags) 11228 uint32_t flags)
11306{ 11229{
11307 struct intel_engine_cs *engine = req->engine; 11230 struct intel_engine_cs *engine = req->engine;
11308 struct drm_i915_private *dev_priv = dev->dev_private; 11231 struct drm_i915_private *dev_priv = to_i915(dev);
11309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11310 uint32_t pf, pipesrc; 11233 uint32_t pf, pipesrc;
11311 int ret; 11234 int ret;
@@ -11464,7 +11387,7 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11464 struct intel_flip_work *work) 11387 struct intel_flip_work *work)
11465{ 11388{
11466 struct drm_device *dev = intel_crtc->base.dev; 11389 struct drm_device *dev = intel_crtc->base.dev;
11467 struct drm_i915_private *dev_priv = dev->dev_private; 11390 struct drm_i915_private *dev_priv = to_i915(dev);
11468 struct drm_framebuffer *fb = intel_crtc->base.primary->fb; 11391 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11469 const enum pipe pipe = intel_crtc->pipe; 11392 const enum pipe pipe = intel_crtc->pipe;
11470 u32 ctl, stride, tile_height; 11393 u32 ctl, stride, tile_height;
@@ -11516,7 +11439,7 @@ static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11516 struct intel_flip_work *work) 11439 struct intel_flip_work *work)
11517{ 11440{
11518 struct drm_device *dev = intel_crtc->base.dev; 11441 struct drm_device *dev = intel_crtc->base.dev;
11519 struct drm_i915_private *dev_priv = dev->dev_private; 11442 struct drm_i915_private *dev_priv = to_i915(dev);
11520 struct intel_framebuffer *intel_fb = 11443 struct intel_framebuffer *intel_fb =
11521 to_intel_framebuffer(intel_crtc->base.primary->fb); 11444 to_intel_framebuffer(intel_crtc->base.primary->fb);
11522 struct drm_i915_gem_object *obj = intel_fb->obj; 11445 struct drm_i915_gem_object *obj = intel_fb->obj;
@@ -11593,7 +11516,7 @@ static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11593 vblank = intel_crtc_get_vblank_counter(intel_crtc); 11516 vblank = intel_crtc_get_vblank_counter(intel_crtc);
11594 if (work->flip_ready_vblank == 0) { 11517 if (work->flip_ready_vblank == 0) {
11595 if (work->flip_queued_req && 11518 if (work->flip_queued_req &&
11596 !i915_gem_request_completed(work->flip_queued_req, true)) 11519 !i915_gem_request_completed(work->flip_queued_req))
11597 return false; 11520 return false;
11598 11521
11599 work->flip_ready_vblank = vblank; 11522 work->flip_ready_vblank = vblank;
@@ -11618,7 +11541,7 @@ static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11618 11541
11619void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) 11542void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11620{ 11543{
11621 struct drm_device *dev = dev_priv->dev; 11544 struct drm_device *dev = &dev_priv->drm;
11622 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 11545 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11624 struct intel_flip_work *work; 11547 struct intel_flip_work *work;
@@ -11646,14 +11569,13 @@ void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11646 spin_unlock(&dev->event_lock); 11569 spin_unlock(&dev->event_lock);
11647} 11570}
11648 11571
11649__maybe_unused
11650static int intel_crtc_page_flip(struct drm_crtc *crtc, 11572static int intel_crtc_page_flip(struct drm_crtc *crtc,
11651 struct drm_framebuffer *fb, 11573 struct drm_framebuffer *fb,
11652 struct drm_pending_vblank_event *event, 11574 struct drm_pending_vblank_event *event,
11653 uint32_t page_flip_flags) 11575 uint32_t page_flip_flags)
11654{ 11576{
11655 struct drm_device *dev = crtc->dev; 11577 struct drm_device *dev = crtc->dev;
11656 struct drm_i915_private *dev_priv = dev->dev_private; 11578 struct drm_i915_private *dev_priv = to_i915(dev);
11657 struct drm_framebuffer *old_fb = crtc->primary->fb; 11579 struct drm_framebuffer *old_fb = crtc->primary->fb;
11658 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 11580 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -11949,8 +11871,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11949 struct drm_framebuffer *fb = plane_state->fb; 11871 struct drm_framebuffer *fb = plane_state->fb;
11950 int ret; 11872 int ret;
11951 11873
11952 if (crtc_state && INTEL_INFO(dev)->gen >= 9 && 11874 if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
11953 plane->type != DRM_PLANE_TYPE_CURSOR) {
11954 ret = skl_update_scaler_plane( 11875 ret = skl_update_scaler_plane(
11955 to_intel_crtc_state(crtc_state), 11876 to_intel_crtc_state(crtc_state),
11956 to_intel_plane_state(plane_state)); 11877 to_intel_plane_state(plane_state));
@@ -12067,31 +11988,11 @@ static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12067 return true; 11988 return true;
12068} 11989}
12069 11990
12070static bool check_encoder_cloning(struct drm_atomic_state *state,
12071 struct intel_crtc *crtc)
12072{
12073 struct intel_encoder *encoder;
12074 struct drm_connector *connector;
12075 struct drm_connector_state *connector_state;
12076 int i;
12077
12078 for_each_connector_in_state(state, connector, connector_state, i) {
12079 if (connector_state->crtc != &crtc->base)
12080 continue;
12081
12082 encoder = to_intel_encoder(connector_state->best_encoder);
12083 if (!check_single_encoder_cloning(state, crtc, encoder))
12084 return false;
12085 }
12086
12087 return true;
12088}
12089
12090static int intel_crtc_atomic_check(struct drm_crtc *crtc, 11991static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12091 struct drm_crtc_state *crtc_state) 11992 struct drm_crtc_state *crtc_state)
12092{ 11993{
12093 struct drm_device *dev = crtc->dev; 11994 struct drm_device *dev = crtc->dev;
12094 struct drm_i915_private *dev_priv = dev->dev_private; 11995 struct drm_i915_private *dev_priv = to_i915(dev);
12095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12096 struct intel_crtc_state *pipe_config = 11997 struct intel_crtc_state *pipe_config =
12097 to_intel_crtc_state(crtc_state); 11998 to_intel_crtc_state(crtc_state);
@@ -12099,11 +12000,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12099 int ret; 12000 int ret;
12100 bool mode_changed = needs_modeset(crtc_state); 12001 bool mode_changed = needs_modeset(crtc_state);
12101 12002
12102 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12103 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12104 return -EINVAL;
12105 }
12106
12107 if (mode_changed && !crtc_state->active) 12003 if (mode_changed && !crtc_state->active)
12108 pipe_config->update_wm_post = true; 12004 pipe_config->update_wm_post = true;
12109 12005
@@ -12299,14 +12195,14 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
12299 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, 12195 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12300 pipe_config->fdi_m_n.tu); 12196 pipe_config->fdi_m_n.tu);
12301 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", 12197 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12302 pipe_config->has_dp_encoder, 12198 intel_crtc_has_dp_encoder(pipe_config),
12303 pipe_config->lane_count, 12199 pipe_config->lane_count,
12304 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, 12200 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12305 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, 12201 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12306 pipe_config->dp_m_n.tu); 12202 pipe_config->dp_m_n.tu);
12307 12203
12308 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", 12204 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12309 pipe_config->has_dp_encoder, 12205 intel_crtc_has_dp_encoder(pipe_config),
12310 pipe_config->lane_count, 12206 pipe_config->lane_count,
12311 pipe_config->dp_m2_n2.gmch_m, 12207 pipe_config->dp_m2_n2.gmch_m,
12312 pipe_config->dp_m2_n2.gmch_n, 12208 pipe_config->dp_m2_n2.gmch_n,
@@ -12439,7 +12335,7 @@ static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12439 case INTEL_OUTPUT_UNKNOWN: 12335 case INTEL_OUTPUT_UNKNOWN:
12440 if (WARN_ON(!HAS_DDI(dev))) 12336 if (WARN_ON(!HAS_DDI(dev)))
12441 break; 12337 break;
12442 case INTEL_OUTPUT_DISPLAYPORT: 12338 case INTEL_OUTPUT_DP:
12443 case INTEL_OUTPUT_HDMI: 12339 case INTEL_OUTPUT_HDMI:
12444 case INTEL_OUTPUT_EDP: 12340 case INTEL_OUTPUT_EDP:
12445 port_mask = 1 << enc_to_dig_port(&encoder->base)->port; 12341 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
@@ -12536,6 +12432,24 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
12536 &pipe_config->pipe_src_w, 12432 &pipe_config->pipe_src_w,
12537 &pipe_config->pipe_src_h); 12433 &pipe_config->pipe_src_h);
12538 12434
12435 for_each_connector_in_state(state, connector, connector_state, i) {
12436 if (connector_state->crtc != crtc)
12437 continue;
12438
12439 encoder = to_intel_encoder(connector_state->best_encoder);
12440
12441 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12442 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12443 goto fail;
12444 }
12445
12446 /*
12447 * Determine output_types before calling the .compute_config()
12448 * hooks so that the hooks can use this information safely.
12449 */
12450 pipe_config->output_types |= 1 << encoder->type;
12451 }
12452
12539encoder_retry: 12453encoder_retry:
12540 /* Ensure the port clock defaults are reset when retrying. */ 12454 /* Ensure the port clock defaults are reset when retrying. */
12541 pipe_config->port_clock = 0; 12455 pipe_config->port_clock = 0;
@@ -12821,7 +12735,6 @@ intel_pipe_config_compare(struct drm_device *dev,
12821 PIPE_CONF_CHECK_I(fdi_lanes); 12735 PIPE_CONF_CHECK_I(fdi_lanes);
12822 PIPE_CONF_CHECK_M_N(fdi_m_n); 12736 PIPE_CONF_CHECK_M_N(fdi_m_n);
12823 12737
12824 PIPE_CONF_CHECK_I(has_dp_encoder);
12825 PIPE_CONF_CHECK_I(lane_count); 12738 PIPE_CONF_CHECK_I(lane_count);
12826 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 12739 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
12827 12740
@@ -12833,7 +12746,7 @@ intel_pipe_config_compare(struct drm_device *dev,
12833 } else 12746 } else
12834 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); 12747 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12835 12748
12836 PIPE_CONF_CHECK_I(has_dsi_encoder); 12749 PIPE_CONF_CHECK_X(output_types);
12837 12750
12838 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); 12751 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12839 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); 12752 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
@@ -12952,7 +12865,7 @@ static void verify_wm_state(struct drm_crtc *crtc,
12952 struct drm_crtc_state *new_state) 12865 struct drm_crtc_state *new_state)
12953{ 12866{
12954 struct drm_device *dev = crtc->dev; 12867 struct drm_device *dev = crtc->dev;
12955 struct drm_i915_private *dev_priv = dev->dev_private; 12868 struct drm_i915_private *dev_priv = to_i915(dev);
12956 struct skl_ddb_allocation hw_ddb, *sw_ddb; 12869 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12957 struct skl_ddb_entry *hw_entry, *sw_entry; 12870 struct skl_ddb_entry *hw_entry, *sw_entry;
12958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 12871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -13058,7 +12971,7 @@ verify_crtc_state(struct drm_crtc *crtc,
13058 struct drm_crtc_state *new_crtc_state) 12971 struct drm_crtc_state *new_crtc_state)
13059{ 12972{
13060 struct drm_device *dev = crtc->dev; 12973 struct drm_device *dev = crtc->dev;
13061 struct drm_i915_private *dev_priv = dev->dev_private; 12974 struct drm_i915_private *dev_priv = to_i915(dev);
13062 struct intel_encoder *encoder; 12975 struct intel_encoder *encoder;
13063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 12976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13064 struct intel_crtc_state *pipe_config, *sw_config; 12977 struct intel_crtc_state *pipe_config, *sw_config;
@@ -13101,8 +13014,10 @@ verify_crtc_state(struct drm_crtc *crtc,
13101 "Encoder connected to wrong pipe %c\n", 13014 "Encoder connected to wrong pipe %c\n",
13102 pipe_name(pipe)); 13015 pipe_name(pipe));
13103 13016
13104 if (active) 13017 if (active) {
13018 pipe_config->output_types |= 1 << encoder->type;
13105 encoder->get_config(encoder, pipe_config); 13019 encoder->get_config(encoder, pipe_config);
13020 }
13106 } 13021 }
13107 13022
13108 if (!new_crtc_state->active) 13023 if (!new_crtc_state->active)
@@ -13181,7 +13096,7 @@ verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13181 struct drm_crtc_state *old_crtc_state, 13096 struct drm_crtc_state *old_crtc_state,
13182 struct drm_crtc_state *new_crtc_state) 13097 struct drm_crtc_state *new_crtc_state)
13183{ 13098{
13184 struct drm_i915_private *dev_priv = dev->dev_private; 13099 struct drm_i915_private *dev_priv = to_i915(dev);
13185 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); 13100 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13186 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); 13101 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13187 13102
@@ -13220,7 +13135,7 @@ intel_modeset_verify_crtc(struct drm_crtc *crtc,
13220static void 13135static void
13221verify_disabled_dpll_state(struct drm_device *dev) 13136verify_disabled_dpll_state(struct drm_device *dev)
13222{ 13137{
13223 struct drm_i915_private *dev_priv = dev->dev_private; 13138 struct drm_i915_private *dev_priv = to_i915(dev);
13224 int i; 13139 int i;
13225 13140
13226 for (i = 0; i < dev_priv->num_shared_dpll; i++) 13141 for (i = 0; i < dev_priv->num_shared_dpll; i++)
@@ -13267,7 +13182,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
13267 13182
13268 crtc->scanline_offset = vtotal - 1; 13183 crtc->scanline_offset = vtotal - 1;
13269 } else if (HAS_DDI(dev) && 13184 } else if (HAS_DDI(dev) &&
13270 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { 13185 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13271 crtc->scanline_offset = 2; 13186 crtc->scanline_offset = 2;
13272 } else 13187 } else
13273 crtc->scanline_offset = 1; 13188 crtc->scanline_offset = 1;
@@ -13402,7 +13317,7 @@ static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13402static int intel_modeset_checks(struct drm_atomic_state *state) 13317static int intel_modeset_checks(struct drm_atomic_state *state)
13403{ 13318{
13404 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 13319 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13405 struct drm_i915_private *dev_priv = state->dev->dev_private; 13320 struct drm_i915_private *dev_priv = to_i915(state->dev);
13406 struct drm_crtc *crtc; 13321 struct drm_crtc *crtc;
13407 struct drm_crtc_state *crtc_state; 13322 struct drm_crtc_state *crtc_state;
13408 int ret = 0, i; 13323 int ret = 0, i;
@@ -13568,7 +13483,7 @@ static int intel_atomic_prepare_commit(struct drm_device *dev,
13568 struct drm_atomic_state *state, 13483 struct drm_atomic_state *state,
13569 bool nonblock) 13484 bool nonblock)
13570{ 13485{
13571 struct drm_i915_private *dev_priv = dev->dev_private; 13486 struct drm_i915_private *dev_priv = to_i915(dev);
13572 struct drm_plane_state *plane_state; 13487 struct drm_plane_state *plane_state;
13573 struct drm_crtc_state *crtc_state; 13488 struct drm_crtc_state *crtc_state;
13574 struct drm_plane *plane; 13489 struct drm_plane *plane;
@@ -13697,7 +13612,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
13697{ 13612{
13698 struct drm_device *dev = state->dev; 13613 struct drm_device *dev = state->dev;
13699 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 13614 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13700 struct drm_i915_private *dev_priv = dev->dev_private; 13615 struct drm_i915_private *dev_priv = to_i915(dev);
13701 struct drm_crtc_state *old_crtc_state; 13616 struct drm_crtc_state *old_crtc_state;
13702 struct drm_crtc *crtc; 13617 struct drm_crtc *crtc;
13703 struct intel_crtc_state *intel_cstate; 13618 struct intel_crtc_state *intel_cstate;
@@ -13929,7 +13844,7 @@ static int intel_atomic_commit(struct drm_device *dev,
13929 bool nonblock) 13844 bool nonblock)
13930{ 13845{
13931 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 13846 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13932 struct drm_i915_private *dev_priv = dev->dev_private; 13847 struct drm_i915_private *dev_priv = to_i915(dev);
13933 int ret = 0; 13848 int ret = 0;
13934 13849
13935 if (intel_state->modeset && nonblock) { 13850 if (intel_state->modeset && nonblock) {
@@ -14008,7 +13923,7 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
14008 .set_config = drm_atomic_helper_set_config, 13923 .set_config = drm_atomic_helper_set_config,
14009 .set_property = drm_atomic_helper_crtc_set_property, 13924 .set_property = drm_atomic_helper_crtc_set_property,
14010 .destroy = intel_crtc_destroy, 13925 .destroy = intel_crtc_destroy,
14011 .page_flip = drm_atomic_helper_page_flip, 13926 .page_flip = intel_crtc_page_flip,
14012 .atomic_duplicate_state = intel_crtc_duplicate_state, 13927 .atomic_duplicate_state = intel_crtc_duplicate_state,
14013 .atomic_destroy_state = intel_crtc_destroy_state, 13928 .atomic_destroy_state = intel_crtc_destroy_state,
14014}; 13929};
@@ -14136,15 +14051,11 @@ int
14136skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) 14051skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14137{ 14052{
14138 int max_scale; 14053 int max_scale;
14139 struct drm_device *dev;
14140 struct drm_i915_private *dev_priv;
14141 int crtc_clock, cdclk; 14054 int crtc_clock, cdclk;
14142 14055
14143 if (!intel_crtc || !crtc_state->base.enable) 14056 if (!intel_crtc || !crtc_state->base.enable)
14144 return DRM_PLANE_HELPER_NO_SCALING; 14057 return DRM_PLANE_HELPER_NO_SCALING;
14145 14058
14146 dev = intel_crtc->base.dev;
14147 dev_priv = dev->dev_private;
14148 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; 14059 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14149 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; 14060 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14150 14061
@@ -14534,7 +14445,7 @@ static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_cr
14534 14445
14535static void intel_crtc_init(struct drm_device *dev, int pipe) 14446static void intel_crtc_init(struct drm_device *dev, int pipe)
14536{ 14447{
14537 struct drm_i915_private *dev_priv = dev->dev_private; 14448 struct drm_i915_private *dev_priv = to_i915(dev);
14538 struct intel_crtc *intel_crtc; 14449 struct intel_crtc *intel_crtc;
14539 struct intel_crtc_state *crtc_state = NULL; 14450 struct intel_crtc_state *crtc_state = NULL;
14540 struct drm_plane *primary = NULL; 14451 struct drm_plane *primary = NULL;
@@ -14633,11 +14544,8 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14633 struct intel_crtc *crtc; 14544 struct intel_crtc *crtc;
14634 14545
14635 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); 14546 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14636 14547 if (!drmmode_crtc)
14637 if (!drmmode_crtc) {
14638 DRM_ERROR("no such CRTC id\n");
14639 return -ENOENT; 14548 return -ENOENT;
14640 }
14641 14549
14642 crtc = to_intel_crtc(drmmode_crtc); 14550 crtc = to_intel_crtc(drmmode_crtc);
14643 pipe_from_crtc_id->pipe = crtc->pipe; 14551 pipe_from_crtc_id->pipe = crtc->pipe;
@@ -14664,7 +14572,7 @@ static int intel_encoder_clones(struct intel_encoder *encoder)
14664 14572
14665static bool has_edp_a(struct drm_device *dev) 14573static bool has_edp_a(struct drm_device *dev)
14666{ 14574{
14667 struct drm_i915_private *dev_priv = dev->dev_private; 14575 struct drm_i915_private *dev_priv = to_i915(dev);
14668 14576
14669 if (!IS_MOBILE(dev)) 14577 if (!IS_MOBILE(dev))
14670 return false; 14578 return false;
@@ -14680,7 +14588,7 @@ static bool has_edp_a(struct drm_device *dev)
14680 14588
14681static bool intel_crt_present(struct drm_device *dev) 14589static bool intel_crt_present(struct drm_device *dev)
14682{ 14590{
14683 struct drm_i915_private *dev_priv = dev->dev_private; 14591 struct drm_i915_private *dev_priv = to_i915(dev);
14684 14592
14685 if (INTEL_INFO(dev)->gen >= 9) 14593 if (INTEL_INFO(dev)->gen >= 9)
14686 return false; 14594 return false;
@@ -14706,10 +14614,15 @@ static bool intel_crt_present(struct drm_device *dev)
14706 14614
14707static void intel_setup_outputs(struct drm_device *dev) 14615static void intel_setup_outputs(struct drm_device *dev)
14708{ 14616{
14709 struct drm_i915_private *dev_priv = dev->dev_private; 14617 struct drm_i915_private *dev_priv = to_i915(dev);
14710 struct intel_encoder *encoder; 14618 struct intel_encoder *encoder;
14711 bool dpd_is_edp = false; 14619 bool dpd_is_edp = false;
14712 14620
14621 /*
14622 * intel_edp_init_connector() depends on this completing first, to
14623 * prevent the registeration of both eDP and LVDS and the incorrect
14624 * sharing of the PPS.
14625 */
14713 intel_lvds_init(dev); 14626 intel_lvds_init(dev);
14714 14627
14715 if (intel_crt_present(dev)) 14628 if (intel_crt_present(dev))
@@ -15354,7 +15267,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15354 */ 15267 */
15355static void quirk_pipea_force(struct drm_device *dev) 15268static void quirk_pipea_force(struct drm_device *dev)
15356{ 15269{
15357 struct drm_i915_private *dev_priv = dev->dev_private; 15270 struct drm_i915_private *dev_priv = to_i915(dev);
15358 15271
15359 dev_priv->quirks |= QUIRK_PIPEA_FORCE; 15272 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15360 DRM_INFO("applying pipe a force quirk\n"); 15273 DRM_INFO("applying pipe a force quirk\n");
@@ -15362,7 +15275,7 @@ static void quirk_pipea_force(struct drm_device *dev)
15362 15275
15363static void quirk_pipeb_force(struct drm_device *dev) 15276static void quirk_pipeb_force(struct drm_device *dev)
15364{ 15277{
15365 struct drm_i915_private *dev_priv = dev->dev_private; 15278 struct drm_i915_private *dev_priv = to_i915(dev);
15366 15279
15367 dev_priv->quirks |= QUIRK_PIPEB_FORCE; 15280 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15368 DRM_INFO("applying pipe b force quirk\n"); 15281 DRM_INFO("applying pipe b force quirk\n");
@@ -15373,7 +15286,7 @@ static void quirk_pipeb_force(struct drm_device *dev)
15373 */ 15286 */
15374static void quirk_ssc_force_disable(struct drm_device *dev) 15287static void quirk_ssc_force_disable(struct drm_device *dev)
15375{ 15288{
15376 struct drm_i915_private *dev_priv = dev->dev_private; 15289 struct drm_i915_private *dev_priv = to_i915(dev);
15377 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; 15290 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15378 DRM_INFO("applying lvds SSC disable quirk\n"); 15291 DRM_INFO("applying lvds SSC disable quirk\n");
15379} 15292}
@@ -15384,7 +15297,7 @@ static void quirk_ssc_force_disable(struct drm_device *dev)
15384 */ 15297 */
15385static void quirk_invert_brightness(struct drm_device *dev) 15298static void quirk_invert_brightness(struct drm_device *dev)
15386{ 15299{
15387 struct drm_i915_private *dev_priv = dev->dev_private; 15300 struct drm_i915_private *dev_priv = to_i915(dev);
15388 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; 15301 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15389 DRM_INFO("applying inverted panel brightness quirk\n"); 15302 DRM_INFO("applying inverted panel brightness quirk\n");
15390} 15303}
@@ -15392,7 +15305,7 @@ static void quirk_invert_brightness(struct drm_device *dev)
15392/* Some VBT's incorrectly indicate no backlight is present */ 15305/* Some VBT's incorrectly indicate no backlight is present */
15393static void quirk_backlight_present(struct drm_device *dev) 15306static void quirk_backlight_present(struct drm_device *dev)
15394{ 15307{
15395 struct drm_i915_private *dev_priv = dev->dev_private; 15308 struct drm_i915_private *dev_priv = to_i915(dev);
15396 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; 15309 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15397 DRM_INFO("applying backlight present quirk\n"); 15310 DRM_INFO("applying backlight present quirk\n");
15398} 15311}
@@ -15518,7 +15431,7 @@ static void intel_init_quirks(struct drm_device *dev)
15518/* Disable the VGA plane that we never use */ 15431/* Disable the VGA plane that we never use */
15519static void i915_disable_vga(struct drm_device *dev) 15432static void i915_disable_vga(struct drm_device *dev)
15520{ 15433{
15521 struct drm_i915_private *dev_priv = dev->dev_private; 15434 struct drm_i915_private *dev_priv = to_i915(dev);
15522 u8 sr1; 15435 u8 sr1;
15523 i915_reg_t vga_reg = i915_vgacntrl_reg(dev); 15436 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15524 15437
@@ -15536,7 +15449,7 @@ static void i915_disable_vga(struct drm_device *dev)
15536 15449
15537void intel_modeset_init_hw(struct drm_device *dev) 15450void intel_modeset_init_hw(struct drm_device *dev)
15538{ 15451{
15539 struct drm_i915_private *dev_priv = dev->dev_private; 15452 struct drm_i915_private *dev_priv = to_i915(dev);
15540 15453
15541 intel_update_cdclk(dev); 15454 intel_update_cdclk(dev);
15542 15455
@@ -15784,7 +15697,7 @@ static bool
15784intel_check_plane_mapping(struct intel_crtc *crtc) 15697intel_check_plane_mapping(struct intel_crtc *crtc)
15785{ 15698{
15786 struct drm_device *dev = crtc->base.dev; 15699 struct drm_device *dev = crtc->base.dev;
15787 struct drm_i915_private *dev_priv = dev->dev_private; 15700 struct drm_i915_private *dev_priv = to_i915(dev);
15788 u32 val; 15701 u32 val;
15789 15702
15790 if (INTEL_INFO(dev)->num_pipes == 1) 15703 if (INTEL_INFO(dev)->num_pipes == 1)
@@ -15824,7 +15737,7 @@ static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15824static void intel_sanitize_crtc(struct intel_crtc *crtc) 15737static void intel_sanitize_crtc(struct intel_crtc *crtc)
15825{ 15738{
15826 struct drm_device *dev = crtc->base.dev; 15739 struct drm_device *dev = crtc->base.dev;
15827 struct drm_i915_private *dev_priv = dev->dev_private; 15740 struct drm_i915_private *dev_priv = to_i915(dev);
15828 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; 15741 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15829 15742
15830 /* Clear any frame start delays used for debugging left by the BIOS */ 15743 /* Clear any frame start delays used for debugging left by the BIOS */
@@ -15949,7 +15862,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
15949 15862
15950void i915_redisable_vga_power_on(struct drm_device *dev) 15863void i915_redisable_vga_power_on(struct drm_device *dev)
15951{ 15864{
15952 struct drm_i915_private *dev_priv = dev->dev_private; 15865 struct drm_i915_private *dev_priv = to_i915(dev);
15953 i915_reg_t vga_reg = i915_vgacntrl_reg(dev); 15866 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15954 15867
15955 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { 15868 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
@@ -15960,7 +15873,7 @@ void i915_redisable_vga_power_on(struct drm_device *dev)
15960 15873
15961void i915_redisable_vga(struct drm_device *dev) 15874void i915_redisable_vga(struct drm_device *dev)
15962{ 15875{
15963 struct drm_i915_private *dev_priv = dev->dev_private; 15876 struct drm_i915_private *dev_priv = to_i915(dev);
15964 15877
15965 /* This function can be called both from intel_modeset_setup_hw_state or 15878 /* This function can be called both from intel_modeset_setup_hw_state or
15966 * at a very early point in our resume sequence, where the power well 15879 * at a very early point in our resume sequence, where the power well
@@ -16000,7 +15913,7 @@ static void readout_plane_state(struct intel_crtc *crtc)
16000 15913
16001static void intel_modeset_readout_hw_state(struct drm_device *dev) 15914static void intel_modeset_readout_hw_state(struct drm_device *dev)
16002{ 15915{
16003 struct drm_i915_private *dev_priv = dev->dev_private; 15916 struct drm_i915_private *dev_priv = to_i915(dev);
16004 enum pipe pipe; 15917 enum pipe pipe;
16005 struct intel_crtc *crtc; 15918 struct intel_crtc *crtc;
16006 struct intel_encoder *encoder; 15919 struct intel_encoder *encoder;
@@ -16069,6 +15982,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
16069 if (encoder->get_hw_state(encoder, &pipe)) { 15982 if (encoder->get_hw_state(encoder, &pipe)) {
16070 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 15983 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16071 encoder->base.crtc = &crtc->base; 15984 encoder->base.crtc = &crtc->base;
15985 crtc->config->output_types |= 1 << encoder->type;
16072 encoder->get_config(encoder, crtc->config); 15986 encoder->get_config(encoder, crtc->config);
16073 } else { 15987 } else {
16074 encoder->base.crtc = NULL; 15988 encoder->base.crtc = NULL;
@@ -16153,7 +16067,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
16153static void 16067static void
16154intel_modeset_setup_hw_state(struct drm_device *dev) 16068intel_modeset_setup_hw_state(struct drm_device *dev)
16155{ 16069{
16156 struct drm_i915_private *dev_priv = dev->dev_private; 16070 struct drm_i915_private *dev_priv = to_i915(dev);
16157 enum pipe pipe; 16071 enum pipe pipe;
16158 struct intel_crtc *crtc; 16072 struct intel_crtc *crtc;
16159 struct intel_encoder *encoder; 16073 struct intel_encoder *encoder;
@@ -16309,8 +16223,21 @@ void intel_modeset_gem_init(struct drm_device *dev)
16309 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); 16223 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16310 } 16224 }
16311 } 16225 }
16226}
16227
16228int intel_connector_register(struct drm_connector *connector)
16229{
16230 struct intel_connector *intel_connector = to_intel_connector(connector);
16231 int ret;
16232
16233 ret = intel_backlight_device_register(intel_connector);
16234 if (ret)
16235 goto err;
16312 16236
16313 intel_backlight_register(dev); 16237 return 0;
16238
16239err:
16240 return ret;
16314} 16241}
16315 16242
16316void intel_connector_unregister(struct drm_connector *connector) 16243void intel_connector_unregister(struct drm_connector *connector)
@@ -16323,7 +16250,7 @@ void intel_connector_unregister(struct drm_connector *connector)
16323 16250
16324void intel_modeset_cleanup(struct drm_device *dev) 16251void intel_modeset_cleanup(struct drm_device *dev)
16325{ 16252{
16326 struct drm_i915_private *dev_priv = dev->dev_private; 16253 struct drm_i915_private *dev_priv = to_i915(dev);
16327 16254
16328 intel_disable_gt_powersave(dev_priv); 16255 intel_disable_gt_powersave(dev_priv);
16329 16256
@@ -16347,8 +16274,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
16347 /* flush any delayed tasks or pending work */ 16274 /* flush any delayed tasks or pending work */
16348 flush_scheduled_work(); 16275 flush_scheduled_work();
16349 16276
16350 drm_connector_unregister_all(dev);
16351
16352 drm_mode_config_cleanup(dev); 16277 drm_mode_config_cleanup(dev);
16353 16278
16354 intel_cleanup_overlay(dev_priv); 16279 intel_cleanup_overlay(dev_priv);
@@ -16371,7 +16296,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector,
16371 */ 16296 */
16372int intel_modeset_vga_set_state(struct drm_device *dev, bool state) 16297int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16373{ 16298{
16374 struct drm_i915_private *dev_priv = dev->dev_private; 16299 struct drm_i915_private *dev_priv = to_i915(dev);
16375 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; 16300 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16376 u16 gmch_ctrl; 16301 u16 gmch_ctrl;
16377 16302
@@ -16527,7 +16452,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16527 struct drm_device *dev, 16452 struct drm_device *dev,
16528 struct intel_display_error_state *error) 16453 struct intel_display_error_state *error)
16529{ 16454{
16530 struct drm_i915_private *dev_priv = dev->dev_private; 16455 struct drm_i915_private *dev_priv = to_i915(dev);
16531 int i; 16456 int i;
16532 16457
16533 if (!error) 16458 if (!error)
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-02 16:08:21 -0400