diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1b61f9810387..ba9321998a41 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -4854,6 +4854,9 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc) | |||
4854 | struct intel_plane *intel_plane; | 4854 | struct intel_plane *intel_plane; |
4855 | int pipe = intel_crtc->pipe; | 4855 | int pipe = intel_crtc->pipe; |
4856 | 4856 | ||
4857 | if (!intel_crtc->active) | ||
4858 | return; | ||
4859 | |||
4857 | intel_crtc_wait_for_pending_flips(crtc); | 4860 | intel_crtc_wait_for_pending_flips(crtc); |
4858 | 4861 | ||
4859 | intel_pre_disable_primary(crtc); | 4862 | intel_pre_disable_primary(crtc); |
@@ -7887,7 +7890,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc, | |||
7887 | int pipe = pipe_config->cpu_transcoder; | 7890 | int pipe = pipe_config->cpu_transcoder; |
7888 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | 7891 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
7889 | intel_clock_t clock; | 7892 | intel_clock_t clock; |
7890 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | 7893 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
7891 | int refclk = 100000; | 7894 | int refclk = 100000; |
7892 | 7895 | ||
7893 | mutex_lock(&dev_priv->sb_lock); | 7896 | mutex_lock(&dev_priv->sb_lock); |
@@ -7895,10 +7898,13 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc, | |||
7895 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | 7898 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); |
7896 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | 7899 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); |
7897 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | 7900 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); |
7901 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); | ||
7898 | mutex_unlock(&dev_priv->sb_lock); | 7902 | mutex_unlock(&dev_priv->sb_lock); |
7899 | 7903 | ||
7900 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | 7904 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; |
7901 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | 7905 | clock.m2 = (pll_dw0 & 0xff) << 22; |
7906 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | ||
7907 | clock.m2 |= pll_dw2 & 0x3fffff; | ||
7902 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | 7908 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
7903 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | 7909 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; |
7904 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | 7910 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; |
@@ -13270,7 +13276,7 @@ intel_check_primary_plane(struct drm_plane *plane, | |||
13270 | if (ret) | 13276 | if (ret) |
13271 | return ret; | 13277 | return ret; |
13272 | 13278 | ||
13273 | if (intel_crtc->active) { | 13279 | if (crtc_state->base.active) { |
13274 | struct intel_plane_state *old_state = | 13280 | struct intel_plane_state *old_state = |
13275 | to_intel_plane_state(plane->state); | 13281 | to_intel_plane_state(plane->state); |
13276 | 13282 | ||