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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7d3309bc0fd2..062c1d7cdace 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3690,7 +3690,7 @@ static void intel_gpu_idle_timer(unsigned long arg)
3690 struct drm_device *dev = (struct drm_device *)arg; 3690 struct drm_device *dev = (struct drm_device *)arg;
3691 drm_i915_private_t *dev_priv = dev->dev_private; 3691 drm_i915_private_t *dev_priv = dev->dev_private;
3692 3692
3693 DRM_DEBUG("idle timer fired, downclocking\n"); 3693 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3694 3694
3695 dev_priv->busy = false; 3695 dev_priv->busy = false;
3696 3696
@@ -3705,7 +3705,7 @@ void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3705 return; 3705 return;
3706 3706
3707 if (!dev_priv->render_reclock_avail) { 3707 if (!dev_priv->render_reclock_avail) {
3708 DRM_DEBUG("not reclocking render clock\n"); 3708 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3709 return; 3709 return;
3710 } 3710 }
3711 3711
@@ -3714,7 +3714,7 @@ void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3714 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock); 3714 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3715 else if (IS_I85X(dev)) 3715 else if (IS_I85X(dev))
3716 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock); 3716 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3717 DRM_DEBUG("increasing render clock frequency\n"); 3717 DRM_DEBUG_DRIVER("increasing render clock frequency\n");
3718 3718
3719 /* Schedule downclock */ 3719 /* Schedule downclock */
3720 if (schedule) 3720 if (schedule)
@@ -3730,7 +3730,7 @@ void intel_decrease_renderclock(struct drm_device *dev)
3730 return; 3730 return;
3731 3731
3732 if (!dev_priv->render_reclock_avail) { 3732 if (!dev_priv->render_reclock_avail) {
3733 DRM_DEBUG("not reclocking render clock\n"); 3733 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3734 return; 3734 return;
3735 } 3735 }
3736 3736
@@ -3790,7 +3790,7 @@ void intel_decrease_renderclock(struct drm_device *dev)
3790 3790
3791 pci_write_config_word(dev->pdev, HPLLCC, hpllcc); 3791 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3792 } 3792 }
3793 DRM_DEBUG("decreasing render clock frequency\n"); 3793 DRM_DEBUG_DRIVER("decreasing render clock frequency\n");
3794} 3794}
3795 3795
3796/* Note that no increase function is needed for this - increase_renderclock() 3796/* Note that no increase function is needed for this - increase_renderclock()
@@ -3824,7 +3824,7 @@ static void intel_crtc_idle_timer(unsigned long arg)
3824 struct drm_crtc *crtc = &intel_crtc->base; 3824 struct drm_crtc *crtc = &intel_crtc->base;
3825 drm_i915_private_t *dev_priv = crtc->dev->dev_private; 3825 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3826 3826
3827 DRM_DEBUG("idle timer fired, downclocking\n"); 3827 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3828 3828
3829 intel_crtc->busy = false; 3829 intel_crtc->busy = false;
3830 3830
@@ -3847,7 +3847,7 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3847 return; 3847 return;
3848 3848
3849 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { 3849 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3850 DRM_DEBUG("upclocking LVDS\n"); 3850 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3851 3851
3852 /* Unlock panel regs */ 3852 /* Unlock panel regs */
3853 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); 3853 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
@@ -3858,7 +3858,7 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3858 intel_wait_for_vblank(dev); 3858 intel_wait_for_vblank(dev);
3859 dpll = I915_READ(dpll_reg); 3859 dpll = I915_READ(dpll_reg);
3860 if (dpll & DISPLAY_RATE_SELECT_FPA1) 3860 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3861 DRM_DEBUG("failed to upclock LVDS!\n"); 3861 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3862 3862
3863 /* ...and lock them again */ 3863 /* ...and lock them again */
3864 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); 3864 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
@@ -3890,7 +3890,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
3890 * the manual case. 3890 * the manual case.
3891 */ 3891 */
3892 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { 3892 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3893 DRM_DEBUG("downclocking LVDS\n"); 3893 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3894 3894
3895 /* Unlock panel regs */ 3895 /* Unlock panel regs */
3896 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); 3896 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
@@ -3901,7 +3901,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
3901 intel_wait_for_vblank(dev); 3901 intel_wait_for_vblank(dev);
3902 dpll = I915_READ(dpll_reg); 3902 dpll = I915_READ(dpll_reg);
3903 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 3903 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3904 DRM_DEBUG("failed to downclock LVDS!\n"); 3904 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3905 3905
3906 /* ...and lock them again */ 3906 /* ...and lock them again */
3907 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); 3907 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);