1 files changed, 15 insertions, 18 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4f0675460336..3b56b2cae804 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2455,7 +2455,7 @@ u32 intel_compute_tile_offset(int *x, int *y,
         u32 alignment;
 
         /* AUX_DIST needs only 4K alignment */
-        if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
+        if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
                 alignment = 4096;
         else
                 alignment = intel_surf_alignment(dev_priv, fb->modifier);
@@ -2700,7 +2700,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
         if (plane_config->tiling == I915_TILING_X)
                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
 
-        mode_cmd.pixel_format = fb->pixel_format;
+        mode_cmd.pixel_format = fb->format->format;
         mode_cmd.width = fb->width;
         mode_cmd.height = fb->height;
         mode_cmd.pitches[0] = fb->pitches[0];
@@ -2976,7 +2976,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
          * Handle the AUX surface first since
          * the main surface setup depends on it.
          */
-        if (fb->pixel_format == DRM_FORMAT_NV12) {
+        if (fb->format->format == DRM_FORMAT_NV12) {
                 ret = skl_check_nv12_aux_surface(plane_state);
                 if (ret)
                         return ret;
@@ -3031,7 +3031,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
         }
 
-        switch (fb->pixel_format) {
+        switch (fb->format->format) {
         case DRM_FORMAT_C8:
                 dspcntr |= DISPPLANE_8BPP;
                 break;
@@ -3146,7 +3146,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
 
-        switch (fb->pixel_format) {
+        switch (fb->format->format) {
         case DRM_FORMAT_C8:
                 dspcntr |= DISPPLANE_8BPP;
                 break;
@@ -3282,7 +3282,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
                 stride /= intel_tile_height(dev_priv, fb->modifier, cpp);
         } else {
                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier,
-                                                    fb->pixel_format);
+                                                    fb->format->format);
         }
 
         return stride;
@@ -3396,7 +3396,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
                     PLANE_CTL_PIPE_GAMMA_ENABLE |
                     PLANE_CTL_PIPE_CSC_ENABLE;
 
-        plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
+        plane_ctl |= skl_plane_ctl_format(fb->format->format);
         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
         plane_ctl |= skl_plane_ctl_rotation(rotation);
@@ -4768,7 +4768,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
         }
 
         /* Check src format */
-        switch (fb->pixel_format) {
+        switch (fb->format->format) {
         case DRM_FORMAT_RGB565:
         case DRM_FORMAT_XBGR8888:
         case DRM_FORMAT_XRGB8888:
@@ -4784,7 +4784,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
         default:
                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
                               intel_plane->base.base.id, intel_plane->base.name,
-                              fb->base.id, fb->pixel_format);
+                              fb->base.id, fb->format->format);
                 return -EINVAL;
         }
 
@@ -8714,7 +8714,6 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
         fourcc = i9xx_format_to_fourcc(pixel_format);
-        fb->pixel_format = fourcc;
         fb->format = drm_format_info(fourcc);
 
         if (INTEL_GEN(dev_priv) >= 4) {
@@ -8736,7 +8735,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
         fb->pitches[0] = val & 0xffffffc0;
 
         aligned_height = intel_fb_align_height(dev, fb->height,
-                                               fb->pixel_format,
+                                               fb->format->format,
                                                fb->modifier);
 
         plane_config->size = fb->pitches[0] * aligned_height;
@@ -9745,7 +9744,6 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
         fourcc = skl_format_to_fourcc(pixel_format,
                                       val & PLANE_CTL_ORDER_RGBX,
                                       val & PLANE_CTL_ALPHA_MASK);
-        fb->pixel_format = fourcc;
         fb->format = drm_format_info(fourcc);
 
         tiling = val & PLANE_CTL_TILED_MASK;
@@ -9779,11 +9777,11 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
         val = I915_READ(PLANE_STRIDE(pipe, 0));
         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier,
-                                                fb->pixel_format);
+                                                fb->format->format);
         fb->pitches[0] = (val & 0x3ff) * stride_mult;
 
         aligned_height = intel_fb_align_height(dev, fb->height,
-                                               fb->pixel_format,
+                                               fb->format->format,
                                                fb->modifier);
 
         plane_config->size = fb->pitches[0] * aligned_height;
@@ -9860,7 +9858,6 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
 
         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
         fourcc = i9xx_format_to_fourcc(pixel_format);
-        fb->pixel_format = fourcc;
         fb->format = drm_format_info(fourcc);
 
         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
@@ -9882,7 +9879,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
         fb->pitches[0] = val & 0xffffffc0;
 
         aligned_height = intel_fb_align_height(dev, fb->height,
-                                               fb->pixel_format,
+                                               fb->format->format,
                                                fb->modifier);
 
         plane_config->size = fb->pitches[0] * aligned_height;
@@ -12150,7 +12147,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
                 return -EBUSY;
 
         /* Can't change pixel format via MI display flips. */
-        if (fb->pixel_format != crtc->primary->fb->pixel_format)
+        if (fb->format->format != crtc->primary->fb->format->format)
                 return -EINVAL;
 
         /*
@@ -12847,7 +12844,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
                               plane->base.id, plane->name,
                               fb->base.id, fb->width, fb->height,
-                              drm_get_format_name(fb->pixel_format, &format_name));
+                              drm_get_format_name(fb->format->format, &format_name));
                 if (INTEL_GEN(dev_priv) >= 9)
                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
                                       state->scaler_id,