1 files changed, 74 insertions, 73 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 536a66a9e71a..1a56d50b3c03 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -897,7 +897,7 @@ bool intel_crtc_active(struct drm_crtc *crtc)
          * properly reconstruct framebuffers.
          */
         return intel_crtc->active && crtc->primary->fb &&
-                intel_crtc->config.adjusted_mode.crtc_clock;
+                intel_crtc->config.base.adjusted_mode.crtc_clock;
 }
 
 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
@@ -2941,7 +2941,7 @@ static void intel_update_pipe_size(struct intel_crtc *crtc)
          * then update the pipesrc and pfit state, even on the flip path.
          */
 
-        adjusted_mode = &crtc->config.adjusted_mode;
+        adjusted_mode = &crtc->config.base.adjusted_mode;
 
         I915_WRITE(PIPESRC(crtc->pipe),
                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
@@ -3577,7 +3577,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
 {
         struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
-        int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
+        int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock;
         u32 divsel, phaseinc, auxdiv, phasedir = 0;
         u32 temp;
 
@@ -4908,7 +4908,7 @@ static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
         for_each_intel_crtc(dev, intel_crtc) {
                 if (intel_crtc->new_enabled)
                         max_pixclk = max(max_pixclk,
-                                         intel_crtc->new_config->adjusted_mode.crtc_clock);
+                                         intel_crtc->new_config->base.adjusted_mode.crtc_clock);
         }
 
         return max_pixclk;
@@ -5429,7 +5429,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
                                        struct intel_crtc_state *pipe_config)
 {
         struct drm_device *dev = intel_crtc->base.dev;
-        struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+        struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
         int lane, link_bw, fdi_dotclock;
         bool setup_ok, needs_recompute = false;
 
@@ -5484,7 +5484,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 {
         struct drm_device *dev = crtc->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
-        struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+        struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 
         /* FIXME should check pixel clock limits on all platforms */
         if (INTEL_INFO(dev)->gen < 4) {
@@ -6206,7 +6206,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
         enum pipe pipe = intel_crtc->pipe;
         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
         struct drm_display_mode *adjusted_mode =
-                &intel_crtc->config.adjusted_mode;
+                &intel_crtc->config.base.adjusted_mode;
         uint32_t crtc_vtotal, crtc_vblank_end;
         int vsyncshift = 0;
 
@@ -6277,56 +6277,56 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
         uint32_t tmp;
 
         tmp = I915_READ(HTOTAL(cpu_transcoder));
-        pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
-        pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
+        pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
+        pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
         tmp = I915_READ(HBLANK(cpu_transcoder));
-        pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
-        pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
+        pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
+        pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
         tmp = I915_READ(HSYNC(cpu_transcoder));
-        pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
-        pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
+        pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
+        pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
 
         tmp = I915_READ(VTOTAL(cpu_transcoder));
-        pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
-        pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
+        pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
+        pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
         tmp = I915_READ(VBLANK(cpu_transcoder));
-        pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
-        pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
+        pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
+        pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
         tmp = I915_READ(VSYNC(cpu_transcoder));
-        pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
-        pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
+        pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
+        pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
 
         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
-                pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
-                pipe_config->adjusted_mode.crtc_vtotal += 1;
-                pipe_config->adjusted_mode.crtc_vblank_end += 1;
+                pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
+                pipe_config->base.adjusted_mode.crtc_vtotal += 1;
+                pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
         }
 
         tmp = I915_READ(PIPESRC(crtc->pipe));
         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
 
-        pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
-        pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
+        pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
+        pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
 }
 
 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
                                  struct intel_crtc_state *pipe_config)
 {
-        mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
-        mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
-        mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
-        mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
+        mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
+        mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
+        mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
+        mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
 
-        mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
-        mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
-        mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
-        mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
+        mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
+        mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
+        mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
+        mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
 
-        mode->flags = pipe_config->adjusted_mode.flags;
+        mode->flags = pipe_config->base.adjusted_mode.flags;
 
-        mode->clock = pipe_config->adjusted_mode.crtc_clock;
-        mode->flags |= pipe_config->adjusted_mode.flags;
+        mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
+        mode->flags |= pipe_config->base.adjusted_mode.flags;
 }
 
 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
@@ -6376,7 +6376,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
                 }
         }
 
-        if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+        if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
                 if (INTEL_INFO(dev)->gen < 4 ||
                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
@@ -7133,7 +7133,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
         if (intel_crtc->config.dither)
                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
 
-        if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+        if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
                 val |= PIPECONF_INTERLACED_ILK;
         else
                 val |= PIPECONF_PROGRESSIVE;
@@ -7223,7 +7223,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
         if (IS_HASWELL(dev) && intel_crtc->config.dither)
                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
 
-        if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+        if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
                 val |= PIPECONF_INTERLACED_ILK;
         else
                 val |= PIPECONF_PROGRESSIVE;
@@ -8789,7 +8789,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
          * agree once we know their relationship in the encoder's
          * get_config() function.
          */
-        pipe_config->adjusted_mode.crtc_clock =
+        pipe_config->base.adjusted_mode.crtc_clock =
                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
                                          &pipe_config->fdi_m_n);
 }
@@ -9981,10 +9981,10 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
                       pipe_config->has_infoframe);
 
         DRM_DEBUG_KMS("requested mode:\n");
-        drm_mode_debug_printmodeline(&pipe_config->requested_mode);
+        drm_mode_debug_printmodeline(&pipe_config->base.mode);
         DRM_DEBUG_KMS("adjusted mode:\n");
-        drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
-        intel_dump_crtc_timings(&pipe_config->adjusted_mode);
+        drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
+        intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
@@ -10108,8 +10108,8 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
         if (!pipe_config)
                 return ERR_PTR(-ENOMEM);
 
-        drm_mode_copy(&pipe_config->adjusted_mode, mode);
-        drm_mode_copy(&pipe_config->requested_mode, mode);
+        drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
+        drm_mode_copy(&pipe_config->base.mode, mode);
 
         pipe_config->cpu_transcoder =
                 (enum transcoder) to_intel_crtc(crtc)->pipe;
@@ -10120,13 +10120,13 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
          * positive or negative polarity is requested, treat this as meaning
          * negative polarity.
          */
-        if (!(pipe_config->adjusted_mode.flags &
+        if (!(pipe_config->base.adjusted_mode.flags &
               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
-                pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
+                pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
 
-        if (!(pipe_config->adjusted_mode.flags &
+        if (!(pipe_config->base.adjusted_mode.flags &
               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
-                pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
+                pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
 
         /* Compute a starting value for pipe_config->pipe_bpp taking the source
          * plane pixel format and any sink constraints into account. Returns the
@@ -10145,7 +10145,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
          * computation to clearly distinguish it from the adjusted mode, which
          * can be changed by the connectors in the below retry loop.
          */
-        drm_crtc_get_hv_timing(&pipe_config->requested_mode,
+        drm_crtc_get_hv_timing(&pipe_config->base.mode,
                                &pipe_config->pipe_src_w,
                                &pipe_config->pipe_src_h);
 
@@ -10155,7 +10155,8 @@ encoder_retry:
         pipe_config->pixel_multiplier = 1;
 
         /* Fill in default crtc timings, allow encoders to overwrite them. */
-        drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
+        drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
+                              CRTC_STEREO_DOUBLE);
 
         /* Pass our mode to the connectors and the CRTC to give them a chance to
          * adjust it according to limitations or connector properties, and also
@@ -10175,7 +10176,7 @@ encoder_retry:
         /* Set default port clock if not overwritten by the encoder. Needs to be
          * done afterwards in case the encoder adjusts the mode. */
         if (!pipe_config->port_clock)
-                pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
+                pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
                         * pipe_config->pixel_multiplier;
 
         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
@@ -10476,19 +10477,19 @@ intel_pipe_config_compare(struct drm_device *dev,
                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
         }
 
-        PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
-        PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
-        PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
-        PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
-        PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
-        PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
+        PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
+        PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
+        PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
+        PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
+        PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
+        PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
 
-        PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
-        PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
-        PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
-        PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
-        PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
-        PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
+        PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
+        PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
+        PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
+        PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
+        PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
+        PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
 
         PIPE_CONF_CHECK_I(pixel_multiplier);
         PIPE_CONF_CHECK_I(has_hdmi_sink);
@@ -10499,17 +10500,17 @@ intel_pipe_config_compare(struct drm_device *dev,
 
         PIPE_CONF_CHECK_I(has_audio);
 
-        PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
+        PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
                               DRM_MODE_FLAG_INTERLACE);
 
         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
-                PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
+                PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
                                       DRM_MODE_FLAG_PHSYNC);
-                PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
+                PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
                                       DRM_MODE_FLAG_NHSYNC);
-                PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
+                PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
                                       DRM_MODE_FLAG_PVSYNC);
-                PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
+                PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
                                       DRM_MODE_FLAG_NVSYNC);
         }
 
@@ -10559,7 +10560,7 @@ intel_pipe_config_compare(struct drm_device *dev,
         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
                 PIPE_CONF_CHECK_I(pipe_bpp);
 
-        PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
+        PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
 
 #undef PIPE_CONF_CHECK_X
@@ -10835,9 +10836,9 @@ void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
          * FDI already provided one idea for the dotclock.
          * Yell if the encoder disagrees.
          */
-        WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
+        WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
-             pipe_config->adjusted_mode.crtc_clock, dotclock);
+             pipe_config->base.adjusted_mode.crtc_clock, dotclock);
 }
 
 static void update_scanline_offset(struct intel_crtc *crtc)
@@ -10863,7 +10864,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
          * one to the value.
          */
         if (IS_GEN2(dev)) {
-                const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
+                const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
                 int vtotal;
 
                 vtotal = mode->crtc_vtotal;
@@ -10992,7 +10993,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
                  * timestamping. They are derived from true hwmode.
                  */
                 drm_calc_timestamping_constants(crtc,
-                                                &pipe_config->adjusted_mode);
+                                                &pipe_config->base.adjusted_mode);
         }
 
         /* Only after disabling all output pipelines that will be changed can we