1 files changed, 110 insertions, 11 deletions

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 875d428ea75f..02f8bf101ccd 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -235,16 +235,6 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 #define IS_SS_DISABLED(ss)      (!(sseu->subslice_mask & BIT(ss)))
                 info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
 
-                /*
-                 * There is a HW issue in 2x6 fused down parts that requires
-                 * Pooled EU to be enabled as a WA. The pool configuration
-                 * changes depending upon which subslice is fused down. This
-                 * doesn't affect if the device has all 3 subslices enabled.
-                 */
-                /* WaEnablePooledEuFor2x6:bxt */
-                info->has_pooled_eu |= (hweight8(sseu->subslice_mask) == 2 &&
-                                        IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST));
-
                 sseu->min_eu_in_pool = 0;
                 if (info->has_pooled_eu) {
                         if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
@@ -329,6 +319,107 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
         sseu->has_eu_pg = 0;
 }
 
+static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
+{
+        u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE);
+        u32 base_freq, frac_freq;
+
+        base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
+                     GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
+        base_freq *= 1000;
+
+        frac_freq = ((ts_override &
+                      GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
+                     GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
+        frac_freq = 1000 / (frac_freq + 1);
+
+        return base_freq + frac_freq;
+}
+
+static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
+{
+        u32 f12_5_mhz = 12500;
+        u32 f19_2_mhz = 19200;
+        u32 f24_mhz = 24000;
+
+        if (INTEL_GEN(dev_priv) <= 4) {
+                /* PRMs say:
+                 *
+                 *     "The value in this register increments once every 16
+                 *      hclks." (through the “Clocking Configuration”
+                 *      (“CLKCFG”) MCHBAR register)
+                 */
+                return dev_priv->rawclk_freq / 16;
+        } else if (INTEL_GEN(dev_priv) <= 8) {
+                /* PRMs say:
+                 *
+                 *     "The PCU TSC counts 10ns increments; this timestamp
+                 *      reflects bits 38:3 of the TSC (i.e. 80ns granularity,
+                 *      rolling over every 1.5 hours).
+                 */
+                return f12_5_mhz;
+        } else if (INTEL_GEN(dev_priv) <= 9) {
+                u32 ctc_reg = I915_READ(CTC_MODE);
+                u32 freq = 0;
+
+                if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
+                        freq = read_reference_ts_freq(dev_priv);
+                } else {
+                        freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz;
+
+                        /* Now figure out how the command stream's timestamp
+                         * register increments from this frequency (it might
+                         * increment only every few clock cycle).
+                         */
+                        freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
+                                      CTC_SHIFT_PARAMETER_SHIFT);
+                }
+
+                return freq;
+        } else if (INTEL_GEN(dev_priv) <= 10) {
+                u32 ctc_reg = I915_READ(CTC_MODE);
+                u32 freq = 0;
+                u32 rpm_config_reg = 0;
+
+                /* First figure out the reference frequency. There are 2 ways
+                 * we can compute the frequency, either through the
+                 * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
+                 * tells us which one we should use.
+                 */
+                if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
+                        freq = read_reference_ts_freq(dev_priv);
+                } else {
+                        u32 crystal_clock;
+
+                        rpm_config_reg = I915_READ(RPM_CONFIG0);
+                        crystal_clock = (rpm_config_reg &
+                                         GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
+                                GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
+                        switch (crystal_clock) {
+                        case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
+                                freq = f19_2_mhz;
+                                break;
+                        case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
+                                freq = f24_mhz;
+                                break;
+                        }
+                }
+
+                /* Now figure out how the command stream's timestamp register
+                 * increments from this frequency (it might increment only
+                 * every few clock cycle).
+                 */
+                freq >>= 3 - ((rpm_config_reg &
+                               GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
+                              GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
+
+                return freq;
+        }
+
+        DRM_ERROR("Unknown gen, unable to compute command stream timestamp frequency\n");
+        return 0;
+}
+
 /*
  * Determine various intel_device_info fields at runtime.
  *
@@ -347,7 +438,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
         struct intel_device_info *info = mkwrite_device_info(dev_priv);
         enum pipe pipe;
 
-        if (INTEL_GEN(dev_priv) >= 9) {
+        if (INTEL_GEN(dev_priv) >= 10) {
+                for_each_pipe(dev_priv, pipe)
+                        info->num_scalers[pipe] = 2;
+        } else if (INTEL_GEN(dev_priv) == 9) {
                 info->num_scalers[PIPE_A] = 2;
                 info->num_scalers[PIPE_B] = 2;
                 info->num_scalers[PIPE_C] = 1;
@@ -447,6 +541,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
         else if (INTEL_GEN(dev_priv) >= 10)
                 gen10_sseu_info_init(dev_priv);
 
+        /* Initialize command stream timestamp frequency */
+        info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
+
         DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
         DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
         DRM_DEBUG_DRIVER("subslice total: %u\n",
@@ -462,4 +559,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
                          info->sseu.has_subslice_pg ? "y" : "n");
         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
                          info->sseu.has_eu_pg ? "y" : "n");
+        DRM_DEBUG_DRIVER("CS timestamp frequency: %u kHz\n",
+                         info->cs_timestamp_frequency_khz);
 }