1 files changed, 4 insertions, 88 deletions
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 3c83b47b5f69..3c3b2d24e830 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -24,94 +24,10 @@
 #ifndef _I915_VGPU_H_
 #define _I915_VGPU_H_
-/* The MMIO offset of the shared info between guest and host emulator */
+#include "i915_pvinfo.h"
-#define VGT_PVINFO_PAGE 0x78000
-#define VGT_PVINFO_SIZE 0x1000
-/*
+void i915_check_vgpu(struct drm_i915_private *dev_priv);
- * The following structure pages are defined in GEN MMIO space
+int intel_vgt_balloon(struct drm_i915_private *dev_priv);
- * for virtualization. (One page for now)
+void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
- */
-#define VGT_MAGIC         0x4776544776544776ULL /* 'vGTvGTvG' */
-#define VGT_VERSION_MAJOR 1
-#define VGT_VERSION_MINOR 0
-#define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor))
-#define INTEL_VGT_IF_VERSION \
-        INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
-/*
- * notifications from guest to vgpu device model
- */
-enum vgt_g2v_type {
-        VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
-        VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
-        VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
-        VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
-        VGT_G2V_EXECLIST_CONTEXT_CREATE,
-        VGT_G2V_EXECLIST_CONTEXT_DESTROY,
-        VGT_G2V_MAX,
-};
-struct vgt_if {
-        uint64_t magic;         /* VGT_MAGIC */
-        uint16_t version_major;
-        uint16_t version_minor;
-        uint32_t vgt_id;        /* ID of vGT instance */
-        uint32_t rsv1[12];      /* pad to offset 0x40 */
-        /*
-         *  Data structure to describe the balooning info of resources.
-         *  Each VM can only have one portion of continuous area for now.
-         *  (May support scattered resource in future)
-         *  (starting from offset 0x40)
-         */
-        struct {
-                /* Aperture register balooning */
-                struct {
-                        uint32_t base;
-                        uint32_t size;
-                } mappable_gmadr;       /* aperture */
-                /* GMADR register balooning */
-                struct {
-                        uint32_t base;
-                        uint32_t size;
-                } nonmappable_gmadr;    /* non aperture */
-                /* allowed fence registers */
-                uint32_t fence_num;
-                uint32_t rsv2[3];
-        } avail_rs;             /* available/assigned resource */
-        uint32_t rsv3[0x200 - 24];      /* pad to half page */
-        /*
-         * The bottom half page is for response from Gfx driver to hypervisor.
-         */
-        uint32_t rsv4;
-        uint32_t display_ready; /* ready for display owner switch */
-        uint32_t rsv5[4];
-        uint32_t g2v_notify;
-        uint32_t rsv6[7];
-        struct {
-                uint32_t lo;
-                uint32_t hi;
-        } pdp[4];
-        uint32_t execlist_context_descriptor_lo;
-        uint32_t execlist_context_descriptor_hi;
-        uint32_t  rsv7[0x200 - 24];    /* pad to one page */
-} __packed;
-#define vgtif_reg(x) \
-        _MMIO((VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x))
-/* vGPU display status to be used by the host side */
-#define VGT_DRV_DISPLAY_NOT_READY 0
-#define VGT_DRV_DISPLAY_READY     1  /* ready for display switch */
-extern void i915_check_vgpu(struct drm_device *dev);
-extern int intel_vgt_balloon(struct drm_device *dev);
-extern void intel_vgt_deballoon(void);
 #endif /* _I915_VGPU_H_ */

diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h index 3c83b47b5f69..3c3b2d24e830 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.h +++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -24,94 +24,10 @@
24	#ifndef _I915_VGPU_H_	24	#ifndef _I915_VGPU_H_
25	#define _I915_VGPU_H_	25	#define _I915_VGPU_H_
26		26
27	/* The MMIO offset of the shared info between guest and host emulator */	27	#include "i915_pvinfo.h"
28	#define VGT_PVINFO_PAGE 0x78000
29	#define VGT_PVINFO_SIZE 0x1000
30		28
31	/*	29	void i915_check_vgpu(struct drm_i915_private *dev_priv);
32	* The following structure pages are defined in GEN MMIO space	30	int intel_vgt_balloon(struct drm_i915_private *dev_priv);
33	* for virtualization. (One page for now)	31	void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
34	*/
35	#define VGT_MAGIC 0x4776544776544776ULL /* 'vGTvGTvG' */
36	#define VGT_VERSION_MAJOR 1
37	#define VGT_VERSION_MINOR 0
38
39	#define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 \| (minor))
40	#define INTEL_VGT_IF_VERSION \
41	INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
42
43	/*
44	* notifications from guest to vgpu device model
45	*/
46	enum vgt_g2v_type {
47	VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
48	VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
49	VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
50	VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
51	VGT_G2V_EXECLIST_CONTEXT_CREATE,
52	VGT_G2V_EXECLIST_CONTEXT_DESTROY,
53	VGT_G2V_MAX,
54	};
55
56	struct vgt_if {
57	uint64_t magic; /* VGT_MAGIC */
58	uint16_t version_major;
59	uint16_t version_minor;
60	uint32_t vgt_id; /* ID of vGT instance */
61	uint32_t rsv1[12]; /* pad to offset 0x40 */
62	/*
63	* Data structure to describe the balooning info of resources.
64	* Each VM can only have one portion of continuous area for now.
65	* (May support scattered resource in future)
66	* (starting from offset 0x40)
67	*/
68	struct {
69	/* Aperture register balooning */
70	struct {
71	uint32_t base;
72	uint32_t size;
73	} mappable_gmadr; /* aperture */
74	/* GMADR register balooning */
75	struct {
76	uint32_t base;
77	uint32_t size;
78	} nonmappable_gmadr; /* non aperture */
79	/* allowed fence registers */
80	uint32_t fence_num;
81	uint32_t rsv2[3];
82	} avail_rs; /* available/assigned resource */
83	uint32_t rsv3[0x200 - 24]; /* pad to half page */
84	/*
85	* The bottom half page is for response from Gfx driver to hypervisor.
86	*/
87	uint32_t rsv4;
88	uint32_t display_ready; /* ready for display owner switch */
89
90	uint32_t rsv5[4];
91
92	uint32_t g2v_notify;
93	uint32_t rsv6[7];
94
95	struct {
96	uint32_t lo;
97	uint32_t hi;
98	} pdp[4];
99
100	uint32_t execlist_context_descriptor_lo;
101	uint32_t execlist_context_descriptor_hi;
102
103	uint32_t rsv7[0x200 - 24]; /* pad to one page */
104	} __packed;
105
106	#define vgtif_reg(x) \
107	_MMIO((VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x))
108
109	/* vGPU display status to be used by the host side */
110	#define VGT_DRV_DISPLAY_NOT_READY 0
111	#define VGT_DRV_DISPLAY_READY 1 /* ready for display switch */
112
113	extern void i915_check_vgpu(struct drm_device *dev);
114	extern int intel_vgt_balloon(struct drm_device *dev);
115	extern void intel_vgt_deballoon(void);
116		32
117	#endif /* _I915_VGPU_H_ */	33	#endif /* _I915_VGPU_H_ */