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path: root/drivers/gpu/drm/i915/i915_reg.h
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h11
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 273162579e1b..90600d899413 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -184,14 +184,15 @@
184 * Fence registers 184 * Fence registers
185 */ 185 */
186#define FENCE_REG_830_0 0x2000 186#define FENCE_REG_830_0 0x2000
187#define FENCE_REG_945_8 0x3000
187#define I830_FENCE_START_MASK 0x07f80000 188#define I830_FENCE_START_MASK 0x07f80000
188#define I830_FENCE_TILING_Y_SHIFT 12 189#define I830_FENCE_TILING_Y_SHIFT 12
189#define I830_FENCE_SIZE_BITS(size) ((get_order(size >> 19) - 1) << 8) 190#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
190#define I830_FENCE_PITCH_SHIFT 4 191#define I830_FENCE_PITCH_SHIFT 4
191#define I830_FENCE_REG_VALID (1<<0) 192#define I830_FENCE_REG_VALID (1<<0)
192 193
193#define I915_FENCE_START_MASK 0x0ff00000 194#define I915_FENCE_START_MASK 0x0ff00000
194#define I915_FENCE_SIZE_BITS(size) ((get_order(size >> 20) - 1) << 8) 195#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
195 196
196#define FENCE_REG_965_0 0x03000 197#define FENCE_REG_965_0 0x03000
197#define I965_FENCE_PITCH_SHIFT 2 198#define I965_FENCE_PITCH_SHIFT 2
@@ -1371,6 +1372,9 @@
1371#define PIPE_FRAME_LOW_SHIFT 24 1372#define PIPE_FRAME_LOW_SHIFT 24
1372#define PIPE_PIXEL_MASK 0x00ffffff 1373#define PIPE_PIXEL_MASK 0x00ffffff
1373#define PIPE_PIXEL_SHIFT 0 1374#define PIPE_PIXEL_SHIFT 0
1375/* GM45+ just has to be different */
1376#define PIPEA_FRMCOUNT_GM45 0x70040
1377#define PIPEA_FLIPCOUNT_GM45 0x70044
1374 1378
1375/* Cursor A & B regs */ 1379/* Cursor A & B regs */
1376#define CURACNTR 0x70080 1380#define CURACNTR 0x70080
@@ -1439,6 +1443,9 @@
1439#define PIPEBSTAT 0x71024 1443#define PIPEBSTAT 0x71024
1440#define PIPEBFRAMEHIGH 0x71040 1444#define PIPEBFRAMEHIGH 0x71040
1441#define PIPEBFRAMEPIXEL 0x71044 1445#define PIPEBFRAMEPIXEL 0x71044
1446#define PIPEB_FRMCOUNT_GM45 0x71040
1447#define PIPEB_FLIPCOUNT_GM45 0x71044
1448
1442 1449
1443/* Display B control */ 1450/* Display B control */
1444#define DSPBCNTR 0x71180 1451#define DSPBCNTR 0x71180