1 files changed, 221 insertions, 17 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4bfd7a9bd75f..0424e45f88db 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -139,19 +139,35 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
         return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
 }
 
+/*
+ * Given the first two numbers __a and __b of arbitrarily many evenly spaced
+ * numbers, pick the 0-based __index'th value.
+ *
+ * Always prefer this over _PICK() if the numbers are evenly spaced.
+ */
+#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
+
+/*
+ * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
+ *
+ * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
+ */
 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
 
-#define _PIPE(pipe, a, b) ((a) + (pipe) * ((b) - (a)))
+/*
+ * Named helper wrappers around _PICK_EVEN() and _PICK().
+ */
+#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
-#define _PLANE(plane, a, b) _PIPE(plane, a, b)
+#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
 #define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
-#define _TRANS(tran, a, b) ((a) + (tran) * ((b) - (a)))
+#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
-#define _PORT(port, a, b) ((a) + (port) * ((b) - (a)))
+#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
-#define _PLL(pll, a, b) ((a) + (pll) * ((b) - (a)))
+#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
@@ -1045,13 +1061,13 @@ enum i915_power_well_id {
 
         /*
          * HSW/BDW
-         *  - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1)
+         *  - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: id*2+1)
          */
         HSW_DISP_PW_GLOBAL = 15,
 
         /*
          * GEN9+
-         *  - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1)
+         *  - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: id*2+1)
          */
         SKL_DISP_PW_MISC_IO = 0,
         SKL_DISP_PW_DDI_A_E,
@@ -1075,17 +1091,54 @@ enum i915_power_well_id {
         SKL_DISP_PW_2,
 
         /* - custom power wells */
-        SKL_DISP_PW_DC_OFF,
         BXT_DPIO_CMN_A,
         BXT_DPIO_CMN_BC,
-        GLK_DPIO_CMN_C,                 /* 19 */
+        GLK_DPIO_CMN_C,                 /* 18 */
+
+        /*
+         * GEN11+
+         *  - _HSW_PWR_WELL_CTL1-4
+         *    (status bit: (id&15)*2, req bit:(id&15)*2+1)
+         */
+        ICL_DISP_PW_1 = 0,
+        ICL_DISP_PW_2,
+        ICL_DISP_PW_3,
+        ICL_DISP_PW_4,
+
+        /*
+         *  - _HSW_PWR_WELL_CTL_AUX1/2/4
+         *    (status bit: (id&15)*2, req bit:(id&15)*2+1)
+         */
+        ICL_DISP_PW_AUX_A = 16,
+        ICL_DISP_PW_AUX_B,
+        ICL_DISP_PW_AUX_C,
+        ICL_DISP_PW_AUX_D,
+        ICL_DISP_PW_AUX_E,
+        ICL_DISP_PW_AUX_F,
+
+        ICL_DISP_PW_AUX_TBT1 = 24,
+        ICL_DISP_PW_AUX_TBT2,
+        ICL_DISP_PW_AUX_TBT3,
+        ICL_DISP_PW_AUX_TBT4,
+
+        /*
+         *  - _HSW_PWR_WELL_CTL_DDI1/2/4
+         *    (status bit: (id&15)*2, req bit:(id&15)*2+1)
+         */
+        ICL_DISP_PW_DDI_A = 32,
+        ICL_DISP_PW_DDI_B,
+        ICL_DISP_PW_DDI_C,
+        ICL_DISP_PW_DDI_D,
+        ICL_DISP_PW_DDI_E,
+        ICL_DISP_PW_DDI_F,                      /* 37 */
 
         /*
          * Multiple platforms.
          * Must start following the highest ID of any platform.
          * - custom power wells
          */
-        I915_DISP_PW_ALWAYS_ON = 20,
+        SKL_DISP_PW_DC_OFF = 38,
+        I915_DISP_PW_ALWAYS_ON,
 };
 
 #define PUNIT_REG_PWRGT_CTRL                    0x60
@@ -1667,6 +1720,26 @@ enum i915_power_well_id {
 #define ICL_PORT_CL_DW5(port)   _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
                                                  _ICL_PORT_CL_DW5_B)
 
+#define _CNL_PORT_CL_DW10_A             0x162028
+#define _ICL_PORT_CL_DW10_B             0x6c028
+#define ICL_PORT_CL_DW10(port)          _MMIO_PORT(port,        \
+                                                   _CNL_PORT_CL_DW10_A, \
+                                                   _ICL_PORT_CL_DW10_B)
+#define  PG_SEQ_DELAY_OVERRIDE_MASK     (3 << 25)
+#define  PG_SEQ_DELAY_OVERRIDE_SHIFT    25
+#define  PG_SEQ_DELAY_OVERRIDE_ENABLE   (1 << 24)
+#define  PWR_UP_ALL_LANES               (0x0 << 4)
+#define  PWR_DOWN_LN_3_2_1              (0xe << 4)
+#define  PWR_DOWN_LN_3_2                (0xc << 4)
+#define  PWR_DOWN_LN_3                  (0x8 << 4)
+#define  PWR_DOWN_LN_2_1_0              (0x7 << 4)
+#define  PWR_DOWN_LN_1_0                (0x3 << 4)
+#define  PWR_DOWN_LN_1                  (0x2 << 4)
+#define  PWR_DOWN_LN_3_1                (0xa << 4)
+#define  PWR_DOWN_LN_3_1_0              (0xb << 4)
+#define  PWR_DOWN_LN_MASK               (0xf << 4)
+#define  PWR_DOWN_LN_SHIFT              4
+
 #define _PORT_CL1CM_DW9_A               0x162024
 #define _PORT_CL1CM_DW9_BC              0x6C024
 #define   IREF0RC_OFFSET_SHIFT          8
@@ -1679,6 +1752,13 @@ enum i915_power_well_id {
 #define   IREF1RC_OFFSET_MASK           (0xFF << IREF1RC_OFFSET_SHIFT)
 #define BXT_PORT_CL1CM_DW10(phy)        _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
 
+#define _ICL_PORT_CL_DW12_A             0x162030
+#define _ICL_PORT_CL_DW12_B             0x6C030
+#define   ICL_LANE_ENABLE_AUX           (1 << 0)
+#define ICL_PORT_CL_DW12(port)          _MMIO_PORT((port),              \
+                                                   _ICL_PORT_CL_DW12_A, \
+                                                   _ICL_PORT_CL_DW12_B)
+
 #define _PORT_CL1CM_DW28_A              0x162070
 #define _PORT_CL1CM_DW28_BC             0x6C070
 #define   OCL1_POWER_DOWN_EN            (1 << 23)
@@ -1716,16 +1796,22 @@ enum i915_power_well_id {
                                                     _CNL_PORT_PCS_DW1_LN0_D, \
                                                     _CNL_PORT_PCS_DW1_LN0_AE, \
                                                     _CNL_PORT_PCS_DW1_LN0_F))
+
 #define _ICL_PORT_PCS_DW1_GRP_A         0x162604
 #define _ICL_PORT_PCS_DW1_GRP_B         0x6C604
 #define _ICL_PORT_PCS_DW1_LN0_A         0x162804
 #define _ICL_PORT_PCS_DW1_LN0_B         0x6C804
+#define _ICL_PORT_PCS_DW1_AUX_A         0x162304
+#define _ICL_PORT_PCS_DW1_AUX_B         0x6c304
 #define ICL_PORT_PCS_DW1_GRP(port)      _MMIO_PORT(port,\
                                                    _ICL_PORT_PCS_DW1_GRP_A, \
                                                    _ICL_PORT_PCS_DW1_GRP_B)
 #define ICL_PORT_PCS_DW1_LN0(port)      _MMIO_PORT(port, \
                                                    _ICL_PORT_PCS_DW1_LN0_A, \
                                                    _ICL_PORT_PCS_DW1_LN0_B)
+#define ICL_PORT_PCS_DW1_AUX(port)      _MMIO_PORT(port, \
+                                                   _ICL_PORT_PCS_DW1_AUX_A, \
+                                                   _ICL_PORT_PCS_DW1_AUX_B)
 #define   COMMON_KEEPER_EN              (1 << 26)
 
 /* CNL Port TX registers */
@@ -1762,16 +1848,23 @@ enum i915_power_well_id {
 #define _ICL_PORT_TX_DW2_GRP_B          0x6C688
 #define _ICL_PORT_TX_DW2_LN0_A          0x162888
 #define _ICL_PORT_TX_DW2_LN0_B          0x6C888
+#define _ICL_PORT_TX_DW2_AUX_A          0x162388
+#define _ICL_PORT_TX_DW2_AUX_B          0x6c388
 #define ICL_PORT_TX_DW2_GRP(port)       _MMIO_PORT(port, \
                                                    _ICL_PORT_TX_DW2_GRP_A, \
                                                    _ICL_PORT_TX_DW2_GRP_B)
 #define ICL_PORT_TX_DW2_LN0(port)       _MMIO_PORT(port, \
                                                    _ICL_PORT_TX_DW2_LN0_A, \
                                                    _ICL_PORT_TX_DW2_LN0_B)
+#define ICL_PORT_TX_DW2_AUX(port)       _MMIO_PORT(port, \
+                                                   _ICL_PORT_TX_DW2_AUX_A, \
+                                                   _ICL_PORT_TX_DW2_AUX_B)
 #define   SWING_SEL_UPPER(x)            (((x) >> 3) << 15)
 #define   SWING_SEL_UPPER_MASK          (1 << 15)
 #define   SWING_SEL_LOWER(x)            (((x) & 0x7) << 11)
 #define   SWING_SEL_LOWER_MASK          (0x7 << 11)
+#define   FRC_LATENCY_OPTIM_MASK        (0x7 << 8)
+#define   FRC_LATENCY_OPTIM_VAL(x)      ((x) << 8)
 #define   RCOMP_SCALAR(x)               ((x) << 0)
 #define   RCOMP_SCALAR_MASK             (0xFF << 0)
 
@@ -1787,6 +1880,8 @@ enum i915_power_well_id {
 #define _ICL_PORT_TX_DW4_LN0_A          0x162890
 #define _ICL_PORT_TX_DW4_LN1_A          0x162990
 #define _ICL_PORT_TX_DW4_LN0_B          0x6C890
+#define _ICL_PORT_TX_DW4_AUX_A          0x162390
+#define _ICL_PORT_TX_DW4_AUX_B          0x6c390
 #define ICL_PORT_TX_DW4_GRP(port)       _MMIO_PORT(port, \
                                                    _ICL_PORT_TX_DW4_GRP_A, \
                                                    _ICL_PORT_TX_DW4_GRP_B)
@@ -1795,6 +1890,9 @@ enum i915_power_well_id {
                                                    _ICL_PORT_TX_DW4_LN0_B) + \
                                              ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
                                                       _ICL_PORT_TX_DW4_LN0_A)))
+#define ICL_PORT_TX_DW4_AUX(port)       _MMIO_PORT(port, \
+                                                   _ICL_PORT_TX_DW4_AUX_A, \
+                                                   _ICL_PORT_TX_DW4_AUX_B)
 #define   LOADGEN_SELECT                (1 << 31)
 #define   POST_CURSOR_1(x)              ((x) << 12)
 #define   POST_CURSOR_1_MASK            (0x3F << 12)
@@ -1809,12 +1907,17 @@ enum i915_power_well_id {
 #define _ICL_PORT_TX_DW5_GRP_B          0x6C694
 #define _ICL_PORT_TX_DW5_LN0_A          0x162894
 #define _ICL_PORT_TX_DW5_LN0_B          0x6C894
+#define _ICL_PORT_TX_DW5_AUX_A          0x162394
+#define _ICL_PORT_TX_DW5_AUX_B          0x6c394
 #define ICL_PORT_TX_DW5_GRP(port)       _MMIO_PORT(port, \
                                                    _ICL_PORT_TX_DW5_GRP_A, \
                                                    _ICL_PORT_TX_DW5_GRP_B)
 #define ICL_PORT_TX_DW5_LN0(port)       _MMIO_PORT(port, \
                                                    _ICL_PORT_TX_DW5_LN0_A, \
                                                    _ICL_PORT_TX_DW5_LN0_B)
+#define ICL_PORT_TX_DW5_AUX(port)       _MMIO_PORT(port, \
+                                                   _ICL_PORT_TX_DW5_AUX_A, \
+                                                   _ICL_PORT_TX_DW5_AUX_B)
 #define   TX_TRAINING_EN                (1 << 31)
 #define   TAP2_DISABLE                  (1 << 30)
 #define   TAP3_DISABLE                  (1 << 29)
@@ -2811,7 +2914,6 @@ enum i915_power_well_id {
 #define I915_DISPLAY_PORT_INTERRUPT                     (1 << 17)
 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT            (1 << 16)
 #define I915_MASTER_ERROR_INTERRUPT                     (1 << 15)
-#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT      (1 << 15)
 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT            (1 << 14)
 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT        (1 << 14) /* p-state */
 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT            (1 << 13)
@@ -4044,6 +4146,7 @@ enum {
 #define   EDP_PSR_SKIP_AUX_EXIT                 (1 << 12)
 #define   EDP_PSR_TP1_TP2_SEL                   (0 << 11)
 #define   EDP_PSR_TP1_TP3_SEL                   (1 << 11)
+#define   EDP_PSR_CRC_ENABLE                    (1 << 10) /* BDW+ */
 #define   EDP_PSR_TP2_TP3_TIME_500us            (0 << 8)
 #define   EDP_PSR_TP2_TP3_TIME_100us            (1 << 8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us           (2 << 8)
@@ -4072,6 +4175,7 @@ enum {
 
 #define EDP_PSR_STATUS                          _MMIO(dev_priv->psr_mmio_base + 0x40)
 #define   EDP_PSR_STATUS_STATE_MASK             (7 << 29)
+#define   EDP_PSR_STATUS_STATE_SHIFT            29
 #define   EDP_PSR_STATUS_STATE_IDLE             (0 << 29)
 #define   EDP_PSR_STATUS_STATE_SRDONACK         (1 << 29)
 #define   EDP_PSR_STATUS_STATE_SRDENT           (2 << 29)
@@ -6829,7 +6933,7 @@ enum {
 #define _PS_ECC_STAT_2B     0x68AD0
 #define _PS_ECC_STAT_1C     0x691D0
 
-#define _ID(id, a, b) ((a) + (id) * ((b) - (a)))
+#define _ID(id, a, b) _PICK_EVEN(id, a, b)
 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe,        \
                         _ID(id, _PS_1A_CTRL, _PS_2A_CTRL),       \
                         _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
@@ -7366,6 +7470,14 @@ enum {
 #define BDW_SCRATCH1                                    _MMIO(0xb11c)
 #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE      (1 << 2)
 
+/*GEN11 chicken */
+#define _PIPEA_CHICKEN                  0x70038
+#define _PIPEB_CHICKEN                  0x71038
+#define _PIPEC_CHICKEN                  0x72038
+#define  PER_PIXEL_ALPHA_BYPASS_EN      (1 << 7)
+#define PIPE_CHICKEN(pipe)              _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
+                                                   _PIPEB_CHICKEN)
+
 /* PCH */
 
 /* south display engine interrupt: IBX */
@@ -7409,7 +7521,7 @@ enum {
 #define SDE_TRANSA_FIFO_UNDER   (1 << 0)
 #define SDE_TRANS_MASK          (0x3f)
 
-/* south display engine interrupt: CPT/PPT */
+/* south display engine interrupt: CPT - CNP */
 #define SDE_AUDIO_POWER_D_CPT   (1 << 31)
 #define SDE_AUDIO_POWER_C_CPT   (1 << 30)
 #define SDE_AUDIO_POWER_B_CPT   (1 << 29)
@@ -7457,6 +7569,21 @@ enum {
                                  SDE_FDI_RXB_CPT | \
                                  SDE_FDI_RXA_CPT)
 
+/* south display engine interrupt: ICP */
+#define SDE_TC4_HOTPLUG_ICP             (1 << 27)
+#define SDE_TC3_HOTPLUG_ICP             (1 << 26)
+#define SDE_TC2_HOTPLUG_ICP             (1 << 25)
+#define SDE_TC1_HOTPLUG_ICP             (1 << 24)
+#define SDE_GMBUS_ICP                   (1 << 23)
+#define SDE_DDIB_HOTPLUG_ICP            (1 << 17)
+#define SDE_DDIA_HOTPLUG_ICP            (1 << 16)
+#define SDE_DDI_MASK_ICP                (SDE_DDIB_HOTPLUG_ICP | \
+                                         SDE_DDIA_HOTPLUG_ICP)
+#define SDE_TC_MASK_ICP                 (SDE_TC4_HOTPLUG_ICP |  \
+                                         SDE_TC3_HOTPLUG_ICP |  \
+                                         SDE_TC2_HOTPLUG_ICP |  \
+                                         SDE_TC1_HOTPLUG_ICP)
+
 #define SDEISR  _MMIO(0xc4000)
 #define SDEIMR  _MMIO(0xc4004)
 #define SDEIIR  _MMIO(0xc4008)
@@ -7517,6 +7644,30 @@ enum {
 #define  PORTE_HOTPLUG_SHORT_DETECT     (1 << 0)
 #define  PORTE_HOTPLUG_LONG_DETECT      (2 << 0)
 
+/* This register is a reuse of PCH_PORT_HOTPLUG register. The
+ * functionality covered in PCH_PORT_HOTPLUG is split into
+ * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
+ */
+
+#define SHOTPLUG_CTL_DDI                        _MMIO(0xc4030)
+#define   ICP_DDIB_HPD_ENABLE                   (1 << 7)
+#define   ICP_DDIB_HPD_STATUS_MASK              (3 << 4)
+#define   ICP_DDIB_HPD_NO_DETECT                (0 << 4)
+#define   ICP_DDIB_HPD_SHORT_DETECT             (1 << 4)
+#define   ICP_DDIB_HPD_LONG_DETECT              (2 << 4)
+#define   ICP_DDIB_HPD_SHORT_LONG_DETECT        (3 << 4)
+#define   ICP_DDIA_HPD_ENABLE                   (1 << 3)
+#define   ICP_DDIA_HPD_STATUS_MASK              (3 << 0)
+#define   ICP_DDIA_HPD_NO_DETECT                (0 << 0)
+#define   ICP_DDIA_HPD_SHORT_DETECT             (1 << 0)
+#define   ICP_DDIA_HPD_LONG_DETECT              (2 << 0)
+#define   ICP_DDIA_HPD_SHORT_LONG_DETECT        (3 << 0)
+
+#define SHOTPLUG_CTL_TC                         _MMIO(0xc4034)
+#define   ICP_TC_HPD_ENABLE(tc_port)            (8 << (tc_port) * 4)
+#define   ICP_TC_HPD_LONG_DETECT(tc_port)       (2 << (tc_port) * 4)
+#define   ICP_TC_HPD_SHORT_DETECT(tc_port)      (1 << (tc_port) * 4)
+
 #define PCH_GPIOA               _MMIO(0xc5010)
 #define PCH_GPIOB               _MMIO(0xc5014)
 #define PCH_GPIOC               _MMIO(0xc5018)
@@ -8555,6 +8706,14 @@ enum {
 #define _HSW_PWR_WELL_CTL3                      0x45408
 #define _HSW_PWR_WELL_CTL4                      0x4540C
 
+#define _ICL_PWR_WELL_CTL_AUX1                  0x45440
+#define _ICL_PWR_WELL_CTL_AUX2                  0x45444
+#define _ICL_PWR_WELL_CTL_AUX4                  0x4544C
+
+#define _ICL_PWR_WELL_CTL_DDI1                  0x45450
+#define _ICL_PWR_WELL_CTL_DDI2                  0x45454
+#define _ICL_PWR_WELL_CTL_DDI4                  0x4545C
+
 /*
  * Each power well control register contains up to 16 (request, status) HW
  * flag tuples. The register index and HW flag shift is determined by the
@@ -8564,14 +8723,20 @@ enum {
  */
 #define _HSW_PW_REG_IDX(pw)                     ((pw) >> 4)
 #define _HSW_PW_SHIFT(pw)                       (((pw) & 0xf) * 2)
-/* TODO: Add all PWR_WELL_CTL registers below for new platforms */
 #define HSW_PWR_WELL_CTL_BIOS(pw)       _MMIO(_PICK(_HSW_PW_REG_IDX(pw),       \
-                                                    _HSW_PWR_WELL_CTL1))
+                                                    _HSW_PWR_WELL_CTL1,        \
+                                                    _ICL_PWR_WELL_CTL_AUX1,    \
+                                                    _ICL_PWR_WELL_CTL_DDI1))
 #define HSW_PWR_WELL_CTL_DRIVER(pw)     _MMIO(_PICK(_HSW_PW_REG_IDX(pw),       \
-                                                    _HSW_PWR_WELL_CTL2))
+                                                    _HSW_PWR_WELL_CTL2,        \
+                                                    _ICL_PWR_WELL_CTL_AUX2,    \
+                                                    _ICL_PWR_WELL_CTL_DDI2))
+/* KVMR doesn't have a reg for AUX or DDI power well control */
 #define HSW_PWR_WELL_CTL_KVMR           _MMIO(_HSW_PWR_WELL_CTL3)
 #define HSW_PWR_WELL_CTL_DEBUG(pw)      _MMIO(_PICK(_HSW_PW_REG_IDX(pw),       \
-                                                    _HSW_PWR_WELL_CTL4))
+                                                    _HSW_PWR_WELL_CTL4,        \
+                                                    _ICL_PWR_WELL_CTL_AUX4,    \
+                                                    _ICL_PWR_WELL_CTL_DDI4))
 
 #define   HSW_PWR_WELL_CTL_REQ(pw)              (1 << (_HSW_PW_SHIFT(pw) + 1))
 #define   HSW_PWR_WELL_CTL_STATE(pw)            (1 << _HSW_PW_SHIFT(pw))
@@ -8592,6 +8757,8 @@ enum skl_power_gate {
 #define  SKL_FUSE_DOWNLOAD_STATUS               (1 << 31)
 /* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */
 #define  SKL_PW_TO_PG(pw)                       ((pw) - SKL_DISP_PW_1 + SKL_PG1)
+/* PG0 (HW control->no power well ID), PG1..PG4 (ICL_DISP_PW1..ICL_DISP_PW4) */
+#define  ICL_PW_TO_PG(pw)                       ((pw) - ICL_DISP_PW_1 + SKL_PG1)
 #define  SKL_FUSE_PG_DIST_STATUS(pg)            (1 << (27 - (pg)))
 
 #define _CNL_AUX_REG_IDX(pw)            ((pw) - 9)
@@ -9047,6 +9214,7 @@ enum skl_power_gate {
 #define _MG_REFCLKIN_CTL_PORT3                          0x16A92C
 #define _MG_REFCLKIN_CTL_PORT4                          0x16B92C
 #define   MG_REFCLKIN_CTL_OD_2_MUX(x)                   ((x) << 8)
+#define   MG_REFCLKIN_CTL_OD_2_MUX_MASK                 (0x7 << 8)
 #define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \
                                          _MG_REFCLKIN_CTL_PORT1, \
                                          _MG_REFCLKIN_CTL_PORT2)
@@ -9056,7 +9224,9 @@ enum skl_power_gate {
 #define _MG_CLKTOP2_CORECLKCTL1_PORT3                   0x16A8D8
 #define _MG_CLKTOP2_CORECLKCTL1_PORT4                   0x16B8D8
 #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x)          ((x) << 16)
+#define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK        (0xff << 16)
 #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x)          ((x) << 8)
+#define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK        (0xff << 8)
 #define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \
                                                 _MG_CLKTOP2_CORECLKCTL1_PORT1, \
                                                 _MG_CLKTOP2_CORECLKCTL1_PORT2)
@@ -9066,9 +9236,13 @@ enum skl_power_gate {
 #define _MG_CLKTOP2_HSCLKCTL_PORT3                      0x16A8D4
 #define _MG_CLKTOP2_HSCLKCTL_PORT4                      0x16B8D4
 #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x)          ((x) << 16)
+#define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK        (0x1 << 16)
 #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x)        ((x) << 14)
+#define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK      (0x3 << 14)
 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x)            ((x) << 12)
+#define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK          (0x3 << 12)
 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x)            ((x) << 8)
+#define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK          (0xf << 8)
 #define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
                                              _MG_CLKTOP2_HSCLKCTL_PORT1, \
                                              _MG_CLKTOP2_HSCLKCTL_PORT2)
@@ -9142,12 +9316,18 @@ enum skl_power_gate {
 #define _MG_PLL_BIAS_PORT3                              0x16AA14
 #define _MG_PLL_BIAS_PORT4                              0x16BA14
 #define   MG_PLL_BIAS_BIAS_GB_SEL(x)                    ((x) << 30)
+#define   MG_PLL_BIAS_BIAS_GB_SEL_MASK                  (0x3 << 30)
 #define   MG_PLL_BIAS_INIT_DCOAMP(x)                    ((x) << 24)
+#define   MG_PLL_BIAS_INIT_DCOAMP_MASK                  (0x3f << 24)
 #define   MG_PLL_BIAS_BIAS_BONUS(x)                     ((x) << 16)
+#define   MG_PLL_BIAS_BIAS_BONUS_MASK                   (0xff << 16)
 #define   MG_PLL_BIAS_BIASCAL_EN                        (1 << 15)
 #define   MG_PLL_BIAS_CTRIM(x)                          ((x) << 8)
+#define   MG_PLL_BIAS_CTRIM_MASK                        (0x1f << 8)
 #define   MG_PLL_BIAS_VREF_RDAC(x)                      ((x) << 5)
+#define   MG_PLL_BIAS_VREF_RDAC_MASK                    (0x7 << 5)
 #define   MG_PLL_BIAS_IREFTRIM(x)                       ((x) << 0)
+#define   MG_PLL_BIAS_IREFTRIM_MASK                     (0x1f << 0)
 #define MG_PLL_BIAS(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_BIAS_PORT1, \
                                      _MG_PLL_BIAS_PORT2)
 
@@ -9401,6 +9581,22 @@ enum skl_power_gate {
 #define MIPIO_TXESC_CLK_DIV2                    _MMIO(0x160008)
 #define  GLK_TX_ESC_CLK_DIV2_MASK                       0x3FF
 
+#define _ICL_DSI_ESC_CLK_DIV0           0x6b090
+#define _ICL_DSI_ESC_CLK_DIV1           0x6b890
+#define ICL_DSI_ESC_CLK_DIV(port)       _MMIO_PORT((port),      \
+                                                        _ICL_DSI_ESC_CLK_DIV0, \
+                                                        _ICL_DSI_ESC_CLK_DIV1)
+#define _ICL_DPHY_ESC_CLK_DIV0          0x162190
+#define _ICL_DPHY_ESC_CLK_DIV1          0x6C190
+#define ICL_DPHY_ESC_CLK_DIV(port)      _MMIO_PORT((port),      \
+                                                _ICL_DPHY_ESC_CLK_DIV0, \
+                                                _ICL_DPHY_ESC_CLK_DIV1)
+#define  ICL_BYTE_CLK_PER_ESC_CLK_MASK          (0x1f << 16)
+#define  ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16
+#define  ICL_ESC_CLK_DIV_MASK                   0x1ff
+#define  ICL_ESC_CLK_DIV_SHIFT                  0
+#define DSI_MAX_ESC_CLK                 20000           /* in KHz */
+
 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
 #define GEN4_TIMESTAMP          _MMIO(0x2358)
 #define ILK_TIMESTAMP_HI        _MMIO(0x70070)
@@ -9535,6 +9731,14 @@ enum skl_power_gate {
 #define _BXT_MIPIC_PORT_CTRL                            0x6B8C0
 #define BXT_MIPI_PORT_CTRL(tc)  _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
 
+/* ICL DSI MODE control */
+#define _ICL_DSI_IO_MODECTL_0                           0x6B094
+#define _ICL_DSI_IO_MODECTL_1                           0x6B894
+#define ICL_DSI_IO_MODECTL(port)        _MMIO_PORT(port,        \
+                                                    _ICL_DSI_IO_MODECTL_0, \
+                                                    _ICL_DSI_IO_MODECTL_1)
+#define  COMBO_PHY_MODE_DSI                             (1 << 0)
+
 #define BXT_P_DSI_REGULATOR_CFG                 _MMIO(0x160020)
 #define  STAP_SELECT                                    (1 << 0)