aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/i915_irq.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c311
1 files changed, 134 insertions, 177 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4378a659d962..1c2aec392412 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -259,12 +259,12 @@ static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
259 dev_priv->gt_irq_mask &= ~interrupt_mask; 259 dev_priv->gt_irq_mask &= ~interrupt_mask;
260 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); 260 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
261 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 261 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
262 POSTING_READ(GTIMR);
263} 262}
264 263
265void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) 264void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
266{ 265{
267 ilk_update_gt_irq(dev_priv, mask, mask); 266 ilk_update_gt_irq(dev_priv, mask, mask);
267 POSTING_READ_FW(GTIMR);
268} 268}
269 269
270void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) 270void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
@@ -351,9 +351,8 @@ void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
351void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) 351void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
352{ 352{
353 spin_lock_irq(&dev_priv->irq_lock); 353 spin_lock_irq(&dev_priv->irq_lock);
354 354 WARN_ON_ONCE(dev_priv->rps.pm_iir);
355 WARN_ON(dev_priv->rps.pm_iir); 355 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
356 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
357 dev_priv->rps.interrupts_enabled = true; 356 dev_priv->rps.interrupts_enabled = true;
358 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | 357 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
359 dev_priv->pm_rps_events); 358 dev_priv->pm_rps_events);
@@ -371,11 +370,6 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
371{ 370{
372 spin_lock_irq(&dev_priv->irq_lock); 371 spin_lock_irq(&dev_priv->irq_lock);
373 dev_priv->rps.interrupts_enabled = false; 372 dev_priv->rps.interrupts_enabled = false;
374 spin_unlock_irq(&dev_priv->irq_lock);
375
376 cancel_work_sync(&dev_priv->rps.work);
377
378 spin_lock_irq(&dev_priv->irq_lock);
379 373
380 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0)); 374 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
381 375
@@ -384,8 +378,15 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
384 ~dev_priv->pm_rps_events); 378 ~dev_priv->pm_rps_events);
385 379
386 spin_unlock_irq(&dev_priv->irq_lock); 380 spin_unlock_irq(&dev_priv->irq_lock);
381 synchronize_irq(dev_priv->drm.irq);
387 382
388 synchronize_irq(dev_priv->dev->irq); 383 /* Now that we will not be generating any more work, flush any
384 * outsanding tasks. As we are called on the RPS idle path,
385 * we will reset the GPU to minimum frequencies, so the current
386 * state of the worker can be discarded.
387 */
388 cancel_work_sync(&dev_priv->rps.work);
389 gen6_reset_rps_interrupts(dev_priv);
389} 390}
390 391
391/** 392/**
@@ -565,7 +566,7 @@ i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
565 u32 enable_mask; 566 u32 enable_mask;
566 567
567 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 568 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
568 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, 569 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
569 status_mask); 570 status_mask);
570 else 571 else
571 enable_mask = status_mask << 16; 572 enable_mask = status_mask << 16;
@@ -579,7 +580,7 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
579 u32 enable_mask; 580 u32 enable_mask;
580 581
581 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 582 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
582 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, 583 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
583 status_mask); 584 status_mask);
584 else 585 else
585 enable_mask = status_mask << 16; 586 enable_mask = status_mask << 16;
@@ -666,7 +667,7 @@ static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
666 */ 667 */
667static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe) 668static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
668{ 669{
669 struct drm_i915_private *dev_priv = dev->dev_private; 670 struct drm_i915_private *dev_priv = to_i915(dev);
670 i915_reg_t high_frame, low_frame; 671 i915_reg_t high_frame, low_frame;
671 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; 672 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
672 struct intel_crtc *intel_crtc = 673 struct intel_crtc *intel_crtc =
@@ -713,7 +714,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
713 714
714static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe) 715static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
715{ 716{
716 struct drm_i915_private *dev_priv = dev->dev_private; 717 struct drm_i915_private *dev_priv = to_i915(dev);
717 718
718 return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); 719 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
719} 720}
@@ -722,7 +723,7 @@ static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
722static int __intel_get_crtc_scanline(struct intel_crtc *crtc) 723static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
723{ 724{
724 struct drm_device *dev = crtc->base.dev; 725 struct drm_device *dev = crtc->base.dev;
725 struct drm_i915_private *dev_priv = dev->dev_private; 726 struct drm_i915_private *dev_priv = to_i915(dev);
726 const struct drm_display_mode *mode = &crtc->base.hwmode; 727 const struct drm_display_mode *mode = &crtc->base.hwmode;
727 enum pipe pipe = crtc->pipe; 728 enum pipe pipe = crtc->pipe;
728 int position, vtotal; 729 int position, vtotal;
@@ -774,7 +775,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
774 ktime_t *stime, ktime_t *etime, 775 ktime_t *stime, ktime_t *etime,
775 const struct drm_display_mode *mode) 776 const struct drm_display_mode *mode)
776{ 777{
777 struct drm_i915_private *dev_priv = dev->dev_private; 778 struct drm_i915_private *dev_priv = to_i915(dev);
778 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 779 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
780 int position; 781 int position;
@@ -895,7 +896,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
895 896
896int intel_get_crtc_scanline(struct intel_crtc *crtc) 897int intel_get_crtc_scanline(struct intel_crtc *crtc)
897{ 898{
898 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 899 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
899 unsigned long irqflags; 900 unsigned long irqflags;
900 int position; 901 int position;
901 902
@@ -976,13 +977,11 @@ static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
976 977
977static void notify_ring(struct intel_engine_cs *engine) 978static void notify_ring(struct intel_engine_cs *engine)
978{ 979{
979 if (!intel_engine_initialized(engine)) 980 smp_store_mb(engine->breadcrumbs.irq_posted, true);
980 return; 981 if (intel_engine_wakeup(engine)) {
981 982 trace_i915_gem_request_notify(engine);
982 trace_i915_gem_request_notify(engine); 983 engine->breadcrumbs.irq_wakeups++;
983 engine->user_interrupts++; 984 }
984
985 wake_up_all(&engine->irq_queue);
986} 985}
987 986
988static void vlv_c0_read(struct drm_i915_private *dev_priv, 987static void vlv_c0_read(struct drm_i915_private *dev_priv,
@@ -1063,7 +1062,7 @@ static bool any_waiters(struct drm_i915_private *dev_priv)
1063 struct intel_engine_cs *engine; 1062 struct intel_engine_cs *engine;
1064 1063
1065 for_each_engine(engine, dev_priv) 1064 for_each_engine(engine, dev_priv)
1066 if (engine->irq_refcount) 1065 if (intel_engine_has_waiter(engine))
1067 return true; 1066 return true;
1068 1067
1069 return false; 1068 return false;
@@ -1084,13 +1083,6 @@ static void gen6_pm_rps_work(struct work_struct *work)
1084 return; 1083 return;
1085 } 1084 }
1086 1085
1087 /*
1088 * The RPS work is synced during runtime suspend, we don't require a
1089 * wakeref. TODO: instead of disabling the asserts make sure that we
1090 * always hold an RPM reference while the work is running.
1091 */
1092 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1093
1094 pm_iir = dev_priv->rps.pm_iir; 1086 pm_iir = dev_priv->rps.pm_iir;
1095 dev_priv->rps.pm_iir = 0; 1087 dev_priv->rps.pm_iir = 0;
1096 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ 1088 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
@@ -1103,7 +1095,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
1103 WARN_ON(pm_iir & ~dev_priv->pm_rps_events); 1095 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1104 1096
1105 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) 1097 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1106 goto out; 1098 return;
1107 1099
1108 mutex_lock(&dev_priv->rps.hw_lock); 1100 mutex_lock(&dev_priv->rps.hw_lock);
1109 1101
@@ -1158,8 +1150,6 @@ static void gen6_pm_rps_work(struct work_struct *work)
1158 intel_set_rps(dev_priv, new_delay); 1150 intel_set_rps(dev_priv, new_delay);
1159 1151
1160 mutex_unlock(&dev_priv->rps.hw_lock); 1152 mutex_unlock(&dev_priv->rps.hw_lock);
1161out:
1162 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1163} 1153}
1164 1154
1165 1155
@@ -1185,7 +1175,7 @@ static void ivybridge_parity_work(struct work_struct *work)
1185 * In order to prevent a get/put style interface, acquire struct mutex 1175 * In order to prevent a get/put style interface, acquire struct mutex
1186 * any time we access those registers. 1176 * any time we access those registers.
1187 */ 1177 */
1188 mutex_lock(&dev_priv->dev->struct_mutex); 1178 mutex_lock(&dev_priv->drm.struct_mutex);
1189 1179
1190 /* If we've screwed up tracking, just let the interrupt fire again */ 1180 /* If we've screwed up tracking, just let the interrupt fire again */
1191 if (WARN_ON(!dev_priv->l3_parity.which_slice)) 1181 if (WARN_ON(!dev_priv->l3_parity.which_slice))
@@ -1221,7 +1211,7 @@ static void ivybridge_parity_work(struct work_struct *work)
1221 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); 1211 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1222 parity_event[5] = NULL; 1212 parity_event[5] = NULL;
1223 1213
1224 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, 1214 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1225 KOBJ_CHANGE, parity_event); 1215 KOBJ_CHANGE, parity_event);
1226 1216
1227 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", 1217 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
@@ -1241,7 +1231,7 @@ out:
1241 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); 1231 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1242 spin_unlock_irq(&dev_priv->irq_lock); 1232 spin_unlock_irq(&dev_priv->irq_lock);
1243 1233
1244 mutex_unlock(&dev_priv->dev->struct_mutex); 1234 mutex_unlock(&dev_priv->drm.struct_mutex);
1245} 1235}
1246 1236
1247static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv, 1237static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
@@ -1267,8 +1257,7 @@ static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv
1267static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv, 1257static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1268 u32 gt_iir) 1258 u32 gt_iir)
1269{ 1259{
1270 if (gt_iir & 1260 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1271 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1272 notify_ring(&dev_priv->engine[RCS]); 1261 notify_ring(&dev_priv->engine[RCS]);
1273 if (gt_iir & ILK_BSD_USER_INTERRUPT) 1262 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1274 notify_ring(&dev_priv->engine[VCS]); 1263 notify_ring(&dev_priv->engine[VCS]);
@@ -1277,9 +1266,7 @@ static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1277static void snb_gt_irq_handler(struct drm_i915_private *dev_priv, 1266static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1278 u32 gt_iir) 1267 u32 gt_iir)
1279{ 1268{
1280 1269 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1281 if (gt_iir &
1282 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1283 notify_ring(&dev_priv->engine[RCS]); 1270 notify_ring(&dev_priv->engine[RCS]);
1284 if (gt_iir & GT_BSD_USER_INTERRUPT) 1271 if (gt_iir & GT_BSD_USER_INTERRUPT)
1285 notify_ring(&dev_priv->engine[VCS]); 1272 notify_ring(&dev_priv->engine[VCS]);
@@ -1526,7 +1513,7 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1526 1513
1527 entry = &pipe_crc->entries[head]; 1514 entry = &pipe_crc->entries[head];
1528 1515
1529 entry->frame = dev_priv->dev->driver->get_vblank_counter(dev_priv->dev, 1516 entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm,
1530 pipe); 1517 pipe);
1531 entry->crc[0] = crc0; 1518 entry->crc[0] = crc0;
1532 entry->crc[1] = crc1; 1519 entry->crc[1] = crc1;
@@ -1602,7 +1589,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1602 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); 1589 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1603 if (dev_priv->rps.interrupts_enabled) { 1590 if (dev_priv->rps.interrupts_enabled) {
1604 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; 1591 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1605 queue_work(dev_priv->wq, &dev_priv->rps.work); 1592 schedule_work(&dev_priv->rps.work);
1606 } 1593 }
1607 spin_unlock(&dev_priv->irq_lock); 1594 spin_unlock(&dev_priv->irq_lock);
1608 } 1595 }
@@ -1624,7 +1611,7 @@ static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1624{ 1611{
1625 bool ret; 1612 bool ret;
1626 1613
1627 ret = drm_handle_vblank(dev_priv->dev, pipe); 1614 ret = drm_handle_vblank(&dev_priv->drm, pipe);
1628 if (ret) 1615 if (ret)
1629 intel_finish_page_flip_mmio(dev_priv, pipe); 1616 intel_finish_page_flip_mmio(dev_priv, pipe);
1630 1617
@@ -1757,7 +1744,7 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1757static irqreturn_t valleyview_irq_handler(int irq, void *arg) 1744static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1758{ 1745{
1759 struct drm_device *dev = arg; 1746 struct drm_device *dev = arg;
1760 struct drm_i915_private *dev_priv = dev->dev_private; 1747 struct drm_i915_private *dev_priv = to_i915(dev);
1761 irqreturn_t ret = IRQ_NONE; 1748 irqreturn_t ret = IRQ_NONE;
1762 1749
1763 if (!intel_irqs_enabled(dev_priv)) 1750 if (!intel_irqs_enabled(dev_priv))
@@ -1840,7 +1827,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1840static irqreturn_t cherryview_irq_handler(int irq, void *arg) 1827static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1841{ 1828{
1842 struct drm_device *dev = arg; 1829 struct drm_device *dev = arg;
1843 struct drm_i915_private *dev_priv = dev->dev_private; 1830 struct drm_i915_private *dev_priv = to_i915(dev);
1844 irqreturn_t ret = IRQ_NONE; 1831 irqreturn_t ret = IRQ_NONE;
1845 1832
1846 if (!intel_irqs_enabled(dev_priv)) 1833 if (!intel_irqs_enabled(dev_priv))
@@ -2225,7 +2212,7 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2225static irqreturn_t ironlake_irq_handler(int irq, void *arg) 2212static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2226{ 2213{
2227 struct drm_device *dev = arg; 2214 struct drm_device *dev = arg;
2228 struct drm_i915_private *dev_priv = dev->dev_private; 2215 struct drm_i915_private *dev_priv = to_i915(dev);
2229 u32 de_iir, gt_iir, de_ier, sde_ier = 0; 2216 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2230 irqreturn_t ret = IRQ_NONE; 2217 irqreturn_t ret = IRQ_NONE;
2231 2218
@@ -2438,7 +2425,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2438 I915_WRITE(SDEIIR, iir); 2425 I915_WRITE(SDEIIR, iir);
2439 ret = IRQ_HANDLED; 2426 ret = IRQ_HANDLED;
2440 2427
2441 if (HAS_PCH_SPT(dev_priv)) 2428 if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2442 spt_irq_handler(dev_priv, iir); 2429 spt_irq_handler(dev_priv, iir);
2443 else 2430 else
2444 cpt_irq_handler(dev_priv, iir); 2431 cpt_irq_handler(dev_priv, iir);
@@ -2457,7 +2444,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2457static irqreturn_t gen8_irq_handler(int irq, void *arg) 2444static irqreturn_t gen8_irq_handler(int irq, void *arg)
2458{ 2445{
2459 struct drm_device *dev = arg; 2446 struct drm_device *dev = arg;
2460 struct drm_i915_private *dev_priv = dev->dev_private; 2447 struct drm_i915_private *dev_priv = to_i915(dev);
2461 u32 master_ctl; 2448 u32 master_ctl;
2462 u32 gt_iir[4] = {}; 2449 u32 gt_iir[4] = {};
2463 irqreturn_t ret; 2450 irqreturn_t ret;
@@ -2488,11 +2475,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
2488 return ret; 2475 return ret;
2489} 2476}
2490 2477
2491static void i915_error_wake_up(struct drm_i915_private *dev_priv, 2478static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2492 bool reset_completed)
2493{ 2479{
2494 struct intel_engine_cs *engine;
2495
2496 /* 2480 /*
2497 * Notify all waiters for GPU completion events that reset state has 2481 * Notify all waiters for GPU completion events that reset state has
2498 * been changed, and that they need to restart their wait after 2482 * been changed, and that they need to restart their wait after
@@ -2501,18 +2485,10 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2501 */ 2485 */
2502 2486
2503 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ 2487 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2504 for_each_engine(engine, dev_priv) 2488 wake_up_all(&dev_priv->gpu_error.wait_queue);
2505 wake_up_all(&engine->irq_queue);
2506 2489
2507 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ 2490 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2508 wake_up_all(&dev_priv->pending_flip_queue); 2491 wake_up_all(&dev_priv->pending_flip_queue);
2509
2510 /*
2511 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2512 * reset state is cleared.
2513 */
2514 if (reset_completed)
2515 wake_up_all(&dev_priv->gpu_error.reset_queue);
2516} 2492}
2517 2493
2518/** 2494/**
@@ -2524,7 +2500,7 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2524 */ 2500 */
2525static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv) 2501static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2526{ 2502{
2527 struct kobject *kobj = &dev_priv->dev->primary->kdev->kobj; 2503 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2528 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; 2504 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2529 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; 2505 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2530 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; 2506 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
@@ -2577,7 +2553,7 @@ static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2577 * Note: The wake_up also serves as a memory barrier so that 2553 * Note: The wake_up also serves as a memory barrier so that
2578 * waiters see the update value of the reset counter atomic_t. 2554 * waiters see the update value of the reset counter atomic_t.
2579 */ 2555 */
2580 i915_error_wake_up(dev_priv, true); 2556 wake_up_all(&dev_priv->gpu_error.reset_queue);
2581 } 2557 }
2582} 2558}
2583 2559
@@ -2714,7 +2690,7 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
2714 * ensure that the waiters see the updated value of the reset 2690 * ensure that the waiters see the updated value of the reset
2715 * counter atomic_t. 2691 * counter atomic_t.
2716 */ 2692 */
2717 i915_error_wake_up(dev_priv, false); 2693 i915_error_wake_up(dev_priv);
2718 } 2694 }
2719 2695
2720 i915_reset_and_wakeup(dev_priv); 2696 i915_reset_and_wakeup(dev_priv);
@@ -2725,7 +2701,7 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
2725 */ 2701 */
2726static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe) 2702static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2727{ 2703{
2728 struct drm_i915_private *dev_priv = dev->dev_private; 2704 struct drm_i915_private *dev_priv = to_i915(dev);
2729 unsigned long irqflags; 2705 unsigned long irqflags;
2730 2706
2731 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2707 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2742,7 +2718,7 @@ static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2742 2718
2743static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) 2719static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2744{ 2720{
2745 struct drm_i915_private *dev_priv = dev->dev_private; 2721 struct drm_i915_private *dev_priv = to_i915(dev);
2746 unsigned long irqflags; 2722 unsigned long irqflags;
2747 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : 2723 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2748 DE_PIPE_VBLANK(pipe); 2724 DE_PIPE_VBLANK(pipe);
@@ -2756,7 +2732,7 @@ static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2756 2732
2757static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe) 2733static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2758{ 2734{
2759 struct drm_i915_private *dev_priv = dev->dev_private; 2735 struct drm_i915_private *dev_priv = to_i915(dev);
2760 unsigned long irqflags; 2736 unsigned long irqflags;
2761 2737
2762 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2738 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2769,7 +2745,7 @@ static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2769 2745
2770static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe) 2746static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2771{ 2747{
2772 struct drm_i915_private *dev_priv = dev->dev_private; 2748 struct drm_i915_private *dev_priv = to_i915(dev);
2773 unsigned long irqflags; 2749 unsigned long irqflags;
2774 2750
2775 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2751 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2784,7 +2760,7 @@ static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2784 */ 2760 */
2785static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe) 2761static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2786{ 2762{
2787 struct drm_i915_private *dev_priv = dev->dev_private; 2763 struct drm_i915_private *dev_priv = to_i915(dev);
2788 unsigned long irqflags; 2764 unsigned long irqflags;
2789 2765
2790 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2766 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2796,7 +2772,7 @@ static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2796 2772
2797static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) 2773static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2798{ 2774{
2799 struct drm_i915_private *dev_priv = dev->dev_private; 2775 struct drm_i915_private *dev_priv = to_i915(dev);
2800 unsigned long irqflags; 2776 unsigned long irqflags;
2801 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : 2777 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2802 DE_PIPE_VBLANK(pipe); 2778 DE_PIPE_VBLANK(pipe);
@@ -2808,7 +2784,7 @@ static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2808 2784
2809static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe) 2785static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2810{ 2786{
2811 struct drm_i915_private *dev_priv = dev->dev_private; 2787 struct drm_i915_private *dev_priv = to_i915(dev);
2812 unsigned long irqflags; 2788 unsigned long irqflags;
2813 2789
2814 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2790 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2819,7 +2795,7 @@ static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2819 2795
2820static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe) 2796static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2821{ 2797{
2822 struct drm_i915_private *dev_priv = dev->dev_private; 2798 struct drm_i915_private *dev_priv = to_i915(dev);
2823 unsigned long irqflags; 2799 unsigned long irqflags;
2824 2800
2825 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2801 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2835,9 +2811,9 @@ ring_idle(struct intel_engine_cs *engine, u32 seqno)
2835} 2811}
2836 2812
2837static bool 2813static bool
2838ipehr_is_semaphore_wait(struct drm_i915_private *dev_priv, u32 ipehr) 2814ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
2839{ 2815{
2840 if (INTEL_GEN(dev_priv) >= 8) { 2816 if (INTEL_GEN(engine->i915) >= 8) {
2841 return (ipehr >> 23) == 0x1c; 2817 return (ipehr >> 23) == 0x1c;
2842 } else { 2818 } else {
2843 ipehr &= ~MI_SEMAPHORE_SYNC_MASK; 2819 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
@@ -2908,7 +2884,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2908 return NULL; 2884 return NULL;
2909 2885
2910 ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); 2886 ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2911 if (!ipehr_is_semaphore_wait(engine->i915, ipehr)) 2887 if (!ipehr_is_semaphore_wait(engine, ipehr))
2912 return NULL; 2888 return NULL;
2913 2889
2914 /* 2890 /*
@@ -2966,7 +2942,7 @@ static int semaphore_passed(struct intel_engine_cs *engine)
2966 if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES) 2942 if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
2967 return -1; 2943 return -1;
2968 2944
2969 if (i915_seqno_passed(signaller->get_seqno(signaller), seqno)) 2945 if (i915_seqno_passed(intel_engine_get_seqno(signaller), seqno))
2970 return 1; 2946 return 1;
2971 2947
2972 /* cursory check for an unkickable deadlock */ 2948 /* cursory check for an unkickable deadlock */
@@ -3078,23 +3054,21 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
3078 return HANGCHECK_HUNG; 3054 return HANGCHECK_HUNG;
3079} 3055}
3080 3056
3081static unsigned kick_waiters(struct intel_engine_cs *engine) 3057static unsigned long kick_waiters(struct intel_engine_cs *engine)
3082{ 3058{
3083 struct drm_i915_private *i915 = engine->i915; 3059 struct drm_i915_private *i915 = engine->i915;
3084 unsigned user_interrupts = READ_ONCE(engine->user_interrupts); 3060 unsigned long irq_count = READ_ONCE(engine->breadcrumbs.irq_wakeups);
3085 3061
3086 if (engine->hangcheck.user_interrupts == user_interrupts && 3062 if (engine->hangcheck.user_interrupts == irq_count &&
3087 !test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) { 3063 !test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) {
3088 if (!(i915->gpu_error.test_irq_rings & intel_engine_flag(engine))) 3064 if (!test_bit(engine->id, &i915->gpu_error.test_irq_rings))
3089 DRM_ERROR("Hangcheck timer elapsed... %s idle\n", 3065 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3090 engine->name); 3066 engine->name);
3091 else 3067
3092 DRM_INFO("Fake missed irq on %s\n", 3068 intel_engine_enable_fake_irq(engine);
3093 engine->name);
3094 wake_up_all(&engine->irq_queue);
3095 } 3069 }
3096 3070
3097 return user_interrupts; 3071 return irq_count;
3098} 3072}
3099/* 3073/*
3100 * This is called when the chip hasn't reported back with completed 3074 * This is called when the chip hasn't reported back with completed
@@ -3110,9 +3084,8 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
3110 container_of(work, typeof(*dev_priv), 3084 container_of(work, typeof(*dev_priv),
3111 gpu_error.hangcheck_work.work); 3085 gpu_error.hangcheck_work.work);
3112 struct intel_engine_cs *engine; 3086 struct intel_engine_cs *engine;
3113 enum intel_engine_id id; 3087 unsigned int hung = 0, stuck = 0;
3114 int busy_count = 0, rings_hung = 0; 3088 int busy_count = 0;
3115 bool stuck[I915_NUM_ENGINES] = { 0 };
3116#define BUSY 1 3089#define BUSY 1
3117#define KICK 5 3090#define KICK 5
3118#define HUNG 20 3091#define HUNG 20
@@ -3121,12 +3094,8 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
3121 if (!i915.enable_hangcheck) 3094 if (!i915.enable_hangcheck)
3122 return; 3095 return;
3123 3096
3124 /* 3097 if (!READ_ONCE(dev_priv->gt.awake))
3125 * The hangcheck work is synced during runtime suspend, we don't 3098 return;
3126 * require a wakeref. TODO: instead of disabling the asserts make
3127 * sure that we hold a reference when this work is running.
3128 */
3129 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3130 3099
3131 /* As enabling the GPU requires fairly extensive mmio access, 3100 /* As enabling the GPU requires fairly extensive mmio access,
3132 * periodically arm the mmio checker to see if we are triggering 3101 * periodically arm the mmio checker to see if we are triggering
@@ -3134,11 +3103,11 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
3134 */ 3103 */
3135 intel_uncore_arm_unclaimed_mmio_detection(dev_priv); 3104 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3136 3105
3137 for_each_engine_id(engine, dev_priv, id) { 3106 for_each_engine(engine, dev_priv) {
3107 bool busy = intel_engine_has_waiter(engine);
3138 u64 acthd; 3108 u64 acthd;
3139 u32 seqno; 3109 u32 seqno;
3140 unsigned user_interrupts; 3110 unsigned user_interrupts;
3141 bool busy = true;
3142 3111
3143 semaphore_clear_deadlocks(dev_priv); 3112 semaphore_clear_deadlocks(dev_priv);
3144 3113
@@ -3153,7 +3122,7 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
3153 engine->irq_seqno_barrier(engine); 3122 engine->irq_seqno_barrier(engine);
3154 3123
3155 acthd = intel_ring_get_active_head(engine); 3124 acthd = intel_ring_get_active_head(engine);
3156 seqno = engine->get_seqno(engine); 3125 seqno = intel_engine_get_seqno(engine);
3157 3126
3158 /* Reset stuck interrupts between batch advances */ 3127 /* Reset stuck interrupts between batch advances */
3159 user_interrupts = 0; 3128 user_interrupts = 0;
@@ -3161,12 +3130,11 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
3161 if (engine->hangcheck.seqno == seqno) { 3130 if (engine->hangcheck.seqno == seqno) {
3162 if (ring_idle(engine, seqno)) { 3131 if (ring_idle(engine, seqno)) {
3163 engine->hangcheck.action = HANGCHECK_IDLE; 3132 engine->hangcheck.action = HANGCHECK_IDLE;
3164 if (waitqueue_active(&engine->irq_queue)) { 3133 if (busy) {
3165 /* Safeguard against driver failure */ 3134 /* Safeguard against driver failure */
3166 user_interrupts = kick_waiters(engine); 3135 user_interrupts = kick_waiters(engine);
3167 engine->hangcheck.score += BUSY; 3136 engine->hangcheck.score += BUSY;
3168 } else 3137 }
3169 busy = false;
3170 } else { 3138 } else {
3171 /* We always increment the hangcheck score 3139 /* We always increment the hangcheck score
3172 * if the ring is busy and still processing 3140 * if the ring is busy and still processing
@@ -3198,10 +3166,15 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
3198 break; 3166 break;
3199 case HANGCHECK_HUNG: 3167 case HANGCHECK_HUNG:
3200 engine->hangcheck.score += HUNG; 3168 engine->hangcheck.score += HUNG;
3201 stuck[id] = true;
3202 break; 3169 break;
3203 } 3170 }
3204 } 3171 }
3172
3173 if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3174 hung |= intel_engine_flag(engine);
3175 if (engine->hangcheck.action != HANGCHECK_HUNG)
3176 stuck |= intel_engine_flag(engine);
3177 }
3205 } else { 3178 } else {
3206 engine->hangcheck.action = HANGCHECK_ACTIVE; 3179 engine->hangcheck.action = HANGCHECK_ACTIVE;
3207 3180
@@ -3226,48 +3199,33 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
3226 busy_count += busy; 3199 busy_count += busy;
3227 } 3200 }
3228 3201
3229 for_each_engine_id(engine, dev_priv, id) { 3202 if (hung) {
3230 if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { 3203 char msg[80];
3231 DRM_INFO("%s on %s\n", 3204 int len;
3232 stuck[id] ? "stuck" : "no progress",
3233 engine->name);
3234 rings_hung |= intel_engine_flag(engine);
3235 }
3236 }
3237 3205
3238 if (rings_hung) { 3206 /* If some rings hung but others were still busy, only
3239 i915_handle_error(dev_priv, rings_hung, "Engine(s) hung"); 3207 * blame the hanging rings in the synopsis.
3240 goto out; 3208 */
3209 if (stuck != hung)
3210 hung &= ~stuck;
3211 len = scnprintf(msg, sizeof(msg),
3212 "%s on ", stuck == hung ? "No progress" : "Hang");
3213 for_each_engine_masked(engine, dev_priv, hung)
3214 len += scnprintf(msg + len, sizeof(msg) - len,
3215 "%s, ", engine->name);
3216 msg[len-2] = '\0';
3217
3218 return i915_handle_error(dev_priv, hung, msg);
3241 } 3219 }
3242 3220
3221 /* Reset timer in case GPU hangs without another request being added */
3243 if (busy_count) 3222 if (busy_count)
3244 /* Reset timer case chip hangs without another request
3245 * being added */
3246 i915_queue_hangcheck(dev_priv); 3223 i915_queue_hangcheck(dev_priv);
3247
3248out:
3249 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3250}
3251
3252void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3253{
3254 struct i915_gpu_error *e = &dev_priv->gpu_error;
3255
3256 if (!i915.enable_hangcheck)
3257 return;
3258
3259 /* Don't continually defer the hangcheck so that it is always run at
3260 * least once after work has been scheduled on any ring. Otherwise,
3261 * we will ignore a hung ring if a second ring is kept busy.
3262 */
3263
3264 queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3265 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
3266} 3224}
3267 3225
3268static void ibx_irq_reset(struct drm_device *dev) 3226static void ibx_irq_reset(struct drm_device *dev)
3269{ 3227{
3270 struct drm_i915_private *dev_priv = dev->dev_private; 3228 struct drm_i915_private *dev_priv = to_i915(dev);
3271 3229
3272 if (HAS_PCH_NOP(dev)) 3230 if (HAS_PCH_NOP(dev))
3273 return; 3231 return;
@@ -3288,7 +3246,7 @@ static void ibx_irq_reset(struct drm_device *dev)
3288 */ 3246 */
3289static void ibx_irq_pre_postinstall(struct drm_device *dev) 3247static void ibx_irq_pre_postinstall(struct drm_device *dev)
3290{ 3248{
3291 struct drm_i915_private *dev_priv = dev->dev_private; 3249 struct drm_i915_private *dev_priv = to_i915(dev);
3292 3250
3293 if (HAS_PCH_NOP(dev)) 3251 if (HAS_PCH_NOP(dev))
3294 return; 3252 return;
@@ -3300,7 +3258,7 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
3300 3258
3301static void gen5_gt_irq_reset(struct drm_device *dev) 3259static void gen5_gt_irq_reset(struct drm_device *dev)
3302{ 3260{
3303 struct drm_i915_private *dev_priv = dev->dev_private; 3261 struct drm_i915_private *dev_priv = to_i915(dev);
3304 3262
3305 GEN5_IRQ_RESET(GT); 3263 GEN5_IRQ_RESET(GT);
3306 if (INTEL_INFO(dev)->gen >= 6) 3264 if (INTEL_INFO(dev)->gen >= 6)
@@ -3360,7 +3318,7 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3360*/ 3318*/
3361static void ironlake_irq_reset(struct drm_device *dev) 3319static void ironlake_irq_reset(struct drm_device *dev)
3362{ 3320{
3363 struct drm_i915_private *dev_priv = dev->dev_private; 3321 struct drm_i915_private *dev_priv = to_i915(dev);
3364 3322
3365 I915_WRITE(HWSTAM, 0xffffffff); 3323 I915_WRITE(HWSTAM, 0xffffffff);
3366 3324
@@ -3375,7 +3333,7 @@ static void ironlake_irq_reset(struct drm_device *dev)
3375 3333
3376static void valleyview_irq_preinstall(struct drm_device *dev) 3334static void valleyview_irq_preinstall(struct drm_device *dev)
3377{ 3335{
3378 struct drm_i915_private *dev_priv = dev->dev_private; 3336 struct drm_i915_private *dev_priv = to_i915(dev);
3379 3337
3380 I915_WRITE(VLV_MASTER_IER, 0); 3338 I915_WRITE(VLV_MASTER_IER, 0);
3381 POSTING_READ(VLV_MASTER_IER); 3339 POSTING_READ(VLV_MASTER_IER);
@@ -3398,7 +3356,7 @@ static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3398 3356
3399static void gen8_irq_reset(struct drm_device *dev) 3357static void gen8_irq_reset(struct drm_device *dev)
3400{ 3358{
3401 struct drm_i915_private *dev_priv = dev->dev_private; 3359 struct drm_i915_private *dev_priv = to_i915(dev);
3402 int pipe; 3360 int pipe;
3403 3361
3404 I915_WRITE(GEN8_MASTER_IRQ, 0); 3362 I915_WRITE(GEN8_MASTER_IRQ, 0);
@@ -3444,12 +3402,12 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3444 spin_unlock_irq(&dev_priv->irq_lock); 3402 spin_unlock_irq(&dev_priv->irq_lock);
3445 3403
3446 /* make sure we're done processing display irqs */ 3404 /* make sure we're done processing display irqs */
3447 synchronize_irq(dev_priv->dev->irq); 3405 synchronize_irq(dev_priv->drm.irq);
3448} 3406}
3449 3407
3450static void cherryview_irq_preinstall(struct drm_device *dev) 3408static void cherryview_irq_preinstall(struct drm_device *dev)
3451{ 3409{
3452 struct drm_i915_private *dev_priv = dev->dev_private; 3410 struct drm_i915_private *dev_priv = to_i915(dev);
3453 3411
3454 I915_WRITE(GEN8_MASTER_IRQ, 0); 3412 I915_WRITE(GEN8_MASTER_IRQ, 0);
3455 POSTING_READ(GEN8_MASTER_IRQ); 3413 POSTING_READ(GEN8_MASTER_IRQ);
@@ -3470,7 +3428,7 @@ static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3470 struct intel_encoder *encoder; 3428 struct intel_encoder *encoder;
3471 u32 enabled_irqs = 0; 3429 u32 enabled_irqs = 0;
3472 3430
3473 for_each_intel_encoder(dev_priv->dev, encoder) 3431 for_each_intel_encoder(&dev_priv->drm, encoder)
3474 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) 3432 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3475 enabled_irqs |= hpd[encoder->hpd_pin]; 3433 enabled_irqs |= hpd[encoder->hpd_pin];
3476 3434
@@ -3601,7 +3559,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3601 3559
3602static void ibx_irq_postinstall(struct drm_device *dev) 3560static void ibx_irq_postinstall(struct drm_device *dev)
3603{ 3561{
3604 struct drm_i915_private *dev_priv = dev->dev_private; 3562 struct drm_i915_private *dev_priv = to_i915(dev);
3605 u32 mask; 3563 u32 mask;
3606 3564
3607 if (HAS_PCH_NOP(dev)) 3565 if (HAS_PCH_NOP(dev))
@@ -3618,7 +3576,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
3618 3576
3619static void gen5_gt_irq_postinstall(struct drm_device *dev) 3577static void gen5_gt_irq_postinstall(struct drm_device *dev)
3620{ 3578{
3621 struct drm_i915_private *dev_priv = dev->dev_private; 3579 struct drm_i915_private *dev_priv = to_i915(dev);
3622 u32 pm_irqs, gt_irqs; 3580 u32 pm_irqs, gt_irqs;
3623 3581
3624 pm_irqs = gt_irqs = 0; 3582 pm_irqs = gt_irqs = 0;
@@ -3632,8 +3590,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
3632 3590
3633 gt_irqs |= GT_RENDER_USER_INTERRUPT; 3591 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3634 if (IS_GEN5(dev)) { 3592 if (IS_GEN5(dev)) {
3635 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | 3593 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3636 ILK_BSD_USER_INTERRUPT;
3637 } else { 3594 } else {
3638 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; 3595 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3639 } 3596 }
@@ -3655,7 +3612,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
3655 3612
3656static int ironlake_irq_postinstall(struct drm_device *dev) 3613static int ironlake_irq_postinstall(struct drm_device *dev)
3657{ 3614{
3658 struct drm_i915_private *dev_priv = dev->dev_private; 3615 struct drm_i915_private *dev_priv = to_i915(dev);
3659 u32 display_mask, extra_mask; 3616 u32 display_mask, extra_mask;
3660 3617
3661 if (INTEL_INFO(dev)->gen >= 7) { 3618 if (INTEL_INFO(dev)->gen >= 7) {
@@ -3734,7 +3691,7 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3734 3691
3735static int valleyview_irq_postinstall(struct drm_device *dev) 3692static int valleyview_irq_postinstall(struct drm_device *dev)
3736{ 3693{
3737 struct drm_i915_private *dev_priv = dev->dev_private; 3694 struct drm_i915_private *dev_priv = to_i915(dev);
3738 3695
3739 gen5_gt_irq_postinstall(dev); 3696 gen5_gt_irq_postinstall(dev);
3740 3697
@@ -3827,7 +3784,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3827 3784
3828static int gen8_irq_postinstall(struct drm_device *dev) 3785static int gen8_irq_postinstall(struct drm_device *dev)
3829{ 3786{
3830 struct drm_i915_private *dev_priv = dev->dev_private; 3787 struct drm_i915_private *dev_priv = to_i915(dev);
3831 3788
3832 if (HAS_PCH_SPLIT(dev)) 3789 if (HAS_PCH_SPLIT(dev))
3833 ibx_irq_pre_postinstall(dev); 3790 ibx_irq_pre_postinstall(dev);
@@ -3846,7 +3803,7 @@ static int gen8_irq_postinstall(struct drm_device *dev)
3846 3803
3847static int cherryview_irq_postinstall(struct drm_device *dev) 3804static int cherryview_irq_postinstall(struct drm_device *dev)
3848{ 3805{
3849 struct drm_i915_private *dev_priv = dev->dev_private; 3806 struct drm_i915_private *dev_priv = to_i915(dev);
3850 3807
3851 gen8_gt_irq_postinstall(dev_priv); 3808 gen8_gt_irq_postinstall(dev_priv);
3852 3809
@@ -3863,7 +3820,7 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
3863 3820
3864static void gen8_irq_uninstall(struct drm_device *dev) 3821static void gen8_irq_uninstall(struct drm_device *dev)
3865{ 3822{
3866 struct drm_i915_private *dev_priv = dev->dev_private; 3823 struct drm_i915_private *dev_priv = to_i915(dev);
3867 3824
3868 if (!dev_priv) 3825 if (!dev_priv)
3869 return; 3826 return;
@@ -3873,7 +3830,7 @@ static void gen8_irq_uninstall(struct drm_device *dev)
3873 3830
3874static void valleyview_irq_uninstall(struct drm_device *dev) 3831static void valleyview_irq_uninstall(struct drm_device *dev)
3875{ 3832{
3876 struct drm_i915_private *dev_priv = dev->dev_private; 3833 struct drm_i915_private *dev_priv = to_i915(dev);
3877 3834
3878 if (!dev_priv) 3835 if (!dev_priv)
3879 return; 3836 return;
@@ -3893,7 +3850,7 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
3893 3850
3894static void cherryview_irq_uninstall(struct drm_device *dev) 3851static void cherryview_irq_uninstall(struct drm_device *dev)
3895{ 3852{
3896 struct drm_i915_private *dev_priv = dev->dev_private; 3853 struct drm_i915_private *dev_priv = to_i915(dev);
3897 3854
3898 if (!dev_priv) 3855 if (!dev_priv)
3899 return; 3856 return;
@@ -3913,7 +3870,7 @@ static void cherryview_irq_uninstall(struct drm_device *dev)
3913 3870
3914static void ironlake_irq_uninstall(struct drm_device *dev) 3871static void ironlake_irq_uninstall(struct drm_device *dev)
3915{ 3872{
3916 struct drm_i915_private *dev_priv = dev->dev_private; 3873 struct drm_i915_private *dev_priv = to_i915(dev);
3917 3874
3918 if (!dev_priv) 3875 if (!dev_priv)
3919 return; 3876 return;
@@ -3923,7 +3880,7 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
3923 3880
3924static void i8xx_irq_preinstall(struct drm_device * dev) 3881static void i8xx_irq_preinstall(struct drm_device * dev)
3925{ 3882{
3926 struct drm_i915_private *dev_priv = dev->dev_private; 3883 struct drm_i915_private *dev_priv = to_i915(dev);
3927 int pipe; 3884 int pipe;
3928 3885
3929 for_each_pipe(dev_priv, pipe) 3886 for_each_pipe(dev_priv, pipe)
@@ -3935,7 +3892,7 @@ static void i8xx_irq_preinstall(struct drm_device * dev)
3935 3892
3936static int i8xx_irq_postinstall(struct drm_device *dev) 3893static int i8xx_irq_postinstall(struct drm_device *dev)
3937{ 3894{
3938 struct drm_i915_private *dev_priv = dev->dev_private; 3895 struct drm_i915_private *dev_priv = to_i915(dev);
3939 3896
3940 I915_WRITE16(EMR, 3897 I915_WRITE16(EMR,
3941 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 3898 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
@@ -3998,7 +3955,7 @@ check_page_flip:
3998static irqreturn_t i8xx_irq_handler(int irq, void *arg) 3955static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3999{ 3956{
4000 struct drm_device *dev = arg; 3957 struct drm_device *dev = arg;
4001 struct drm_i915_private *dev_priv = dev->dev_private; 3958 struct drm_i915_private *dev_priv = to_i915(dev);
4002 u16 iir, new_iir; 3959 u16 iir, new_iir;
4003 u32 pipe_stats[2]; 3960 u32 pipe_stats[2];
4004 int pipe; 3961 int pipe;
@@ -4075,7 +4032,7 @@ out:
4075 4032
4076static void i8xx_irq_uninstall(struct drm_device * dev) 4033static void i8xx_irq_uninstall(struct drm_device * dev)
4077{ 4034{
4078 struct drm_i915_private *dev_priv = dev->dev_private; 4035 struct drm_i915_private *dev_priv = to_i915(dev);
4079 int pipe; 4036 int pipe;
4080 4037
4081 for_each_pipe(dev_priv, pipe) { 4038 for_each_pipe(dev_priv, pipe) {
@@ -4090,7 +4047,7 @@ static void i8xx_irq_uninstall(struct drm_device * dev)
4090 4047
4091static void i915_irq_preinstall(struct drm_device * dev) 4048static void i915_irq_preinstall(struct drm_device * dev)
4092{ 4049{
4093 struct drm_i915_private *dev_priv = dev->dev_private; 4050 struct drm_i915_private *dev_priv = to_i915(dev);
4094 int pipe; 4051 int pipe;
4095 4052
4096 if (I915_HAS_HOTPLUG(dev)) { 4053 if (I915_HAS_HOTPLUG(dev)) {
@@ -4108,7 +4065,7 @@ static void i915_irq_preinstall(struct drm_device * dev)
4108 4065
4109static int i915_irq_postinstall(struct drm_device *dev) 4066static int i915_irq_postinstall(struct drm_device *dev)
4110{ 4067{
4111 struct drm_i915_private *dev_priv = dev->dev_private; 4068 struct drm_i915_private *dev_priv = to_i915(dev);
4112 u32 enable_mask; 4069 u32 enable_mask;
4113 4070
4114 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 4071 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
@@ -4187,7 +4144,7 @@ check_page_flip:
4187static irqreturn_t i915_irq_handler(int irq, void *arg) 4144static irqreturn_t i915_irq_handler(int irq, void *arg)
4188{ 4145{
4189 struct drm_device *dev = arg; 4146 struct drm_device *dev = arg;
4190 struct drm_i915_private *dev_priv = dev->dev_private; 4147 struct drm_i915_private *dev_priv = to_i915(dev);
4191 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; 4148 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4192 u32 flip_mask = 4149 u32 flip_mask =
4193 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 4150 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
@@ -4292,7 +4249,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
4292 4249
4293static void i915_irq_uninstall(struct drm_device * dev) 4250static void i915_irq_uninstall(struct drm_device * dev)
4294{ 4251{
4295 struct drm_i915_private *dev_priv = dev->dev_private; 4252 struct drm_i915_private *dev_priv = to_i915(dev);
4296 int pipe; 4253 int pipe;
4297 4254
4298 if (I915_HAS_HOTPLUG(dev)) { 4255 if (I915_HAS_HOTPLUG(dev)) {
@@ -4314,7 +4271,7 @@ static void i915_irq_uninstall(struct drm_device * dev)
4314 4271
4315static void i965_irq_preinstall(struct drm_device * dev) 4272static void i965_irq_preinstall(struct drm_device * dev)
4316{ 4273{
4317 struct drm_i915_private *dev_priv = dev->dev_private; 4274 struct drm_i915_private *dev_priv = to_i915(dev);
4318 int pipe; 4275 int pipe;
4319 4276
4320 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); 4277 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
@@ -4330,7 +4287,7 @@ static void i965_irq_preinstall(struct drm_device * dev)
4330 4287
4331static int i965_irq_postinstall(struct drm_device *dev) 4288static int i965_irq_postinstall(struct drm_device *dev)
4332{ 4289{
4333 struct drm_i915_private *dev_priv = dev->dev_private; 4290 struct drm_i915_private *dev_priv = to_i915(dev);
4334 u32 enable_mask; 4291 u32 enable_mask;
4335 u32 error_mask; 4292 u32 error_mask;
4336 4293
@@ -4414,7 +4371,7 @@ static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4414static irqreturn_t i965_irq_handler(int irq, void *arg) 4371static irqreturn_t i965_irq_handler(int irq, void *arg)
4415{ 4372{
4416 struct drm_device *dev = arg; 4373 struct drm_device *dev = arg;
4417 struct drm_i915_private *dev_priv = dev->dev_private; 4374 struct drm_i915_private *dev_priv = to_i915(dev);
4418 u32 iir, new_iir; 4375 u32 iir, new_iir;
4419 u32 pipe_stats[I915_MAX_PIPES]; 4376 u32 pipe_stats[I915_MAX_PIPES];
4420 int ret = IRQ_NONE, pipe; 4377 int ret = IRQ_NONE, pipe;
@@ -4523,7 +4480,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
4523 4480
4524static void i965_irq_uninstall(struct drm_device * dev) 4481static void i965_irq_uninstall(struct drm_device * dev)
4525{ 4482{
4526 struct drm_i915_private *dev_priv = dev->dev_private; 4483 struct drm_i915_private *dev_priv = to_i915(dev);
4527 int pipe; 4484 int pipe;
4528 4485
4529 if (!dev_priv) 4486 if (!dev_priv)
@@ -4553,7 +4510,7 @@ static void i965_irq_uninstall(struct drm_device * dev)
4553 */ 4510 */
4554void intel_irq_init(struct drm_i915_private *dev_priv) 4511void intel_irq_init(struct drm_i915_private *dev_priv)
4555{ 4512{
4556 struct drm_device *dev = dev_priv->dev; 4513 struct drm_device *dev = &dev_priv->drm;
4557 4514
4558 intel_hpd_init_work(dev_priv); 4515 intel_hpd_init_work(dev_priv);
4559 4516
@@ -4631,7 +4588,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
4631 dev->driver->disable_vblank = gen8_disable_vblank; 4588 dev->driver->disable_vblank = gen8_disable_vblank;
4632 if (IS_BROXTON(dev)) 4589 if (IS_BROXTON(dev))
4633 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; 4590 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4634 else if (HAS_PCH_SPT(dev)) 4591 else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))
4635 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; 4592 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4636 else 4593 else
4637 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; 4594 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
@@ -4687,7 +4644,7 @@ int intel_irq_install(struct drm_i915_private *dev_priv)
4687 */ 4644 */
4688 dev_priv->pm.irqs_enabled = true; 4645 dev_priv->pm.irqs_enabled = true;
4689 4646
4690 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); 4647 return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4691} 4648}
4692 4649
4693/** 4650/**
@@ -4699,7 +4656,7 @@ int intel_irq_install(struct drm_i915_private *dev_priv)
4699 */ 4656 */
4700void intel_irq_uninstall(struct drm_i915_private *dev_priv) 4657void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4701{ 4658{
4702 drm_irq_uninstall(dev_priv->dev); 4659 drm_irq_uninstall(&dev_priv->drm);
4703 intel_hpd_cancel_work(dev_priv); 4660 intel_hpd_cancel_work(dev_priv);
4704 dev_priv->pm.irqs_enabled = false; 4661 dev_priv->pm.irqs_enabled = false;
4705} 4662}
@@ -4713,9 +4670,9 @@ void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4713 */ 4670 */
4714void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) 4671void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4715{ 4672{
4716 dev_priv->dev->driver->irq_uninstall(dev_priv->dev); 4673 dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4717 dev_priv->pm.irqs_enabled = false; 4674 dev_priv->pm.irqs_enabled = false;
4718 synchronize_irq(dev_priv->dev->irq); 4675 synchronize_irq(dev_priv->drm.irq);
4719} 4676}
4720 4677
4721/** 4678/**
@@ -4728,6 +4685,6 @@ void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4728void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) 4685void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4729{ 4686{
4730 dev_priv->pm.irqs_enabled = true; 4687 dev_priv->pm.irqs_enabled = true;
4731 dev_priv->dev->driver->irq_preinstall(dev_priv->dev); 4688 dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4732 dev_priv->dev->driver->irq_postinstall(dev_priv->dev); 4689 dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
4733} 4690}