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path: root/drivers/gpu/drm/i915/i915_irq.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c807
1 files changed, 367 insertions, 440 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index aab47f7bb61b..1c2aec392412 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -259,12 +259,12 @@ static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
259 dev_priv->gt_irq_mask &= ~interrupt_mask; 259 dev_priv->gt_irq_mask &= ~interrupt_mask;
260 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); 260 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
261 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 261 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
262 POSTING_READ(GTIMR);
263} 262}
264 263
265void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) 264void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
266{ 265{
267 ilk_update_gt_irq(dev_priv, mask, mask); 266 ilk_update_gt_irq(dev_priv, mask, mask);
267 POSTING_READ_FW(GTIMR);
268} 268}
269 269
270void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) 270void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
@@ -336,9 +336,8 @@ void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
336 __gen6_disable_pm_irq(dev_priv, mask); 336 __gen6_disable_pm_irq(dev_priv, mask);
337} 337}
338 338
339void gen6_reset_rps_interrupts(struct drm_device *dev) 339void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
340{ 340{
341 struct drm_i915_private *dev_priv = dev->dev_private;
342 i915_reg_t reg = gen6_pm_iir(dev_priv); 341 i915_reg_t reg = gen6_pm_iir(dev_priv);
343 342
344 spin_lock_irq(&dev_priv->irq_lock); 343 spin_lock_irq(&dev_priv->irq_lock);
@@ -349,14 +348,11 @@ void gen6_reset_rps_interrupts(struct drm_device *dev)
349 spin_unlock_irq(&dev_priv->irq_lock); 348 spin_unlock_irq(&dev_priv->irq_lock);
350} 349}
351 350
352void gen6_enable_rps_interrupts(struct drm_device *dev) 351void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
353{ 352{
354 struct drm_i915_private *dev_priv = dev->dev_private;
355
356 spin_lock_irq(&dev_priv->irq_lock); 353 spin_lock_irq(&dev_priv->irq_lock);
357 354 WARN_ON_ONCE(dev_priv->rps.pm_iir);
358 WARN_ON(dev_priv->rps.pm_iir); 355 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
359 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
360 dev_priv->rps.interrupts_enabled = true; 356 dev_priv->rps.interrupts_enabled = true;
361 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | 357 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
362 dev_priv->pm_rps_events); 358 dev_priv->pm_rps_events);
@@ -367,32 +363,13 @@ void gen6_enable_rps_interrupts(struct drm_device *dev)
367 363
368u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) 364u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
369{ 365{
370 /* 366 return (mask & ~dev_priv->rps.pm_intr_keep);
371 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
372 * if GEN6_PM_UP_EI_EXPIRED is masked.
373 *
374 * TODO: verify if this can be reproduced on VLV,CHV.
375 */
376 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
377 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
378
379 if (INTEL_INFO(dev_priv)->gen >= 8)
380 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
381
382 return mask;
383} 367}
384 368
385void gen6_disable_rps_interrupts(struct drm_device *dev) 369void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
386{ 370{
387 struct drm_i915_private *dev_priv = dev->dev_private;
388
389 spin_lock_irq(&dev_priv->irq_lock); 371 spin_lock_irq(&dev_priv->irq_lock);
390 dev_priv->rps.interrupts_enabled = false; 372 dev_priv->rps.interrupts_enabled = false;
391 spin_unlock_irq(&dev_priv->irq_lock);
392
393 cancel_work_sync(&dev_priv->rps.work);
394
395 spin_lock_irq(&dev_priv->irq_lock);
396 373
397 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0)); 374 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
398 375
@@ -401,8 +378,15 @@ void gen6_disable_rps_interrupts(struct drm_device *dev)
401 ~dev_priv->pm_rps_events); 378 ~dev_priv->pm_rps_events);
402 379
403 spin_unlock_irq(&dev_priv->irq_lock); 380 spin_unlock_irq(&dev_priv->irq_lock);
381 synchronize_irq(dev_priv->drm.irq);
404 382
405 synchronize_irq(dev->irq); 383 /* Now that we will not be generating any more work, flush any
384 * outsanding tasks. As we are called on the RPS idle path,
385 * we will reset the GPU to minimum frequencies, so the current
386 * state of the worker can be discarded.
387 */
388 cancel_work_sync(&dev_priv->rps.work);
389 gen6_reset_rps_interrupts(dev_priv);
406} 390}
407 391
408/** 392/**
@@ -582,7 +566,7 @@ i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
582 u32 enable_mask; 566 u32 enable_mask;
583 567
584 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 568 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
585 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, 569 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
586 status_mask); 570 status_mask);
587 else 571 else
588 enable_mask = status_mask << 16; 572 enable_mask = status_mask << 16;
@@ -596,7 +580,7 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
596 u32 enable_mask; 580 u32 enable_mask;
597 581
598 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 582 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
599 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, 583 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
600 status_mask); 584 status_mask);
601 else 585 else
602 enable_mask = status_mask << 16; 586 enable_mask = status_mask << 16;
@@ -605,19 +589,17 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
605 589
606/** 590/**
607 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion 591 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
608 * @dev: drm device 592 * @dev_priv: i915 device private
609 */ 593 */
610static void i915_enable_asle_pipestat(struct drm_device *dev) 594static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
611{ 595{
612 struct drm_i915_private *dev_priv = dev->dev_private; 596 if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
613
614 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
615 return; 597 return;
616 598
617 spin_lock_irq(&dev_priv->irq_lock); 599 spin_lock_irq(&dev_priv->irq_lock);
618 600
619 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); 601 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
620 if (INTEL_INFO(dev)->gen >= 4) 602 if (INTEL_GEN(dev_priv) >= 4)
621 i915_enable_pipestat(dev_priv, PIPE_A, 603 i915_enable_pipestat(dev_priv, PIPE_A,
622 PIPE_LEGACY_BLC_EVENT_STATUS); 604 PIPE_LEGACY_BLC_EVENT_STATUS);
623 605
@@ -685,7 +667,7 @@ static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
685 */ 667 */
686static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe) 668static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
687{ 669{
688 struct drm_i915_private *dev_priv = dev->dev_private; 670 struct drm_i915_private *dev_priv = to_i915(dev);
689 i915_reg_t high_frame, low_frame; 671 i915_reg_t high_frame, low_frame;
690 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; 672 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
691 struct intel_crtc *intel_crtc = 673 struct intel_crtc *intel_crtc =
@@ -732,7 +714,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
732 714
733static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe) 715static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
734{ 716{
735 struct drm_i915_private *dev_priv = dev->dev_private; 717 struct drm_i915_private *dev_priv = to_i915(dev);
736 718
737 return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); 719 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
738} 720}
@@ -741,7 +723,7 @@ static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
741static int __intel_get_crtc_scanline(struct intel_crtc *crtc) 723static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
742{ 724{
743 struct drm_device *dev = crtc->base.dev; 725 struct drm_device *dev = crtc->base.dev;
744 struct drm_i915_private *dev_priv = dev->dev_private; 726 struct drm_i915_private *dev_priv = to_i915(dev);
745 const struct drm_display_mode *mode = &crtc->base.hwmode; 727 const struct drm_display_mode *mode = &crtc->base.hwmode;
746 enum pipe pipe = crtc->pipe; 728 enum pipe pipe = crtc->pipe;
747 int position, vtotal; 729 int position, vtotal;
@@ -750,7 +732,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
750 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 732 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
751 vtotal /= 2; 733 vtotal /= 2;
752 734
753 if (IS_GEN2(dev)) 735 if (IS_GEN2(dev_priv))
754 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; 736 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
755 else 737 else
756 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; 738 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
@@ -767,7 +749,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
767 * problem. We may need to extend this to include other platforms, 749 * problem. We may need to extend this to include other platforms,
768 * but so far testing only shows the problem on HSW. 750 * but so far testing only shows the problem on HSW.
769 */ 751 */
770 if (HAS_DDI(dev) && !position) { 752 if (HAS_DDI(dev_priv) && !position) {
771 int i, temp; 753 int i, temp;
772 754
773 for (i = 0; i < 100; i++) { 755 for (i = 0; i < 100; i++) {
@@ -793,7 +775,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
793 ktime_t *stime, ktime_t *etime, 775 ktime_t *stime, ktime_t *etime,
794 const struct drm_display_mode *mode) 776 const struct drm_display_mode *mode)
795{ 777{
796 struct drm_i915_private *dev_priv = dev->dev_private; 778 struct drm_i915_private *dev_priv = to_i915(dev);
797 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 779 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
799 int position; 781 int position;
@@ -835,7 +817,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
835 if (stime) 817 if (stime)
836 *stime = ktime_get(); 818 *stime = ktime_get();
837 819
838 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 820 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
839 /* No obvious pixelcount register. Only query vertical 821 /* No obvious pixelcount register. Only query vertical
840 * scanout position from Display scan line register. 822 * scanout position from Display scan line register.
841 */ 823 */
@@ -897,7 +879,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
897 else 879 else
898 position += vtotal - vbl_end; 880 position += vtotal - vbl_end;
899 881
900 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 882 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
901 *vpos = position; 883 *vpos = position;
902 *hpos = 0; 884 *hpos = 0;
903 } else { 885 } else {
@@ -914,7 +896,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
914 896
915int intel_get_crtc_scanline(struct intel_crtc *crtc) 897int intel_get_crtc_scanline(struct intel_crtc *crtc)
916{ 898{
917 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 899 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
918 unsigned long irqflags; 900 unsigned long irqflags;
919 int position; 901 int position;
920 902
@@ -955,9 +937,8 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
955 &crtc->hwmode); 937 &crtc->hwmode);
956} 938}
957 939
958static void ironlake_rps_change_irq_handler(struct drm_device *dev) 940static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
959{ 941{
960 struct drm_i915_private *dev_priv = dev->dev_private;
961 u32 busy_up, busy_down, max_avg, min_avg; 942 u32 busy_up, busy_down, max_avg, min_avg;
962 u8 new_delay; 943 u8 new_delay;
963 944
@@ -986,7 +967,7 @@ static void ironlake_rps_change_irq_handler(struct drm_device *dev)
986 new_delay = dev_priv->ips.min_delay; 967 new_delay = dev_priv->ips.min_delay;
987 } 968 }
988 969
989 if (ironlake_set_drps(dev, new_delay)) 970 if (ironlake_set_drps(dev_priv, new_delay))
990 dev_priv->ips.cur_delay = new_delay; 971 dev_priv->ips.cur_delay = new_delay;
991 972
992 spin_unlock(&mchdev_lock); 973 spin_unlock(&mchdev_lock);
@@ -996,13 +977,11 @@ static void ironlake_rps_change_irq_handler(struct drm_device *dev)
996 977
997static void notify_ring(struct intel_engine_cs *engine) 978static void notify_ring(struct intel_engine_cs *engine)
998{ 979{
999 if (!intel_engine_initialized(engine)) 980 smp_store_mb(engine->breadcrumbs.irq_posted, true);
1000 return; 981 if (intel_engine_wakeup(engine)) {
1001 982 trace_i915_gem_request_notify(engine);
1002 trace_i915_gem_request_notify(engine); 983 engine->breadcrumbs.irq_wakeups++;
1003 engine->user_interrupts++; 984 }
1004
1005 wake_up_all(&engine->irq_queue);
1006} 985}
1007 986
1008static void vlv_c0_read(struct drm_i915_private *dev_priv, 987static void vlv_c0_read(struct drm_i915_private *dev_priv,
@@ -1083,7 +1062,7 @@ static bool any_waiters(struct drm_i915_private *dev_priv)
1083 struct intel_engine_cs *engine; 1062 struct intel_engine_cs *engine;
1084 1063
1085 for_each_engine(engine, dev_priv) 1064 for_each_engine(engine, dev_priv)
1086 if (engine->irq_refcount) 1065 if (intel_engine_has_waiter(engine))
1087 return true; 1066 return true;
1088 1067
1089 return false; 1068 return false;
@@ -1104,13 +1083,6 @@ static void gen6_pm_rps_work(struct work_struct *work)
1104 return; 1083 return;
1105 } 1084 }
1106 1085
1107 /*
1108 * The RPS work is synced during runtime suspend, we don't require a
1109 * wakeref. TODO: instead of disabling the asserts make sure that we
1110 * always hold an RPM reference while the work is running.
1111 */
1112 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1113
1114 pm_iir = dev_priv->rps.pm_iir; 1086 pm_iir = dev_priv->rps.pm_iir;
1115 dev_priv->rps.pm_iir = 0; 1087 dev_priv->rps.pm_iir = 0;
1116 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ 1088 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
@@ -1123,7 +1095,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
1123 WARN_ON(pm_iir & ~dev_priv->pm_rps_events); 1095 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1124 1096
1125 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) 1097 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1126 goto out; 1098 return;
1127 1099
1128 mutex_lock(&dev_priv->rps.hw_lock); 1100 mutex_lock(&dev_priv->rps.hw_lock);
1129 1101
@@ -1175,11 +1147,9 @@ static void gen6_pm_rps_work(struct work_struct *work)
1175 new_delay += adj; 1147 new_delay += adj;
1176 new_delay = clamp_t(int, new_delay, min, max); 1148 new_delay = clamp_t(int, new_delay, min, max);
1177 1149
1178 intel_set_rps(dev_priv->dev, new_delay); 1150 intel_set_rps(dev_priv, new_delay);
1179 1151
1180 mutex_unlock(&dev_priv->rps.hw_lock); 1152 mutex_unlock(&dev_priv->rps.hw_lock);
1181out:
1182 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1183} 1153}
1184 1154
1185 1155
@@ -1205,7 +1175,7 @@ static void ivybridge_parity_work(struct work_struct *work)
1205 * In order to prevent a get/put style interface, acquire struct mutex 1175 * In order to prevent a get/put style interface, acquire struct mutex
1206 * any time we access those registers. 1176 * any time we access those registers.
1207 */ 1177 */
1208 mutex_lock(&dev_priv->dev->struct_mutex); 1178 mutex_lock(&dev_priv->drm.struct_mutex);
1209 1179
1210 /* If we've screwed up tracking, just let the interrupt fire again */ 1180 /* If we've screwed up tracking, just let the interrupt fire again */
1211 if (WARN_ON(!dev_priv->l3_parity.which_slice)) 1181 if (WARN_ON(!dev_priv->l3_parity.which_slice))
@@ -1241,7 +1211,7 @@ static void ivybridge_parity_work(struct work_struct *work)
1241 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); 1211 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1242 parity_event[5] = NULL; 1212 parity_event[5] = NULL;
1243 1213
1244 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, 1214 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1245 KOBJ_CHANGE, parity_event); 1215 KOBJ_CHANGE, parity_event);
1246 1216
1247 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", 1217 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
@@ -1261,7 +1231,7 @@ out:
1261 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); 1231 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1262 spin_unlock_irq(&dev_priv->irq_lock); 1232 spin_unlock_irq(&dev_priv->irq_lock);
1263 1233
1264 mutex_unlock(&dev_priv->dev->struct_mutex); 1234 mutex_unlock(&dev_priv->drm.struct_mutex);
1265} 1235}
1266 1236
1267static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv, 1237static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
@@ -1287,8 +1257,7 @@ static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv
1287static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv, 1257static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1288 u32 gt_iir) 1258 u32 gt_iir)
1289{ 1259{
1290 if (gt_iir & 1260 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1291 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1292 notify_ring(&dev_priv->engine[RCS]); 1261 notify_ring(&dev_priv->engine[RCS]);
1293 if (gt_iir & ILK_BSD_USER_INTERRUPT) 1262 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1294 notify_ring(&dev_priv->engine[VCS]); 1263 notify_ring(&dev_priv->engine[VCS]);
@@ -1297,9 +1266,7 @@ static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1297static void snb_gt_irq_handler(struct drm_i915_private *dev_priv, 1266static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1298 u32 gt_iir) 1267 u32 gt_iir)
1299{ 1268{
1300 1269 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1301 if (gt_iir &
1302 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1303 notify_ring(&dev_priv->engine[RCS]); 1270 notify_ring(&dev_priv->engine[RCS]);
1304 if (gt_iir & GT_BSD_USER_INTERRUPT) 1271 if (gt_iir & GT_BSD_USER_INTERRUPT)
1305 notify_ring(&dev_priv->engine[VCS]); 1272 notify_ring(&dev_priv->engine[VCS]);
@@ -1506,27 +1473,23 @@ static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1506 1473
1507} 1474}
1508 1475
1509static void gmbus_irq_handler(struct drm_device *dev) 1476static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1510{ 1477{
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512
1513 wake_up_all(&dev_priv->gmbus_wait_queue); 1478 wake_up_all(&dev_priv->gmbus_wait_queue);
1514} 1479}
1515 1480
1516static void dp_aux_irq_handler(struct drm_device *dev) 1481static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1517{ 1482{
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519
1520 wake_up_all(&dev_priv->gmbus_wait_queue); 1483 wake_up_all(&dev_priv->gmbus_wait_queue);
1521} 1484}
1522 1485
1523#if defined(CONFIG_DEBUG_FS) 1486#if defined(CONFIG_DEBUG_FS)
1524static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, 1487static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1488 enum pipe pipe,
1525 uint32_t crc0, uint32_t crc1, 1489 uint32_t crc0, uint32_t crc1,
1526 uint32_t crc2, uint32_t crc3, 1490 uint32_t crc2, uint32_t crc3,
1527 uint32_t crc4) 1491 uint32_t crc4)
1528{ 1492{
1529 struct drm_i915_private *dev_priv = dev->dev_private;
1530 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 1493 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1531 struct intel_pipe_crc_entry *entry; 1494 struct intel_pipe_crc_entry *entry;
1532 int head, tail; 1495 int head, tail;
@@ -1550,7 +1513,8 @@ static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1550 1513
1551 entry = &pipe_crc->entries[head]; 1514 entry = &pipe_crc->entries[head];
1552 1515
1553 entry->frame = dev->driver->get_vblank_counter(dev, pipe); 1516 entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm,
1517 pipe);
1554 entry->crc[0] = crc0; 1518 entry->crc[0] = crc0;
1555 entry->crc[1] = crc1; 1519 entry->crc[1] = crc1;
1556 entry->crc[2] = crc2; 1520 entry->crc[2] = crc2;
@@ -1566,27 +1530,26 @@ static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1566} 1530}
1567#else 1531#else
1568static inline void 1532static inline void
1569display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, 1533display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1534 enum pipe pipe,
1570 uint32_t crc0, uint32_t crc1, 1535 uint32_t crc0, uint32_t crc1,
1571 uint32_t crc2, uint32_t crc3, 1536 uint32_t crc2, uint32_t crc3,
1572 uint32_t crc4) {} 1537 uint32_t crc4) {}
1573#endif 1538#endif
1574 1539
1575 1540
1576static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) 1541static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1542 enum pipe pipe)
1577{ 1543{
1578 struct drm_i915_private *dev_priv = dev->dev_private; 1544 display_pipe_crc_irq_handler(dev_priv, pipe,
1579
1580 display_pipe_crc_irq_handler(dev, pipe,
1581 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), 1545 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1582 0, 0, 0, 0); 1546 0, 0, 0, 0);
1583} 1547}
1584 1548
1585static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) 1549static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1550 enum pipe pipe)
1586{ 1551{
1587 struct drm_i915_private *dev_priv = dev->dev_private; 1552 display_pipe_crc_irq_handler(dev_priv, pipe,
1588
1589 display_pipe_crc_irq_handler(dev, pipe,
1590 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), 1553 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1591 I915_READ(PIPE_CRC_RES_2_IVB(pipe)), 1554 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1592 I915_READ(PIPE_CRC_RES_3_IVB(pipe)), 1555 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
@@ -1594,22 +1557,22 @@ static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1594 I915_READ(PIPE_CRC_RES_5_IVB(pipe))); 1557 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1595} 1558}
1596 1559
1597static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) 1560static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1561 enum pipe pipe)
1598{ 1562{
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600 uint32_t res1, res2; 1563 uint32_t res1, res2;
1601 1564
1602 if (INTEL_INFO(dev)->gen >= 3) 1565 if (INTEL_GEN(dev_priv) >= 3)
1603 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); 1566 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1604 else 1567 else
1605 res1 = 0; 1568 res1 = 0;
1606 1569
1607 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) 1570 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1608 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); 1571 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1609 else 1572 else
1610 res2 = 0; 1573 res2 = 0;
1611 1574
1612 display_pipe_crc_irq_handler(dev, pipe, 1575 display_pipe_crc_irq_handler(dev_priv, pipe,
1613 I915_READ(PIPE_CRC_RES_RED(pipe)), 1576 I915_READ(PIPE_CRC_RES_RED(pipe)),
1614 I915_READ(PIPE_CRC_RES_GREEN(pipe)), 1577 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1615 I915_READ(PIPE_CRC_RES_BLUE(pipe)), 1578 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
@@ -1626,7 +1589,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1626 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); 1589 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1627 if (dev_priv->rps.interrupts_enabled) { 1590 if (dev_priv->rps.interrupts_enabled) {
1628 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; 1591 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1629 queue_work(dev_priv->wq, &dev_priv->rps.work); 1592 schedule_work(&dev_priv->rps.work);
1630 } 1593 }
1631 spin_unlock(&dev_priv->irq_lock); 1594 spin_unlock(&dev_priv->irq_lock);
1632 } 1595 }
@@ -1643,18 +1606,21 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1643 } 1606 }
1644} 1607}
1645 1608
1646static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) 1609static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1610 enum pipe pipe)
1647{ 1611{
1648 if (!drm_handle_vblank(dev, pipe)) 1612 bool ret;
1649 return false;
1650 1613
1651 return true; 1614 ret = drm_handle_vblank(&dev_priv->drm, pipe);
1615 if (ret)
1616 intel_finish_page_flip_mmio(dev_priv, pipe);
1617
1618 return ret;
1652} 1619}
1653 1620
1654static void valleyview_pipestat_irq_ack(struct drm_device *dev, u32 iir, 1621static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1655 u32 pipe_stats[I915_MAX_PIPES]) 1622 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1656{ 1623{
1657 struct drm_i915_private *dev_priv = dev->dev_private;
1658 int pipe; 1624 int pipe;
1659 1625
1660 spin_lock(&dev_priv->irq_lock); 1626 spin_lock(&dev_priv->irq_lock);
@@ -1710,31 +1676,28 @@ static void valleyview_pipestat_irq_ack(struct drm_device *dev, u32 iir,
1710 spin_unlock(&dev_priv->irq_lock); 1676 spin_unlock(&dev_priv->irq_lock);
1711} 1677}
1712 1678
1713static void valleyview_pipestat_irq_handler(struct drm_device *dev, 1679static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1714 u32 pipe_stats[I915_MAX_PIPES]) 1680 u32 pipe_stats[I915_MAX_PIPES])
1715{ 1681{
1716 struct drm_i915_private *dev_priv = to_i915(dev);
1717 enum pipe pipe; 1682 enum pipe pipe;
1718 1683
1719 for_each_pipe(dev_priv, pipe) { 1684 for_each_pipe(dev_priv, pipe) {
1720 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && 1685 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1721 intel_pipe_handle_vblank(dev, pipe)) 1686 intel_pipe_handle_vblank(dev_priv, pipe))
1722 intel_check_page_flip(dev, pipe); 1687 intel_check_page_flip(dev_priv, pipe);
1723 1688
1724 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { 1689 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1725 intel_prepare_page_flip(dev, pipe); 1690 intel_finish_page_flip_cs(dev_priv, pipe);
1726 intel_finish_page_flip(dev, pipe);
1727 }
1728 1691
1729 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 1692 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1730 i9xx_pipe_crc_irq_handler(dev, pipe); 1693 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1731 1694
1732 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 1695 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1733 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 1696 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1734 } 1697 }
1735 1698
1736 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 1699 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1737 gmbus_irq_handler(dev); 1700 gmbus_irq_handler(dev_priv);
1738} 1701}
1739 1702
1740static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) 1703static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
@@ -1747,12 +1710,13 @@ static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1747 return hotplug_status; 1710 return hotplug_status;
1748} 1711}
1749 1712
1750static void i9xx_hpd_irq_handler(struct drm_device *dev, 1713static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1751 u32 hotplug_status) 1714 u32 hotplug_status)
1752{ 1715{
1753 u32 pin_mask = 0, long_mask = 0; 1716 u32 pin_mask = 0, long_mask = 0;
1754 1717
1755 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 1718 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1719 IS_CHERRYVIEW(dev_priv)) {
1756 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; 1720 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1757 1721
1758 if (hotplug_trigger) { 1722 if (hotplug_trigger) {
@@ -1760,11 +1724,11 @@ static void i9xx_hpd_irq_handler(struct drm_device *dev,
1760 hotplug_trigger, hpd_status_g4x, 1724 hotplug_trigger, hpd_status_g4x,
1761 i9xx_port_hotplug_long_detect); 1725 i9xx_port_hotplug_long_detect);
1762 1726
1763 intel_hpd_irq_handler(dev, pin_mask, long_mask); 1727 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1764 } 1728 }
1765 1729
1766 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) 1730 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1767 dp_aux_irq_handler(dev); 1731 dp_aux_irq_handler(dev_priv);
1768 } else { 1732 } else {
1769 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; 1733 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1770 1734
@@ -1772,7 +1736,7 @@ static void i9xx_hpd_irq_handler(struct drm_device *dev,
1772 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, 1736 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1773 hotplug_trigger, hpd_status_i915, 1737 hotplug_trigger, hpd_status_i915,
1774 i9xx_port_hotplug_long_detect); 1738 i9xx_port_hotplug_long_detect);
1775 intel_hpd_irq_handler(dev, pin_mask, long_mask); 1739 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1776 } 1740 }
1777 } 1741 }
1778} 1742}
@@ -1780,7 +1744,7 @@ static void i9xx_hpd_irq_handler(struct drm_device *dev,
1780static irqreturn_t valleyview_irq_handler(int irq, void *arg) 1744static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1781{ 1745{
1782 struct drm_device *dev = arg; 1746 struct drm_device *dev = arg;
1783 struct drm_i915_private *dev_priv = dev->dev_private; 1747 struct drm_i915_private *dev_priv = to_i915(dev);
1784 irqreturn_t ret = IRQ_NONE; 1748 irqreturn_t ret = IRQ_NONE;
1785 1749
1786 if (!intel_irqs_enabled(dev_priv)) 1750 if (!intel_irqs_enabled(dev_priv))
@@ -1831,7 +1795,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1831 1795
1832 /* Call regardless, as some status bits might not be 1796 /* Call regardless, as some status bits might not be
1833 * signalled in iir */ 1797 * signalled in iir */
1834 valleyview_pipestat_irq_ack(dev, iir, pipe_stats); 1798 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1835 1799
1836 /* 1800 /*
1837 * VLV_IIR is single buffered, and reflects the level 1801 * VLV_IIR is single buffered, and reflects the level
@@ -1850,9 +1814,9 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1850 gen6_rps_irq_handler(dev_priv, pm_iir); 1814 gen6_rps_irq_handler(dev_priv, pm_iir);
1851 1815
1852 if (hotplug_status) 1816 if (hotplug_status)
1853 i9xx_hpd_irq_handler(dev, hotplug_status); 1817 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1854 1818
1855 valleyview_pipestat_irq_handler(dev, pipe_stats); 1819 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1856 } while (0); 1820 } while (0);
1857 1821
1858 enable_rpm_wakeref_asserts(dev_priv); 1822 enable_rpm_wakeref_asserts(dev_priv);
@@ -1863,7 +1827,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1863static irqreturn_t cherryview_irq_handler(int irq, void *arg) 1827static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1864{ 1828{
1865 struct drm_device *dev = arg; 1829 struct drm_device *dev = arg;
1866 struct drm_i915_private *dev_priv = dev->dev_private; 1830 struct drm_i915_private *dev_priv = to_i915(dev);
1867 irqreturn_t ret = IRQ_NONE; 1831 irqreturn_t ret = IRQ_NONE;
1868 1832
1869 if (!intel_irqs_enabled(dev_priv)) 1833 if (!intel_irqs_enabled(dev_priv))
@@ -1911,7 +1875,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1911 1875
1912 /* Call regardless, as some status bits might not be 1876 /* Call regardless, as some status bits might not be
1913 * signalled in iir */ 1877 * signalled in iir */
1914 valleyview_pipestat_irq_ack(dev, iir, pipe_stats); 1878 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1915 1879
1916 /* 1880 /*
1917 * VLV_IIR is single buffered, and reflects the level 1881 * VLV_IIR is single buffered, and reflects the level
@@ -1927,9 +1891,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1927 gen8_gt_irq_handler(dev_priv, gt_iir); 1891 gen8_gt_irq_handler(dev_priv, gt_iir);
1928 1892
1929 if (hotplug_status) 1893 if (hotplug_status)
1930 i9xx_hpd_irq_handler(dev, hotplug_status); 1894 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1931 1895
1932 valleyview_pipestat_irq_handler(dev, pipe_stats); 1896 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1933 } while (0); 1897 } while (0);
1934 1898
1935 enable_rpm_wakeref_asserts(dev_priv); 1899 enable_rpm_wakeref_asserts(dev_priv);
@@ -1937,10 +1901,10 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1937 return ret; 1901 return ret;
1938} 1902}
1939 1903
1940static void ibx_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger, 1904static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1905 u32 hotplug_trigger,
1941 const u32 hpd[HPD_NUM_PINS]) 1906 const u32 hpd[HPD_NUM_PINS])
1942{ 1907{
1943 struct drm_i915_private *dev_priv = to_i915(dev);
1944 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 1908 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1945 1909
1946 /* 1910 /*
@@ -1966,16 +1930,15 @@ static void ibx_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
1966 dig_hotplug_reg, hpd, 1930 dig_hotplug_reg, hpd,
1967 pch_port_hotplug_long_detect); 1931 pch_port_hotplug_long_detect);
1968 1932
1969 intel_hpd_irq_handler(dev, pin_mask, long_mask); 1933 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1970} 1934}
1971 1935
1972static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) 1936static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1973{ 1937{
1974 struct drm_i915_private *dev_priv = dev->dev_private;
1975 int pipe; 1938 int pipe;
1976 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; 1939 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1977 1940
1978 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); 1941 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
1979 1942
1980 if (pch_iir & SDE_AUDIO_POWER_MASK) { 1943 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1981 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> 1944 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
@@ -1985,10 +1948,10 @@ static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1985 } 1948 }
1986 1949
1987 if (pch_iir & SDE_AUX_MASK) 1950 if (pch_iir & SDE_AUX_MASK)
1988 dp_aux_irq_handler(dev); 1951 dp_aux_irq_handler(dev_priv);
1989 1952
1990 if (pch_iir & SDE_GMBUS) 1953 if (pch_iir & SDE_GMBUS)
1991 gmbus_irq_handler(dev); 1954 gmbus_irq_handler(dev_priv);
1992 1955
1993 if (pch_iir & SDE_AUDIO_HDCP_MASK) 1956 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1994 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); 1957 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
@@ -2018,9 +1981,8 @@ static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
2018 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); 1981 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2019} 1982}
2020 1983
2021static void ivb_err_int_handler(struct drm_device *dev) 1984static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2022{ 1985{
2023 struct drm_i915_private *dev_priv = dev->dev_private;
2024 u32 err_int = I915_READ(GEN7_ERR_INT); 1986 u32 err_int = I915_READ(GEN7_ERR_INT);
2025 enum pipe pipe; 1987 enum pipe pipe;
2026 1988
@@ -2032,19 +1994,18 @@ static void ivb_err_int_handler(struct drm_device *dev)
2032 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 1994 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2033 1995
2034 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { 1996 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2035 if (IS_IVYBRIDGE(dev)) 1997 if (IS_IVYBRIDGE(dev_priv))
2036 ivb_pipe_crc_irq_handler(dev, pipe); 1998 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2037 else 1999 else
2038 hsw_pipe_crc_irq_handler(dev, pipe); 2000 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2039 } 2001 }
2040 } 2002 }
2041 2003
2042 I915_WRITE(GEN7_ERR_INT, err_int); 2004 I915_WRITE(GEN7_ERR_INT, err_int);
2043} 2005}
2044 2006
2045static void cpt_serr_int_handler(struct drm_device *dev) 2007static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2046{ 2008{
2047 struct drm_i915_private *dev_priv = dev->dev_private;
2048 u32 serr_int = I915_READ(SERR_INT); 2009 u32 serr_int = I915_READ(SERR_INT);
2049 2010
2050 if (serr_int & SERR_INT_POISON) 2011 if (serr_int & SERR_INT_POISON)
@@ -2062,13 +2023,12 @@ static void cpt_serr_int_handler(struct drm_device *dev)
2062 I915_WRITE(SERR_INT, serr_int); 2023 I915_WRITE(SERR_INT, serr_int);
2063} 2024}
2064 2025
2065static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) 2026static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2066{ 2027{
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 int pipe; 2028 int pipe;
2069 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; 2029 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2070 2030
2071 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); 2031 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2072 2032
2073 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { 2033 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2074 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> 2034 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
@@ -2078,10 +2038,10 @@ static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2078 } 2038 }
2079 2039
2080 if (pch_iir & SDE_AUX_MASK_CPT) 2040 if (pch_iir & SDE_AUX_MASK_CPT)
2081 dp_aux_irq_handler(dev); 2041 dp_aux_irq_handler(dev_priv);
2082 2042
2083 if (pch_iir & SDE_GMBUS_CPT) 2043 if (pch_iir & SDE_GMBUS_CPT)
2084 gmbus_irq_handler(dev); 2044 gmbus_irq_handler(dev_priv);
2085 2045
2086 if (pch_iir & SDE_AUDIO_CP_REQ_CPT) 2046 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2087 DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); 2047 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
@@ -2096,12 +2056,11 @@ static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2096 I915_READ(FDI_RX_IIR(pipe))); 2056 I915_READ(FDI_RX_IIR(pipe)));
2097 2057
2098 if (pch_iir & SDE_ERROR_CPT) 2058 if (pch_iir & SDE_ERROR_CPT)
2099 cpt_serr_int_handler(dev); 2059 cpt_serr_int_handler(dev_priv);
2100} 2060}
2101 2061
2102static void spt_irq_handler(struct drm_device *dev, u32 pch_iir) 2062static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2103{ 2063{
2104 struct drm_i915_private *dev_priv = dev->dev_private;
2105 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & 2064 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2106 ~SDE_PORTE_HOTPLUG_SPT; 2065 ~SDE_PORTE_HOTPLUG_SPT;
2107 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; 2066 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
@@ -2130,16 +2089,16 @@ static void spt_irq_handler(struct drm_device *dev, u32 pch_iir)
2130 } 2089 }
2131 2090
2132 if (pin_mask) 2091 if (pin_mask)
2133 intel_hpd_irq_handler(dev, pin_mask, long_mask); 2092 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2134 2093
2135 if (pch_iir & SDE_GMBUS_CPT) 2094 if (pch_iir & SDE_GMBUS_CPT)
2136 gmbus_irq_handler(dev); 2095 gmbus_irq_handler(dev_priv);
2137} 2096}
2138 2097
2139static void ilk_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger, 2098static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2099 u32 hotplug_trigger,
2140 const u32 hpd[HPD_NUM_PINS]) 2100 const u32 hpd[HPD_NUM_PINS])
2141{ 2101{
2142 struct drm_i915_private *dev_priv = to_i915(dev);
2143 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 2102 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2144 2103
2145 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); 2104 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
@@ -2149,97 +2108,93 @@ static void ilk_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
2149 dig_hotplug_reg, hpd, 2108 dig_hotplug_reg, hpd,
2150 ilk_port_hotplug_long_detect); 2109 ilk_port_hotplug_long_detect);
2151 2110
2152 intel_hpd_irq_handler(dev, pin_mask, long_mask); 2111 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2153} 2112}
2154 2113
2155static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) 2114static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2115 u32 de_iir)
2156{ 2116{
2157 struct drm_i915_private *dev_priv = dev->dev_private;
2158 enum pipe pipe; 2117 enum pipe pipe;
2159 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; 2118 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2160 2119
2161 if (hotplug_trigger) 2120 if (hotplug_trigger)
2162 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ilk); 2121 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2163 2122
2164 if (de_iir & DE_AUX_CHANNEL_A) 2123 if (de_iir & DE_AUX_CHANNEL_A)
2165 dp_aux_irq_handler(dev); 2124 dp_aux_irq_handler(dev_priv);
2166 2125
2167 if (de_iir & DE_GSE) 2126 if (de_iir & DE_GSE)
2168 intel_opregion_asle_intr(dev); 2127 intel_opregion_asle_intr(dev_priv);
2169 2128
2170 if (de_iir & DE_POISON) 2129 if (de_iir & DE_POISON)
2171 DRM_ERROR("Poison interrupt\n"); 2130 DRM_ERROR("Poison interrupt\n");
2172 2131
2173 for_each_pipe(dev_priv, pipe) { 2132 for_each_pipe(dev_priv, pipe) {
2174 if (de_iir & DE_PIPE_VBLANK(pipe) && 2133 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2175 intel_pipe_handle_vblank(dev, pipe)) 2134 intel_pipe_handle_vblank(dev_priv, pipe))
2176 intel_check_page_flip(dev, pipe); 2135 intel_check_page_flip(dev_priv, pipe);
2177 2136
2178 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) 2137 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2179 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 2138 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2180 2139
2181 if (de_iir & DE_PIPE_CRC_DONE(pipe)) 2140 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2182 i9xx_pipe_crc_irq_handler(dev, pipe); 2141 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2183 2142
2184 /* plane/pipes map 1:1 on ilk+ */ 2143 /* plane/pipes map 1:1 on ilk+ */
2185 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { 2144 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2186 intel_prepare_page_flip(dev, pipe); 2145 intel_finish_page_flip_cs(dev_priv, pipe);
2187 intel_finish_page_flip_plane(dev, pipe);
2188 }
2189 } 2146 }
2190 2147
2191 /* check event from PCH */ 2148 /* check event from PCH */
2192 if (de_iir & DE_PCH_EVENT) { 2149 if (de_iir & DE_PCH_EVENT) {
2193 u32 pch_iir = I915_READ(SDEIIR); 2150 u32 pch_iir = I915_READ(SDEIIR);
2194 2151
2195 if (HAS_PCH_CPT(dev)) 2152 if (HAS_PCH_CPT(dev_priv))
2196 cpt_irq_handler(dev, pch_iir); 2153 cpt_irq_handler(dev_priv, pch_iir);
2197 else 2154 else
2198 ibx_irq_handler(dev, pch_iir); 2155 ibx_irq_handler(dev_priv, pch_iir);
2199 2156
2200 /* should clear PCH hotplug event before clear CPU irq */ 2157 /* should clear PCH hotplug event before clear CPU irq */
2201 I915_WRITE(SDEIIR, pch_iir); 2158 I915_WRITE(SDEIIR, pch_iir);
2202 } 2159 }
2203 2160
2204 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) 2161 if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2205 ironlake_rps_change_irq_handler(dev); 2162 ironlake_rps_change_irq_handler(dev_priv);
2206} 2163}
2207 2164
2208static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) 2165static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2166 u32 de_iir)
2209{ 2167{
2210 struct drm_i915_private *dev_priv = dev->dev_private;
2211 enum pipe pipe; 2168 enum pipe pipe;
2212 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; 2169 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2213 2170
2214 if (hotplug_trigger) 2171 if (hotplug_trigger)
2215 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ivb); 2172 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2216 2173
2217 if (de_iir & DE_ERR_INT_IVB) 2174 if (de_iir & DE_ERR_INT_IVB)
2218 ivb_err_int_handler(dev); 2175 ivb_err_int_handler(dev_priv);
2219 2176
2220 if (de_iir & DE_AUX_CHANNEL_A_IVB) 2177 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2221 dp_aux_irq_handler(dev); 2178 dp_aux_irq_handler(dev_priv);
2222 2179
2223 if (de_iir & DE_GSE_IVB) 2180 if (de_iir & DE_GSE_IVB)
2224 intel_opregion_asle_intr(dev); 2181 intel_opregion_asle_intr(dev_priv);
2225 2182
2226 for_each_pipe(dev_priv, pipe) { 2183 for_each_pipe(dev_priv, pipe) {
2227 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && 2184 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2228 intel_pipe_handle_vblank(dev, pipe)) 2185 intel_pipe_handle_vblank(dev_priv, pipe))
2229 intel_check_page_flip(dev, pipe); 2186 intel_check_page_flip(dev_priv, pipe);
2230 2187
2231 /* plane/pipes map 1:1 on ilk+ */ 2188 /* plane/pipes map 1:1 on ilk+ */
2232 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { 2189 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2233 intel_prepare_page_flip(dev, pipe); 2190 intel_finish_page_flip_cs(dev_priv, pipe);
2234 intel_finish_page_flip_plane(dev, pipe);
2235 }
2236 } 2191 }
2237 2192
2238 /* check event from PCH */ 2193 /* check event from PCH */
2239 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { 2194 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2240 u32 pch_iir = I915_READ(SDEIIR); 2195 u32 pch_iir = I915_READ(SDEIIR);
2241 2196
2242 cpt_irq_handler(dev, pch_iir); 2197 cpt_irq_handler(dev_priv, pch_iir);
2243 2198
2244 /* clear PCH hotplug event before clear CPU irq */ 2199 /* clear PCH hotplug event before clear CPU irq */
2245 I915_WRITE(SDEIIR, pch_iir); 2200 I915_WRITE(SDEIIR, pch_iir);
@@ -2257,7 +2212,7 @@ static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2257static irqreturn_t ironlake_irq_handler(int irq, void *arg) 2212static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2258{ 2213{
2259 struct drm_device *dev = arg; 2214 struct drm_device *dev = arg;
2260 struct drm_i915_private *dev_priv = dev->dev_private; 2215 struct drm_i915_private *dev_priv = to_i915(dev);
2261 u32 de_iir, gt_iir, de_ier, sde_ier = 0; 2216 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2262 irqreturn_t ret = IRQ_NONE; 2217 irqreturn_t ret = IRQ_NONE;
2263 2218
@@ -2277,7 +2232,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2277 * able to process them after we restore SDEIER (as soon as we restore 2232 * able to process them after we restore SDEIER (as soon as we restore
2278 * it, we'll get an interrupt if SDEIIR still has something to process 2233 * it, we'll get an interrupt if SDEIIR still has something to process
2279 * due to its back queue). */ 2234 * due to its back queue). */
2280 if (!HAS_PCH_NOP(dev)) { 2235 if (!HAS_PCH_NOP(dev_priv)) {
2281 sde_ier = I915_READ(SDEIER); 2236 sde_ier = I915_READ(SDEIER);
2282 I915_WRITE(SDEIER, 0); 2237 I915_WRITE(SDEIER, 0);
2283 POSTING_READ(SDEIER); 2238 POSTING_READ(SDEIER);
@@ -2289,7 +2244,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2289 if (gt_iir) { 2244 if (gt_iir) {
2290 I915_WRITE(GTIIR, gt_iir); 2245 I915_WRITE(GTIIR, gt_iir);
2291 ret = IRQ_HANDLED; 2246 ret = IRQ_HANDLED;
2292 if (INTEL_INFO(dev)->gen >= 6) 2247 if (INTEL_GEN(dev_priv) >= 6)
2293 snb_gt_irq_handler(dev_priv, gt_iir); 2248 snb_gt_irq_handler(dev_priv, gt_iir);
2294 else 2249 else
2295 ilk_gt_irq_handler(dev_priv, gt_iir); 2250 ilk_gt_irq_handler(dev_priv, gt_iir);
@@ -2299,13 +2254,13 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2299 if (de_iir) { 2254 if (de_iir) {
2300 I915_WRITE(DEIIR, de_iir); 2255 I915_WRITE(DEIIR, de_iir);
2301 ret = IRQ_HANDLED; 2256 ret = IRQ_HANDLED;
2302 if (INTEL_INFO(dev)->gen >= 7) 2257 if (INTEL_GEN(dev_priv) >= 7)
2303 ivb_display_irq_handler(dev, de_iir); 2258 ivb_display_irq_handler(dev_priv, de_iir);
2304 else 2259 else
2305 ilk_display_irq_handler(dev, de_iir); 2260 ilk_display_irq_handler(dev_priv, de_iir);
2306 } 2261 }
2307 2262
2308 if (INTEL_INFO(dev)->gen >= 6) { 2263 if (INTEL_GEN(dev_priv) >= 6) {
2309 u32 pm_iir = I915_READ(GEN6_PMIIR); 2264 u32 pm_iir = I915_READ(GEN6_PMIIR);
2310 if (pm_iir) { 2265 if (pm_iir) {
2311 I915_WRITE(GEN6_PMIIR, pm_iir); 2266 I915_WRITE(GEN6_PMIIR, pm_iir);
@@ -2316,7 +2271,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2316 2271
2317 I915_WRITE(DEIER, de_ier); 2272 I915_WRITE(DEIER, de_ier);
2318 POSTING_READ(DEIER); 2273 POSTING_READ(DEIER);
2319 if (!HAS_PCH_NOP(dev)) { 2274 if (!HAS_PCH_NOP(dev_priv)) {
2320 I915_WRITE(SDEIER, sde_ier); 2275 I915_WRITE(SDEIER, sde_ier);
2321 POSTING_READ(SDEIER); 2276 POSTING_READ(SDEIER);
2322 } 2277 }
@@ -2327,10 +2282,10 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2327 return ret; 2282 return ret;
2328} 2283}
2329 2284
2330static void bxt_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger, 2285static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2286 u32 hotplug_trigger,
2331 const u32 hpd[HPD_NUM_PINS]) 2287 const u32 hpd[HPD_NUM_PINS])
2332{ 2288{
2333 struct drm_i915_private *dev_priv = to_i915(dev);
2334 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 2289 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2335 2290
2336 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); 2291 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
@@ -2340,13 +2295,12 @@ static void bxt_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
2340 dig_hotplug_reg, hpd, 2295 dig_hotplug_reg, hpd,
2341 bxt_port_hotplug_long_detect); 2296 bxt_port_hotplug_long_detect);
2342 2297
2343 intel_hpd_irq_handler(dev, pin_mask, long_mask); 2298 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2344} 2299}
2345 2300
2346static irqreturn_t 2301static irqreturn_t
2347gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) 2302gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2348{ 2303{
2349 struct drm_device *dev = dev_priv->dev;
2350 irqreturn_t ret = IRQ_NONE; 2304 irqreturn_t ret = IRQ_NONE;
2351 u32 iir; 2305 u32 iir;
2352 enum pipe pipe; 2306 enum pipe pipe;
@@ -2357,7 +2311,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2357 I915_WRITE(GEN8_DE_MISC_IIR, iir); 2311 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2358 ret = IRQ_HANDLED; 2312 ret = IRQ_HANDLED;
2359 if (iir & GEN8_DE_MISC_GSE) 2313 if (iir & GEN8_DE_MISC_GSE)
2360 intel_opregion_asle_intr(dev); 2314 intel_opregion_asle_intr(dev_priv);
2361 else 2315 else
2362 DRM_ERROR("Unexpected DE Misc interrupt\n"); 2316 DRM_ERROR("Unexpected DE Misc interrupt\n");
2363 } 2317 }
@@ -2381,26 +2335,28 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2381 GEN9_AUX_CHANNEL_D; 2335 GEN9_AUX_CHANNEL_D;
2382 2336
2383 if (iir & tmp_mask) { 2337 if (iir & tmp_mask) {
2384 dp_aux_irq_handler(dev); 2338 dp_aux_irq_handler(dev_priv);
2385 found = true; 2339 found = true;
2386 } 2340 }
2387 2341
2388 if (IS_BROXTON(dev_priv)) { 2342 if (IS_BROXTON(dev_priv)) {
2389 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK; 2343 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2390 if (tmp_mask) { 2344 if (tmp_mask) {
2391 bxt_hpd_irq_handler(dev, tmp_mask, hpd_bxt); 2345 bxt_hpd_irq_handler(dev_priv, tmp_mask,
2346 hpd_bxt);
2392 found = true; 2347 found = true;
2393 } 2348 }
2394 } else if (IS_BROADWELL(dev_priv)) { 2349 } else if (IS_BROADWELL(dev_priv)) {
2395 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG; 2350 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2396 if (tmp_mask) { 2351 if (tmp_mask) {
2397 ilk_hpd_irq_handler(dev, tmp_mask, hpd_bdw); 2352 ilk_hpd_irq_handler(dev_priv,
2353 tmp_mask, hpd_bdw);
2398 found = true; 2354 found = true;
2399 } 2355 }
2400 } 2356 }
2401 2357
2402 if (IS_BROXTON(dev) && (iir & BXT_DE_PORT_GMBUS)) { 2358 if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2403 gmbus_irq_handler(dev); 2359 gmbus_irq_handler(dev_priv);
2404 found = true; 2360 found = true;
2405 } 2361 }
2406 2362
@@ -2427,8 +2383,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2427 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir); 2383 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2428 2384
2429 if (iir & GEN8_PIPE_VBLANK && 2385 if (iir & GEN8_PIPE_VBLANK &&
2430 intel_pipe_handle_vblank(dev, pipe)) 2386 intel_pipe_handle_vblank(dev_priv, pipe))
2431 intel_check_page_flip(dev, pipe); 2387 intel_check_page_flip(dev_priv, pipe);
2432 2388
2433 flip_done = iir; 2389 flip_done = iir;
2434 if (INTEL_INFO(dev_priv)->gen >= 9) 2390 if (INTEL_INFO(dev_priv)->gen >= 9)
@@ -2436,13 +2392,11 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2436 else 2392 else
2437 flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE; 2393 flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2438 2394
2439 if (flip_done) { 2395 if (flip_done)
2440 intel_prepare_page_flip(dev, pipe); 2396 intel_finish_page_flip_cs(dev_priv, pipe);
2441 intel_finish_page_flip_plane(dev, pipe);
2442 }
2443 2397
2444 if (iir & GEN8_PIPE_CDCLK_CRC_DONE) 2398 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2445 hsw_pipe_crc_irq_handler(dev, pipe); 2399 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2446 2400
2447 if (iir & GEN8_PIPE_FIFO_UNDERRUN) 2401 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2448 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 2402 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
@@ -2459,7 +2413,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2459 fault_errors); 2413 fault_errors);
2460 } 2414 }
2461 2415
2462 if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) && 2416 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2463 master_ctl & GEN8_DE_PCH_IRQ) { 2417 master_ctl & GEN8_DE_PCH_IRQ) {
2464 /* 2418 /*
2465 * FIXME(BDW): Assume for now that the new interrupt handling 2419 * FIXME(BDW): Assume for now that the new interrupt handling
@@ -2472,9 +2426,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2472 ret = IRQ_HANDLED; 2426 ret = IRQ_HANDLED;
2473 2427
2474 if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv)) 2428 if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2475 spt_irq_handler(dev, iir); 2429 spt_irq_handler(dev_priv, iir);
2476 else 2430 else
2477 cpt_irq_handler(dev, iir); 2431 cpt_irq_handler(dev_priv, iir);
2478 } else { 2432 } else {
2479 /* 2433 /*
2480 * Like on previous PCH there seems to be something 2434 * Like on previous PCH there seems to be something
@@ -2490,7 +2444,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2490static irqreturn_t gen8_irq_handler(int irq, void *arg) 2444static irqreturn_t gen8_irq_handler(int irq, void *arg)
2491{ 2445{
2492 struct drm_device *dev = arg; 2446 struct drm_device *dev = arg;
2493 struct drm_i915_private *dev_priv = dev->dev_private; 2447 struct drm_i915_private *dev_priv = to_i915(dev);
2494 u32 master_ctl; 2448 u32 master_ctl;
2495 u32 gt_iir[4] = {}; 2449 u32 gt_iir[4] = {};
2496 irqreturn_t ret; 2450 irqreturn_t ret;
@@ -2521,11 +2475,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
2521 return ret; 2475 return ret;
2522} 2476}
2523 2477
2524static void i915_error_wake_up(struct drm_i915_private *dev_priv, 2478static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2525 bool reset_completed)
2526{ 2479{
2527 struct intel_engine_cs *engine;
2528
2529 /* 2480 /*
2530 * Notify all waiters for GPU completion events that reset state has 2481 * Notify all waiters for GPU completion events that reset state has
2531 * been changed, and that they need to restart their wait after 2482 * been changed, and that they need to restart their wait after
@@ -2534,36 +2485,28 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2534 */ 2485 */
2535 2486
2536 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ 2487 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2537 for_each_engine(engine, dev_priv) 2488 wake_up_all(&dev_priv->gpu_error.wait_queue);
2538 wake_up_all(&engine->irq_queue);
2539 2489
2540 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ 2490 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2541 wake_up_all(&dev_priv->pending_flip_queue); 2491 wake_up_all(&dev_priv->pending_flip_queue);
2542
2543 /*
2544 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2545 * reset state is cleared.
2546 */
2547 if (reset_completed)
2548 wake_up_all(&dev_priv->gpu_error.reset_queue);
2549} 2492}
2550 2493
2551/** 2494/**
2552 * i915_reset_and_wakeup - do process context error handling work 2495 * i915_reset_and_wakeup - do process context error handling work
2553 * @dev: drm device 2496 * @dev_priv: i915 device private
2554 * 2497 *
2555 * Fire an error uevent so userspace can see that a hang or error 2498 * Fire an error uevent so userspace can see that a hang or error
2556 * was detected. 2499 * was detected.
2557 */ 2500 */
2558static void i915_reset_and_wakeup(struct drm_device *dev) 2501static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2559{ 2502{
2560 struct drm_i915_private *dev_priv = to_i915(dev); 2503 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2561 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; 2504 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2562 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; 2505 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2563 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; 2506 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2564 int ret; 2507 int ret;
2565 2508
2566 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); 2509 kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2567 2510
2568 /* 2511 /*
2569 * Note that there's only one work item which does gpu resets, so we 2512 * Note that there's only one work item which does gpu resets, so we
@@ -2577,8 +2520,7 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
2577 */ 2520 */
2578 if (i915_reset_in_progress(&dev_priv->gpu_error)) { 2521 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
2579 DRM_DEBUG_DRIVER("resetting chip\n"); 2522 DRM_DEBUG_DRIVER("resetting chip\n");
2580 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, 2523 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2581 reset_event);
2582 2524
2583 /* 2525 /*
2584 * In most cases it's guaranteed that we get here with an RPM 2526 * In most cases it's guaranteed that we get here with an RPM
@@ -2589,7 +2531,7 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
2589 */ 2531 */
2590 intel_runtime_pm_get(dev_priv); 2532 intel_runtime_pm_get(dev_priv);
2591 2533
2592 intel_prepare_reset(dev); 2534 intel_prepare_reset(dev_priv);
2593 2535
2594 /* 2536 /*
2595 * All state reset _must_ be completed before we update the 2537 * All state reset _must_ be completed before we update the
@@ -2597,27 +2539,26 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
2597 * pending state and not properly drop locks, resulting in 2539 * pending state and not properly drop locks, resulting in
2598 * deadlocks with the reset work. 2540 * deadlocks with the reset work.
2599 */ 2541 */
2600 ret = i915_reset(dev); 2542 ret = i915_reset(dev_priv);
2601 2543
2602 intel_finish_reset(dev); 2544 intel_finish_reset(dev_priv);
2603 2545
2604 intel_runtime_pm_put(dev_priv); 2546 intel_runtime_pm_put(dev_priv);
2605 2547
2606 if (ret == 0) 2548 if (ret == 0)
2607 kobject_uevent_env(&dev->primary->kdev->kobj, 2549 kobject_uevent_env(kobj,
2608 KOBJ_CHANGE, reset_done_event); 2550 KOBJ_CHANGE, reset_done_event);
2609 2551
2610 /* 2552 /*
2611 * Note: The wake_up also serves as a memory barrier so that 2553 * Note: The wake_up also serves as a memory barrier so that
2612 * waiters see the update value of the reset counter atomic_t. 2554 * waiters see the update value of the reset counter atomic_t.
2613 */ 2555 */
2614 i915_error_wake_up(dev_priv, true); 2556 wake_up_all(&dev_priv->gpu_error.reset_queue);
2615 } 2557 }
2616} 2558}
2617 2559
2618static void i915_report_and_clear_eir(struct drm_device *dev) 2560static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
2619{ 2561{
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621 uint32_t instdone[I915_NUM_INSTDONE_REG]; 2562 uint32_t instdone[I915_NUM_INSTDONE_REG];
2622 u32 eir = I915_READ(EIR); 2563 u32 eir = I915_READ(EIR);
2623 int pipe, i; 2564 int pipe, i;
@@ -2627,9 +2568,9 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
2627 2568
2628 pr_err("render error detected, EIR: 0x%08x\n", eir); 2569 pr_err("render error detected, EIR: 0x%08x\n", eir);
2629 2570
2630 i915_get_extra_instdone(dev, instdone); 2571 i915_get_extra_instdone(dev_priv, instdone);
2631 2572
2632 if (IS_G4X(dev)) { 2573 if (IS_G4X(dev_priv)) {
2633 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { 2574 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2634 u32 ipeir = I915_READ(IPEIR_I965); 2575 u32 ipeir = I915_READ(IPEIR_I965);
2635 2576
@@ -2651,7 +2592,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
2651 } 2592 }
2652 } 2593 }
2653 2594
2654 if (!IS_GEN2(dev)) { 2595 if (!IS_GEN2(dev_priv)) {
2655 if (eir & I915_ERROR_PAGE_TABLE) { 2596 if (eir & I915_ERROR_PAGE_TABLE) {
2656 u32 pgtbl_err = I915_READ(PGTBL_ER); 2597 u32 pgtbl_err = I915_READ(PGTBL_ER);
2657 pr_err("page table error\n"); 2598 pr_err("page table error\n");
@@ -2673,7 +2614,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
2673 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); 2614 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2674 for (i = 0; i < ARRAY_SIZE(instdone); i++) 2615 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2675 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); 2616 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2676 if (INTEL_INFO(dev)->gen < 4) { 2617 if (INTEL_GEN(dev_priv) < 4) {
2677 u32 ipeir = I915_READ(IPEIR); 2618 u32 ipeir = I915_READ(IPEIR);
2678 2619
2679 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); 2620 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
@@ -2709,18 +2650,19 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
2709 2650
2710/** 2651/**
2711 * i915_handle_error - handle a gpu error 2652 * i915_handle_error - handle a gpu error
2712 * @dev: drm device 2653 * @dev_priv: i915 device private
2713 * @engine_mask: mask representing engines that are hung 2654 * @engine_mask: mask representing engines that are hung
2714 * Do some basic checking of register state at error time and 2655 * Do some basic checking of register state at error time and
2715 * dump it to the syslog. Also call i915_capture_error_state() to make 2656 * dump it to the syslog. Also call i915_capture_error_state() to make
2716 * sure we get a record and make it available in debugfs. Fire a uevent 2657 * sure we get a record and make it available in debugfs. Fire a uevent
2717 * so userspace knows something bad happened (should trigger collection 2658 * so userspace knows something bad happened (should trigger collection
2718 * of a ring dump etc.). 2659 * of a ring dump etc.).
2660 * @fmt: Error message format string
2719 */ 2661 */
2720void i915_handle_error(struct drm_device *dev, u32 engine_mask, 2662void i915_handle_error(struct drm_i915_private *dev_priv,
2663 u32 engine_mask,
2721 const char *fmt, ...) 2664 const char *fmt, ...)
2722{ 2665{
2723 struct drm_i915_private *dev_priv = dev->dev_private;
2724 va_list args; 2666 va_list args;
2725 char error_msg[80]; 2667 char error_msg[80];
2726 2668
@@ -2728,8 +2670,8 @@ void i915_handle_error(struct drm_device *dev, u32 engine_mask,
2728 vscnprintf(error_msg, sizeof(error_msg), fmt, args); 2670 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2729 va_end(args); 2671 va_end(args);
2730 2672
2731 i915_capture_error_state(dev, engine_mask, error_msg); 2673 i915_capture_error_state(dev_priv, engine_mask, error_msg);
2732 i915_report_and_clear_eir(dev); 2674 i915_report_and_clear_eir(dev_priv);
2733 2675
2734 if (engine_mask) { 2676 if (engine_mask) {
2735 atomic_or(I915_RESET_IN_PROGRESS_FLAG, 2677 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
@@ -2748,10 +2690,10 @@ void i915_handle_error(struct drm_device *dev, u32 engine_mask,
2748 * ensure that the waiters see the updated value of the reset 2690 * ensure that the waiters see the updated value of the reset
2749 * counter atomic_t. 2691 * counter atomic_t.
2750 */ 2692 */
2751 i915_error_wake_up(dev_priv, false); 2693 i915_error_wake_up(dev_priv);
2752 } 2694 }
2753 2695
2754 i915_reset_and_wakeup(dev); 2696 i915_reset_and_wakeup(dev_priv);
2755} 2697}
2756 2698
2757/* Called from drm generic code, passed 'crtc' which 2699/* Called from drm generic code, passed 'crtc' which
@@ -2759,7 +2701,7 @@ void i915_handle_error(struct drm_device *dev, u32 engine_mask,
2759 */ 2701 */
2760static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe) 2702static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2761{ 2703{
2762 struct drm_i915_private *dev_priv = dev->dev_private; 2704 struct drm_i915_private *dev_priv = to_i915(dev);
2763 unsigned long irqflags; 2705 unsigned long irqflags;
2764 2706
2765 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2707 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2776,7 +2718,7 @@ static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2776 2718
2777static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) 2719static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2778{ 2720{
2779 struct drm_i915_private *dev_priv = dev->dev_private; 2721 struct drm_i915_private *dev_priv = to_i915(dev);
2780 unsigned long irqflags; 2722 unsigned long irqflags;
2781 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : 2723 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2782 DE_PIPE_VBLANK(pipe); 2724 DE_PIPE_VBLANK(pipe);
@@ -2790,7 +2732,7 @@ static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2790 2732
2791static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe) 2733static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2792{ 2734{
2793 struct drm_i915_private *dev_priv = dev->dev_private; 2735 struct drm_i915_private *dev_priv = to_i915(dev);
2794 unsigned long irqflags; 2736 unsigned long irqflags;
2795 2737
2796 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2738 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2803,7 +2745,7 @@ static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2803 2745
2804static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe) 2746static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2805{ 2747{
2806 struct drm_i915_private *dev_priv = dev->dev_private; 2748 struct drm_i915_private *dev_priv = to_i915(dev);
2807 unsigned long irqflags; 2749 unsigned long irqflags;
2808 2750
2809 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2751 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2818,7 +2760,7 @@ static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2818 */ 2760 */
2819static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe) 2761static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2820{ 2762{
2821 struct drm_i915_private *dev_priv = dev->dev_private; 2763 struct drm_i915_private *dev_priv = to_i915(dev);
2822 unsigned long irqflags; 2764 unsigned long irqflags;
2823 2765
2824 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2766 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2830,7 +2772,7 @@ static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2830 2772
2831static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) 2773static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2832{ 2774{
2833 struct drm_i915_private *dev_priv = dev->dev_private; 2775 struct drm_i915_private *dev_priv = to_i915(dev);
2834 unsigned long irqflags; 2776 unsigned long irqflags;
2835 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : 2777 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2836 DE_PIPE_VBLANK(pipe); 2778 DE_PIPE_VBLANK(pipe);
@@ -2842,7 +2784,7 @@ static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2842 2784
2843static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe) 2785static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2844{ 2786{
2845 struct drm_i915_private *dev_priv = dev->dev_private; 2787 struct drm_i915_private *dev_priv = to_i915(dev);
2846 unsigned long irqflags; 2788 unsigned long irqflags;
2847 2789
2848 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2790 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2853,7 +2795,7 @@ static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2853 2795
2854static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe) 2796static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2855{ 2797{
2856 struct drm_i915_private *dev_priv = dev->dev_private; 2798 struct drm_i915_private *dev_priv = to_i915(dev);
2857 unsigned long irqflags; 2799 unsigned long irqflags;
2858 2800
2859 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2801 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2869,9 +2811,9 @@ ring_idle(struct intel_engine_cs *engine, u32 seqno)
2869} 2811}
2870 2812
2871static bool 2813static bool
2872ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) 2814ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
2873{ 2815{
2874 if (INTEL_INFO(dev)->gen >= 8) { 2816 if (INTEL_GEN(engine->i915) >= 8) {
2875 return (ipehr >> 23) == 0x1c; 2817 return (ipehr >> 23) == 0x1c;
2876 } else { 2818 } else {
2877 ipehr &= ~MI_SEMAPHORE_SYNC_MASK; 2819 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
@@ -2884,10 +2826,10 @@ static struct intel_engine_cs *
2884semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr, 2826semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
2885 u64 offset) 2827 u64 offset)
2886{ 2828{
2887 struct drm_i915_private *dev_priv = engine->dev->dev_private; 2829 struct drm_i915_private *dev_priv = engine->i915;
2888 struct intel_engine_cs *signaller; 2830 struct intel_engine_cs *signaller;
2889 2831
2890 if (INTEL_INFO(dev_priv)->gen >= 8) { 2832 if (INTEL_GEN(dev_priv) >= 8) {
2891 for_each_engine(signaller, dev_priv) { 2833 for_each_engine(signaller, dev_priv) {
2892 if (engine == signaller) 2834 if (engine == signaller)
2893 continue; 2835 continue;
@@ -2916,7 +2858,7 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
2916static struct intel_engine_cs * 2858static struct intel_engine_cs *
2917semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno) 2859semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2918{ 2860{
2919 struct drm_i915_private *dev_priv = engine->dev->dev_private; 2861 struct drm_i915_private *dev_priv = engine->i915;
2920 u32 cmd, ipehr, head; 2862 u32 cmd, ipehr, head;
2921 u64 offset = 0; 2863 u64 offset = 0;
2922 int i, backwards; 2864 int i, backwards;
@@ -2942,7 +2884,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2942 return NULL; 2884 return NULL;
2943 2885
2944 ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); 2886 ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2945 if (!ipehr_is_semaphore_wait(engine->dev, ipehr)) 2887 if (!ipehr_is_semaphore_wait(engine, ipehr))
2946 return NULL; 2888 return NULL;
2947 2889
2948 /* 2890 /*
@@ -2954,7 +2896,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2954 * ringbuffer itself. 2896 * ringbuffer itself.
2955 */ 2897 */
2956 head = I915_READ_HEAD(engine) & HEAD_ADDR; 2898 head = I915_READ_HEAD(engine) & HEAD_ADDR;
2957 backwards = (INTEL_INFO(engine->dev)->gen >= 8) ? 5 : 4; 2899 backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
2958 2900
2959 for (i = backwards; i; --i) { 2901 for (i = backwards; i; --i) {
2960 /* 2902 /*
@@ -2976,7 +2918,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2976 return NULL; 2918 return NULL;
2977 2919
2978 *seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1; 2920 *seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1;
2979 if (INTEL_INFO(engine->dev)->gen >= 8) { 2921 if (INTEL_GEN(dev_priv) >= 8) {
2980 offset = ioread32(engine->buffer->virtual_start + head + 12); 2922 offset = ioread32(engine->buffer->virtual_start + head + 12);
2981 offset <<= 32; 2923 offset <<= 32;
2982 offset = ioread32(engine->buffer->virtual_start + head + 8); 2924 offset = ioread32(engine->buffer->virtual_start + head + 8);
@@ -2986,7 +2928,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2986 2928
2987static int semaphore_passed(struct intel_engine_cs *engine) 2929static int semaphore_passed(struct intel_engine_cs *engine)
2988{ 2930{
2989 struct drm_i915_private *dev_priv = engine->dev->dev_private; 2931 struct drm_i915_private *dev_priv = engine->i915;
2990 struct intel_engine_cs *signaller; 2932 struct intel_engine_cs *signaller;
2991 u32 seqno; 2933 u32 seqno;
2992 2934
@@ -3000,7 +2942,7 @@ static int semaphore_passed(struct intel_engine_cs *engine)
3000 if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES) 2942 if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
3001 return -1; 2943 return -1;
3002 2944
3003 if (i915_seqno_passed(signaller->get_seqno(signaller), seqno)) 2945 if (i915_seqno_passed(intel_engine_get_seqno(signaller), seqno))
3004 return 1; 2946 return 1;
3005 2947
3006 /* cursory check for an unkickable deadlock */ 2948 /* cursory check for an unkickable deadlock */
@@ -3028,7 +2970,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine)
3028 if (engine->id != RCS) 2970 if (engine->id != RCS)
3029 return true; 2971 return true;
3030 2972
3031 i915_get_extra_instdone(engine->dev, instdone); 2973 i915_get_extra_instdone(engine->i915, instdone);
3032 2974
3033 /* There might be unstable subunit states even when 2975 /* There might be unstable subunit states even when
3034 * actual head is not moving. Filter out the unstable ones by 2976 * actual head is not moving. Filter out the unstable ones by
@@ -3069,8 +3011,7 @@ head_stuck(struct intel_engine_cs *engine, u64 acthd)
3069static enum intel_ring_hangcheck_action 3011static enum intel_ring_hangcheck_action
3070ring_stuck(struct intel_engine_cs *engine, u64 acthd) 3012ring_stuck(struct intel_engine_cs *engine, u64 acthd)
3071{ 3013{
3072 struct drm_device *dev = engine->dev; 3014 struct drm_i915_private *dev_priv = engine->i915;
3073 struct drm_i915_private *dev_priv = dev->dev_private;
3074 enum intel_ring_hangcheck_action ha; 3015 enum intel_ring_hangcheck_action ha;
3075 u32 tmp; 3016 u32 tmp;
3076 3017
@@ -3078,7 +3019,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
3078 if (ha != HANGCHECK_HUNG) 3019 if (ha != HANGCHECK_HUNG)
3079 return ha; 3020 return ha;
3080 3021
3081 if (IS_GEN2(dev)) 3022 if (IS_GEN2(dev_priv))
3082 return HANGCHECK_HUNG; 3023 return HANGCHECK_HUNG;
3083 3024
3084 /* Is the chip hanging on a WAIT_FOR_EVENT? 3025 /* Is the chip hanging on a WAIT_FOR_EVENT?
@@ -3088,19 +3029,19 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
3088 */ 3029 */
3089 tmp = I915_READ_CTL(engine); 3030 tmp = I915_READ_CTL(engine);
3090 if (tmp & RING_WAIT) { 3031 if (tmp & RING_WAIT) {
3091 i915_handle_error(dev, 0, 3032 i915_handle_error(dev_priv, 0,
3092 "Kicking stuck wait on %s", 3033 "Kicking stuck wait on %s",
3093 engine->name); 3034 engine->name);
3094 I915_WRITE_CTL(engine, tmp); 3035 I915_WRITE_CTL(engine, tmp);
3095 return HANGCHECK_KICK; 3036 return HANGCHECK_KICK;
3096 } 3037 }
3097 3038
3098 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { 3039 if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3099 switch (semaphore_passed(engine)) { 3040 switch (semaphore_passed(engine)) {
3100 default: 3041 default:
3101 return HANGCHECK_HUNG; 3042 return HANGCHECK_HUNG;
3102 case 1: 3043 case 1:
3103 i915_handle_error(dev, 0, 3044 i915_handle_error(dev_priv, 0,
3104 "Kicking stuck semaphore on %s", 3045 "Kicking stuck semaphore on %s",
3105 engine->name); 3046 engine->name);
3106 I915_WRITE_CTL(engine, tmp); 3047 I915_WRITE_CTL(engine, tmp);
@@ -3113,23 +3054,21 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
3113 return HANGCHECK_HUNG; 3054 return HANGCHECK_HUNG;
3114} 3055}
3115 3056
3116static unsigned kick_waiters(struct intel_engine_cs *engine) 3057static unsigned long kick_waiters(struct intel_engine_cs *engine)
3117{ 3058{
3118 struct drm_i915_private *i915 = to_i915(engine->dev); 3059 struct drm_i915_private *i915 = engine->i915;
3119 unsigned user_interrupts = READ_ONCE(engine->user_interrupts); 3060 unsigned long irq_count = READ_ONCE(engine->breadcrumbs.irq_wakeups);
3120 3061
3121 if (engine->hangcheck.user_interrupts == user_interrupts && 3062 if (engine->hangcheck.user_interrupts == irq_count &&
3122 !test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) { 3063 !test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) {
3123 if (!(i915->gpu_error.test_irq_rings & intel_engine_flag(engine))) 3064 if (!test_bit(engine->id, &i915->gpu_error.test_irq_rings))
3124 DRM_ERROR("Hangcheck timer elapsed... %s idle\n", 3065 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3125 engine->name); 3066 engine->name);
3126 else 3067
3127 DRM_INFO("Fake missed irq on %s\n", 3068 intel_engine_enable_fake_irq(engine);
3128 engine->name);
3129 wake_up_all(&engine->irq_queue);
3130 } 3069 }
3131 3070
3132 return user_interrupts; 3071 return irq_count;
3133} 3072}
3134/* 3073/*
3135 * This is called when the chip hasn't reported back with completed 3074 * This is called when the chip hasn't reported back with completed
@@ -3144,11 +3083,9 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
3144 struct drm_i915_private *dev_priv = 3083 struct drm_i915_private *dev_priv =
3145 container_of(work, typeof(*dev_priv), 3084 container_of(work, typeof(*dev_priv),
3146 gpu_error.hangcheck_work.work); 3085 gpu_error.hangcheck_work.work);
3147 struct drm_device *dev = dev_priv->dev;
3148 struct intel_engine_cs *engine; 3086 struct intel_engine_cs *engine;
3149 enum intel_engine_id id; 3087 unsigned int hung = 0, stuck = 0;
3150 int busy_count = 0, rings_hung = 0; 3088 int busy_count = 0;
3151 bool stuck[I915_NUM_ENGINES] = { 0 };
3152#define BUSY 1 3089#define BUSY 1
3153#define KICK 5 3090#define KICK 5
3154#define HUNG 20 3091#define HUNG 20
@@ -3157,12 +3094,8 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
3157 if (!i915.enable_hangcheck) 3094 if (!i915.enable_hangcheck)
3158 return; 3095 return;
3159 3096
3160 /* 3097 if (!READ_ONCE(dev_priv->gt.awake))
3161 * The hangcheck work is synced during runtime suspend, we don't 3098 return;
3162 * require a wakeref. TODO: instead of disabling the asserts make
3163 * sure that we hold a reference when this work is running.
3164 */
3165 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3166 3099
3167 /* As enabling the GPU requires fairly extensive mmio access, 3100 /* As enabling the GPU requires fairly extensive mmio access,
3168 * periodically arm the mmio checker to see if we are triggering 3101 * periodically arm the mmio checker to see if we are triggering
@@ -3170,11 +3103,11 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
3170 */ 3103 */
3171 intel_uncore_arm_unclaimed_mmio_detection(dev_priv); 3104 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3172 3105
3173 for_each_engine_id(engine, dev_priv, id) { 3106 for_each_engine(engine, dev_priv) {
3107 bool busy = intel_engine_has_waiter(engine);
3174 u64 acthd; 3108 u64 acthd;
3175 u32 seqno; 3109 u32 seqno;
3176 unsigned user_interrupts; 3110 unsigned user_interrupts;
3177 bool busy = true;
3178 3111
3179 semaphore_clear_deadlocks(dev_priv); 3112 semaphore_clear_deadlocks(dev_priv);
3180 3113
@@ -3189,7 +3122,7 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
3189 engine->irq_seqno_barrier(engine); 3122 engine->irq_seqno_barrier(engine);
3190 3123
3191 acthd = intel_ring_get_active_head(engine); 3124 acthd = intel_ring_get_active_head(engine);
3192 seqno = engine->get_seqno(engine); 3125 seqno = intel_engine_get_seqno(engine);
3193 3126
3194 /* Reset stuck interrupts between batch advances */ 3127 /* Reset stuck interrupts between batch advances */
3195 user_interrupts = 0; 3128 user_interrupts = 0;
@@ -3197,12 +3130,11 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
3197 if (engine->hangcheck.seqno == seqno) { 3130 if (engine->hangcheck.seqno == seqno) {
3198 if (ring_idle(engine, seqno)) { 3131 if (ring_idle(engine, seqno)) {
3199 engine->hangcheck.action = HANGCHECK_IDLE; 3132 engine->hangcheck.action = HANGCHECK_IDLE;
3200 if (waitqueue_active(&engine->irq_queue)) { 3133 if (busy) {
3201 /* Safeguard against driver failure */ 3134 /* Safeguard against driver failure */
3202 user_interrupts = kick_waiters(engine); 3135 user_interrupts = kick_waiters(engine);
3203 engine->hangcheck.score += BUSY; 3136 engine->hangcheck.score += BUSY;
3204 } else 3137 }
3205 busy = false;
3206 } else { 3138 } else {
3207 /* We always increment the hangcheck score 3139 /* We always increment the hangcheck score
3208 * if the ring is busy and still processing 3140 * if the ring is busy and still processing
@@ -3234,10 +3166,15 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
3234 break; 3166 break;
3235 case HANGCHECK_HUNG: 3167 case HANGCHECK_HUNG:
3236 engine->hangcheck.score += HUNG; 3168 engine->hangcheck.score += HUNG;
3237 stuck[id] = true;
3238 break; 3169 break;
3239 } 3170 }
3240 } 3171 }
3172
3173 if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3174 hung |= intel_engine_flag(engine);
3175 if (engine->hangcheck.action != HANGCHECK_HUNG)
3176 stuck |= intel_engine_flag(engine);
3177 }
3241 } else { 3178 } else {
3242 engine->hangcheck.action = HANGCHECK_ACTIVE; 3179 engine->hangcheck.action = HANGCHECK_ACTIVE;
3243 3180
@@ -3262,48 +3199,33 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
3262 busy_count += busy; 3199 busy_count += busy;
3263 } 3200 }
3264 3201
3265 for_each_engine_id(engine, dev_priv, id) { 3202 if (hung) {
3266 if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { 3203 char msg[80];
3267 DRM_INFO("%s on %s\n", 3204 int len;
3268 stuck[id] ? "stuck" : "no progress",
3269 engine->name);
3270 rings_hung |= intel_engine_flag(engine);
3271 }
3272 }
3273 3205
3274 if (rings_hung) { 3206 /* If some rings hung but others were still busy, only
3275 i915_handle_error(dev, rings_hung, "Engine(s) hung"); 3207 * blame the hanging rings in the synopsis.
3276 goto out; 3208 */
3209 if (stuck != hung)
3210 hung &= ~stuck;
3211 len = scnprintf(msg, sizeof(msg),
3212 "%s on ", stuck == hung ? "No progress" : "Hang");
3213 for_each_engine_masked(engine, dev_priv, hung)
3214 len += scnprintf(msg + len, sizeof(msg) - len,
3215 "%s, ", engine->name);
3216 msg[len-2] = '\0';
3217
3218 return i915_handle_error(dev_priv, hung, msg);
3277 } 3219 }
3278 3220
3221 /* Reset timer in case GPU hangs without another request being added */
3279 if (busy_count) 3222 if (busy_count)
3280 /* Reset timer case chip hangs without another request 3223 i915_queue_hangcheck(dev_priv);
3281 * being added */
3282 i915_queue_hangcheck(dev);
3283
3284out:
3285 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3286}
3287
3288void i915_queue_hangcheck(struct drm_device *dev)
3289{
3290 struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
3291
3292 if (!i915.enable_hangcheck)
3293 return;
3294
3295 /* Don't continually defer the hangcheck so that it is always run at
3296 * least once after work has been scheduled on any ring. Otherwise,
3297 * we will ignore a hung ring if a second ring is kept busy.
3298 */
3299
3300 queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3301 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
3302} 3224}
3303 3225
3304static void ibx_irq_reset(struct drm_device *dev) 3226static void ibx_irq_reset(struct drm_device *dev)
3305{ 3227{
3306 struct drm_i915_private *dev_priv = dev->dev_private; 3228 struct drm_i915_private *dev_priv = to_i915(dev);
3307 3229
3308 if (HAS_PCH_NOP(dev)) 3230 if (HAS_PCH_NOP(dev))
3309 return; 3231 return;
@@ -3324,7 +3246,7 @@ static void ibx_irq_reset(struct drm_device *dev)
3324 */ 3246 */
3325static void ibx_irq_pre_postinstall(struct drm_device *dev) 3247static void ibx_irq_pre_postinstall(struct drm_device *dev)
3326{ 3248{
3327 struct drm_i915_private *dev_priv = dev->dev_private; 3249 struct drm_i915_private *dev_priv = to_i915(dev);
3328 3250
3329 if (HAS_PCH_NOP(dev)) 3251 if (HAS_PCH_NOP(dev))
3330 return; 3252 return;
@@ -3336,7 +3258,7 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
3336 3258
3337static void gen5_gt_irq_reset(struct drm_device *dev) 3259static void gen5_gt_irq_reset(struct drm_device *dev)
3338{ 3260{
3339 struct drm_i915_private *dev_priv = dev->dev_private; 3261 struct drm_i915_private *dev_priv = to_i915(dev);
3340 3262
3341 GEN5_IRQ_RESET(GT); 3263 GEN5_IRQ_RESET(GT);
3342 if (INTEL_INFO(dev)->gen >= 6) 3264 if (INTEL_INFO(dev)->gen >= 6)
@@ -3396,7 +3318,7 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3396*/ 3318*/
3397static void ironlake_irq_reset(struct drm_device *dev) 3319static void ironlake_irq_reset(struct drm_device *dev)
3398{ 3320{
3399 struct drm_i915_private *dev_priv = dev->dev_private; 3321 struct drm_i915_private *dev_priv = to_i915(dev);
3400 3322
3401 I915_WRITE(HWSTAM, 0xffffffff); 3323 I915_WRITE(HWSTAM, 0xffffffff);
3402 3324
@@ -3411,7 +3333,7 @@ static void ironlake_irq_reset(struct drm_device *dev)
3411 3333
3412static void valleyview_irq_preinstall(struct drm_device *dev) 3334static void valleyview_irq_preinstall(struct drm_device *dev)
3413{ 3335{
3414 struct drm_i915_private *dev_priv = dev->dev_private; 3336 struct drm_i915_private *dev_priv = to_i915(dev);
3415 3337
3416 I915_WRITE(VLV_MASTER_IER, 0); 3338 I915_WRITE(VLV_MASTER_IER, 0);
3417 POSTING_READ(VLV_MASTER_IER); 3339 POSTING_READ(VLV_MASTER_IER);
@@ -3434,7 +3356,7 @@ static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3434 3356
3435static void gen8_irq_reset(struct drm_device *dev) 3357static void gen8_irq_reset(struct drm_device *dev)
3436{ 3358{
3437 struct drm_i915_private *dev_priv = dev->dev_private; 3359 struct drm_i915_private *dev_priv = to_i915(dev);
3438 int pipe; 3360 int pipe;
3439 3361
3440 I915_WRITE(GEN8_MASTER_IRQ, 0); 3362 I915_WRITE(GEN8_MASTER_IRQ, 0);
@@ -3480,12 +3402,12 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3480 spin_unlock_irq(&dev_priv->irq_lock); 3402 spin_unlock_irq(&dev_priv->irq_lock);
3481 3403
3482 /* make sure we're done processing display irqs */ 3404 /* make sure we're done processing display irqs */
3483 synchronize_irq(dev_priv->dev->irq); 3405 synchronize_irq(dev_priv->drm.irq);
3484} 3406}
3485 3407
3486static void cherryview_irq_preinstall(struct drm_device *dev) 3408static void cherryview_irq_preinstall(struct drm_device *dev)
3487{ 3409{
3488 struct drm_i915_private *dev_priv = dev->dev_private; 3410 struct drm_i915_private *dev_priv = to_i915(dev);
3489 3411
3490 I915_WRITE(GEN8_MASTER_IRQ, 0); 3412 I915_WRITE(GEN8_MASTER_IRQ, 0);
3491 POSTING_READ(GEN8_MASTER_IRQ); 3413 POSTING_READ(GEN8_MASTER_IRQ);
@@ -3500,31 +3422,29 @@ static void cherryview_irq_preinstall(struct drm_device *dev)
3500 spin_unlock_irq(&dev_priv->irq_lock); 3422 spin_unlock_irq(&dev_priv->irq_lock);
3501} 3423}
3502 3424
3503static u32 intel_hpd_enabled_irqs(struct drm_device *dev, 3425static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3504 const u32 hpd[HPD_NUM_PINS]) 3426 const u32 hpd[HPD_NUM_PINS])
3505{ 3427{
3506 struct drm_i915_private *dev_priv = to_i915(dev);
3507 struct intel_encoder *encoder; 3428 struct intel_encoder *encoder;
3508 u32 enabled_irqs = 0; 3429 u32 enabled_irqs = 0;
3509 3430
3510 for_each_intel_encoder(dev, encoder) 3431 for_each_intel_encoder(&dev_priv->drm, encoder)
3511 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) 3432 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3512 enabled_irqs |= hpd[encoder->hpd_pin]; 3433 enabled_irqs |= hpd[encoder->hpd_pin];
3513 3434
3514 return enabled_irqs; 3435 return enabled_irqs;
3515} 3436}
3516 3437
3517static void ibx_hpd_irq_setup(struct drm_device *dev) 3438static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3518{ 3439{
3519 struct drm_i915_private *dev_priv = dev->dev_private;
3520 u32 hotplug_irqs, hotplug, enabled_irqs; 3440 u32 hotplug_irqs, hotplug, enabled_irqs;
3521 3441
3522 if (HAS_PCH_IBX(dev)) { 3442 if (HAS_PCH_IBX(dev_priv)) {
3523 hotplug_irqs = SDE_HOTPLUG_MASK; 3443 hotplug_irqs = SDE_HOTPLUG_MASK;
3524 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx); 3444 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3525 } else { 3445 } else {
3526 hotplug_irqs = SDE_HOTPLUG_MASK_CPT; 3446 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3527 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt); 3447 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3528 } 3448 }
3529 3449
3530 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 3450 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
@@ -3543,18 +3463,17 @@ static void ibx_hpd_irq_setup(struct drm_device *dev)
3543 * When CPU and PCH are on the same package, port A 3463 * When CPU and PCH are on the same package, port A
3544 * HPD must be enabled in both north and south. 3464 * HPD must be enabled in both north and south.
3545 */ 3465 */
3546 if (HAS_PCH_LPT_LP(dev)) 3466 if (HAS_PCH_LPT_LP(dev_priv))
3547 hotplug |= PORTA_HOTPLUG_ENABLE; 3467 hotplug |= PORTA_HOTPLUG_ENABLE;
3548 I915_WRITE(PCH_PORT_HOTPLUG, hotplug); 3468 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3549} 3469}
3550 3470
3551static void spt_hpd_irq_setup(struct drm_device *dev) 3471static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3552{ 3472{
3553 struct drm_i915_private *dev_priv = dev->dev_private;
3554 u32 hotplug_irqs, hotplug, enabled_irqs; 3473 u32 hotplug_irqs, hotplug, enabled_irqs;
3555 3474
3556 hotplug_irqs = SDE_HOTPLUG_MASK_SPT; 3475 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3557 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt); 3476 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3558 3477
3559 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 3478 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3560 3479
@@ -3569,24 +3488,23 @@ static void spt_hpd_irq_setup(struct drm_device *dev)
3569 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug); 3488 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3570} 3489}
3571 3490
3572static void ilk_hpd_irq_setup(struct drm_device *dev) 3491static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3573{ 3492{
3574 struct drm_i915_private *dev_priv = dev->dev_private;
3575 u32 hotplug_irqs, hotplug, enabled_irqs; 3493 u32 hotplug_irqs, hotplug, enabled_irqs;
3576 3494
3577 if (INTEL_INFO(dev)->gen >= 8) { 3495 if (INTEL_GEN(dev_priv) >= 8) {
3578 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; 3496 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3579 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw); 3497 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3580 3498
3581 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); 3499 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3582 } else if (INTEL_INFO(dev)->gen >= 7) { 3500 } else if (INTEL_GEN(dev_priv) >= 7) {
3583 hotplug_irqs = DE_DP_A_HOTPLUG_IVB; 3501 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3584 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb); 3502 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3585 3503
3586 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); 3504 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3587 } else { 3505 } else {
3588 hotplug_irqs = DE_DP_A_HOTPLUG; 3506 hotplug_irqs = DE_DP_A_HOTPLUG;
3589 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ilk); 3507 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3590 3508
3591 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); 3509 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3592 } 3510 }
@@ -3601,15 +3519,14 @@ static void ilk_hpd_irq_setup(struct drm_device *dev)
3601 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms; 3519 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3602 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); 3520 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3603 3521
3604 ibx_hpd_irq_setup(dev); 3522 ibx_hpd_irq_setup(dev_priv);
3605} 3523}
3606 3524
3607static void bxt_hpd_irq_setup(struct drm_device *dev) 3525static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3608{ 3526{
3609 struct drm_i915_private *dev_priv = dev->dev_private;
3610 u32 hotplug_irqs, hotplug, enabled_irqs; 3527 u32 hotplug_irqs, hotplug, enabled_irqs;
3611 3528
3612 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bxt); 3529 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3613 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; 3530 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3614 3531
3615 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); 3532 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
@@ -3642,7 +3559,7 @@ static void bxt_hpd_irq_setup(struct drm_device *dev)
3642 3559
3643static void ibx_irq_postinstall(struct drm_device *dev) 3560static void ibx_irq_postinstall(struct drm_device *dev)
3644{ 3561{
3645 struct drm_i915_private *dev_priv = dev->dev_private; 3562 struct drm_i915_private *dev_priv = to_i915(dev);
3646 u32 mask; 3563 u32 mask;
3647 3564
3648 if (HAS_PCH_NOP(dev)) 3565 if (HAS_PCH_NOP(dev))
@@ -3659,7 +3576,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
3659 3576
3660static void gen5_gt_irq_postinstall(struct drm_device *dev) 3577static void gen5_gt_irq_postinstall(struct drm_device *dev)
3661{ 3578{
3662 struct drm_i915_private *dev_priv = dev->dev_private; 3579 struct drm_i915_private *dev_priv = to_i915(dev);
3663 u32 pm_irqs, gt_irqs; 3580 u32 pm_irqs, gt_irqs;
3664 3581
3665 pm_irqs = gt_irqs = 0; 3582 pm_irqs = gt_irqs = 0;
@@ -3673,8 +3590,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
3673 3590
3674 gt_irqs |= GT_RENDER_USER_INTERRUPT; 3591 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3675 if (IS_GEN5(dev)) { 3592 if (IS_GEN5(dev)) {
3676 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | 3593 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3677 ILK_BSD_USER_INTERRUPT;
3678 } else { 3594 } else {
3679 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; 3595 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3680 } 3596 }
@@ -3696,7 +3612,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
3696 3612
3697static int ironlake_irq_postinstall(struct drm_device *dev) 3613static int ironlake_irq_postinstall(struct drm_device *dev)
3698{ 3614{
3699 struct drm_i915_private *dev_priv = dev->dev_private; 3615 struct drm_i915_private *dev_priv = to_i915(dev);
3700 u32 display_mask, extra_mask; 3616 u32 display_mask, extra_mask;
3701 3617
3702 if (INTEL_INFO(dev)->gen >= 7) { 3618 if (INTEL_INFO(dev)->gen >= 7) {
@@ -3775,7 +3691,7 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3775 3691
3776static int valleyview_irq_postinstall(struct drm_device *dev) 3692static int valleyview_irq_postinstall(struct drm_device *dev)
3777{ 3693{
3778 struct drm_i915_private *dev_priv = dev->dev_private; 3694 struct drm_i915_private *dev_priv = to_i915(dev);
3779 3695
3780 gen5_gt_irq_postinstall(dev); 3696 gen5_gt_irq_postinstall(dev);
3781 3697
@@ -3827,6 +3743,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3827 uint32_t de_pipe_enables; 3743 uint32_t de_pipe_enables;
3828 u32 de_port_masked = GEN8_AUX_CHANNEL_A; 3744 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3829 u32 de_port_enables; 3745 u32 de_port_enables;
3746 u32 de_misc_masked = GEN8_DE_MISC_GSE;
3830 enum pipe pipe; 3747 enum pipe pipe;
3831 3748
3832 if (INTEL_INFO(dev_priv)->gen >= 9) { 3749 if (INTEL_INFO(dev_priv)->gen >= 9) {
@@ -3862,11 +3779,12 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3862 de_pipe_enables); 3779 de_pipe_enables);
3863 3780
3864 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables); 3781 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3782 GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3865} 3783}
3866 3784
3867static int gen8_irq_postinstall(struct drm_device *dev) 3785static int gen8_irq_postinstall(struct drm_device *dev)
3868{ 3786{
3869 struct drm_i915_private *dev_priv = dev->dev_private; 3787 struct drm_i915_private *dev_priv = to_i915(dev);
3870 3788
3871 if (HAS_PCH_SPLIT(dev)) 3789 if (HAS_PCH_SPLIT(dev))
3872 ibx_irq_pre_postinstall(dev); 3790 ibx_irq_pre_postinstall(dev);
@@ -3885,7 +3803,7 @@ static int gen8_irq_postinstall(struct drm_device *dev)
3885 3803
3886static int cherryview_irq_postinstall(struct drm_device *dev) 3804static int cherryview_irq_postinstall(struct drm_device *dev)
3887{ 3805{
3888 struct drm_i915_private *dev_priv = dev->dev_private; 3806 struct drm_i915_private *dev_priv = to_i915(dev);
3889 3807
3890 gen8_gt_irq_postinstall(dev_priv); 3808 gen8_gt_irq_postinstall(dev_priv);
3891 3809
@@ -3902,7 +3820,7 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
3902 3820
3903static void gen8_irq_uninstall(struct drm_device *dev) 3821static void gen8_irq_uninstall(struct drm_device *dev)
3904{ 3822{
3905 struct drm_i915_private *dev_priv = dev->dev_private; 3823 struct drm_i915_private *dev_priv = to_i915(dev);
3906 3824
3907 if (!dev_priv) 3825 if (!dev_priv)
3908 return; 3826 return;
@@ -3912,7 +3830,7 @@ static void gen8_irq_uninstall(struct drm_device *dev)
3912 3830
3913static void valleyview_irq_uninstall(struct drm_device *dev) 3831static void valleyview_irq_uninstall(struct drm_device *dev)
3914{ 3832{
3915 struct drm_i915_private *dev_priv = dev->dev_private; 3833 struct drm_i915_private *dev_priv = to_i915(dev);
3916 3834
3917 if (!dev_priv) 3835 if (!dev_priv)
3918 return; 3836 return;
@@ -3932,7 +3850,7 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
3932 3850
3933static void cherryview_irq_uninstall(struct drm_device *dev) 3851static void cherryview_irq_uninstall(struct drm_device *dev)
3934{ 3852{
3935 struct drm_i915_private *dev_priv = dev->dev_private; 3853 struct drm_i915_private *dev_priv = to_i915(dev);
3936 3854
3937 if (!dev_priv) 3855 if (!dev_priv)
3938 return; 3856 return;
@@ -3952,7 +3870,7 @@ static void cherryview_irq_uninstall(struct drm_device *dev)
3952 3870
3953static void ironlake_irq_uninstall(struct drm_device *dev) 3871static void ironlake_irq_uninstall(struct drm_device *dev)
3954{ 3872{
3955 struct drm_i915_private *dev_priv = dev->dev_private; 3873 struct drm_i915_private *dev_priv = to_i915(dev);
3956 3874
3957 if (!dev_priv) 3875 if (!dev_priv)
3958 return; 3876 return;
@@ -3962,7 +3880,7 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
3962 3880
3963static void i8xx_irq_preinstall(struct drm_device * dev) 3881static void i8xx_irq_preinstall(struct drm_device * dev)
3964{ 3882{
3965 struct drm_i915_private *dev_priv = dev->dev_private; 3883 struct drm_i915_private *dev_priv = to_i915(dev);
3966 int pipe; 3884 int pipe;
3967 3885
3968 for_each_pipe(dev_priv, pipe) 3886 for_each_pipe(dev_priv, pipe)
@@ -3974,7 +3892,7 @@ static void i8xx_irq_preinstall(struct drm_device * dev)
3974 3892
3975static int i8xx_irq_postinstall(struct drm_device *dev) 3893static int i8xx_irq_postinstall(struct drm_device *dev)
3976{ 3894{
3977 struct drm_i915_private *dev_priv = dev->dev_private; 3895 struct drm_i915_private *dev_priv = to_i915(dev);
3978 3896
3979 I915_WRITE16(EMR, 3897 I915_WRITE16(EMR,
3980 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 3898 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
@@ -4006,13 +3924,12 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
4006/* 3924/*
4007 * Returns true when a page flip has completed. 3925 * Returns true when a page flip has completed.
4008 */ 3926 */
4009static bool i8xx_handle_vblank(struct drm_device *dev, 3927static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
4010 int plane, int pipe, u32 iir) 3928 int plane, int pipe, u32 iir)
4011{ 3929{
4012 struct drm_i915_private *dev_priv = dev->dev_private;
4013 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); 3930 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4014 3931
4015 if (!intel_pipe_handle_vblank(dev, pipe)) 3932 if (!intel_pipe_handle_vblank(dev_priv, pipe))
4016 return false; 3933 return false;
4017 3934
4018 if ((iir & flip_pending) == 0) 3935 if ((iir & flip_pending) == 0)
@@ -4027,19 +3944,18 @@ static bool i8xx_handle_vblank(struct drm_device *dev,
4027 if (I915_READ16(ISR) & flip_pending) 3944 if (I915_READ16(ISR) & flip_pending)
4028 goto check_page_flip; 3945 goto check_page_flip;
4029 3946
4030 intel_prepare_page_flip(dev, plane); 3947 intel_finish_page_flip_cs(dev_priv, pipe);
4031 intel_finish_page_flip(dev, pipe);
4032 return true; 3948 return true;
4033 3949
4034check_page_flip: 3950check_page_flip:
4035 intel_check_page_flip(dev, pipe); 3951 intel_check_page_flip(dev_priv, pipe);
4036 return false; 3952 return false;
4037} 3953}
4038 3954
4039static irqreturn_t i8xx_irq_handler(int irq, void *arg) 3955static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4040{ 3956{
4041 struct drm_device *dev = arg; 3957 struct drm_device *dev = arg;
4042 struct drm_i915_private *dev_priv = dev->dev_private; 3958 struct drm_i915_private *dev_priv = to_i915(dev);
4043 u16 iir, new_iir; 3959 u16 iir, new_iir;
4044 u32 pipe_stats[2]; 3960 u32 pipe_stats[2];
4045 int pipe; 3961 int pipe;
@@ -4089,15 +4005,15 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4089 4005
4090 for_each_pipe(dev_priv, pipe) { 4006 for_each_pipe(dev_priv, pipe) {
4091 int plane = pipe; 4007 int plane = pipe;
4092 if (HAS_FBC(dev)) 4008 if (HAS_FBC(dev_priv))
4093 plane = !plane; 4009 plane = !plane;
4094 4010
4095 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && 4011 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4096 i8xx_handle_vblank(dev, plane, pipe, iir)) 4012 i8xx_handle_vblank(dev_priv, plane, pipe, iir))
4097 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); 4013 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4098 4014
4099 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 4015 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4100 i9xx_pipe_crc_irq_handler(dev, pipe); 4016 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4101 4017
4102 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 4018 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4103 intel_cpu_fifo_underrun_irq_handler(dev_priv, 4019 intel_cpu_fifo_underrun_irq_handler(dev_priv,
@@ -4116,7 +4032,7 @@ out:
4116 4032
4117static void i8xx_irq_uninstall(struct drm_device * dev) 4033static void i8xx_irq_uninstall(struct drm_device * dev)
4118{ 4034{
4119 struct drm_i915_private *dev_priv = dev->dev_private; 4035 struct drm_i915_private *dev_priv = to_i915(dev);
4120 int pipe; 4036 int pipe;
4121 4037
4122 for_each_pipe(dev_priv, pipe) { 4038 for_each_pipe(dev_priv, pipe) {
@@ -4131,7 +4047,7 @@ static void i8xx_irq_uninstall(struct drm_device * dev)
4131 4047
4132static void i915_irq_preinstall(struct drm_device * dev) 4048static void i915_irq_preinstall(struct drm_device * dev)
4133{ 4049{
4134 struct drm_i915_private *dev_priv = dev->dev_private; 4050 struct drm_i915_private *dev_priv = to_i915(dev);
4135 int pipe; 4051 int pipe;
4136 4052
4137 if (I915_HAS_HOTPLUG(dev)) { 4053 if (I915_HAS_HOTPLUG(dev)) {
@@ -4149,7 +4065,7 @@ static void i915_irq_preinstall(struct drm_device * dev)
4149 4065
4150static int i915_irq_postinstall(struct drm_device *dev) 4066static int i915_irq_postinstall(struct drm_device *dev)
4151{ 4067{
4152 struct drm_i915_private *dev_priv = dev->dev_private; 4068 struct drm_i915_private *dev_priv = to_i915(dev);
4153 u32 enable_mask; 4069 u32 enable_mask;
4154 4070
4155 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 4071 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
@@ -4182,7 +4098,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
4182 I915_WRITE(IER, enable_mask); 4098 I915_WRITE(IER, enable_mask);
4183 POSTING_READ(IER); 4099 POSTING_READ(IER);
4184 4100
4185 i915_enable_asle_pipestat(dev); 4101 i915_enable_asle_pipestat(dev_priv);
4186 4102
4187 /* Interrupt setup is already guaranteed to be single-threaded, this is 4103 /* Interrupt setup is already guaranteed to be single-threaded, this is
4188 * just to make the assert_spin_locked check happy. */ 4104 * just to make the assert_spin_locked check happy. */
@@ -4197,13 +4113,12 @@ static int i915_irq_postinstall(struct drm_device *dev)
4197/* 4113/*
4198 * Returns true when a page flip has completed. 4114 * Returns true when a page flip has completed.
4199 */ 4115 */
4200static bool i915_handle_vblank(struct drm_device *dev, 4116static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
4201 int plane, int pipe, u32 iir) 4117 int plane, int pipe, u32 iir)
4202{ 4118{
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); 4119 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4205 4120
4206 if (!intel_pipe_handle_vblank(dev, pipe)) 4121 if (!intel_pipe_handle_vblank(dev_priv, pipe))
4207 return false; 4122 return false;
4208 4123
4209 if ((iir & flip_pending) == 0) 4124 if ((iir & flip_pending) == 0)
@@ -4218,19 +4133,18 @@ static bool i915_handle_vblank(struct drm_device *dev,
4218 if (I915_READ(ISR) & flip_pending) 4133 if (I915_READ(ISR) & flip_pending)
4219 goto check_page_flip; 4134 goto check_page_flip;
4220 4135
4221 intel_prepare_page_flip(dev, plane); 4136 intel_finish_page_flip_cs(dev_priv, pipe);
4222 intel_finish_page_flip(dev, pipe);
4223 return true; 4137 return true;
4224 4138
4225check_page_flip: 4139check_page_flip:
4226 intel_check_page_flip(dev, pipe); 4140 intel_check_page_flip(dev_priv, pipe);
4227 return false; 4141 return false;
4228} 4142}
4229 4143
4230static irqreturn_t i915_irq_handler(int irq, void *arg) 4144static irqreturn_t i915_irq_handler(int irq, void *arg)
4231{ 4145{
4232 struct drm_device *dev = arg; 4146 struct drm_device *dev = arg;
4233 struct drm_i915_private *dev_priv = dev->dev_private; 4147 struct drm_i915_private *dev_priv = to_i915(dev);
4234 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; 4148 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4235 u32 flip_mask = 4149 u32 flip_mask =
4236 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 4150 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
@@ -4273,11 +4187,11 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
4273 break; 4187 break;
4274 4188
4275 /* Consume port. Then clear IIR or we'll miss events */ 4189 /* Consume port. Then clear IIR or we'll miss events */
4276 if (I915_HAS_HOTPLUG(dev) && 4190 if (I915_HAS_HOTPLUG(dev_priv) &&
4277 iir & I915_DISPLAY_PORT_INTERRUPT) { 4191 iir & I915_DISPLAY_PORT_INTERRUPT) {
4278 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv); 4192 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4279 if (hotplug_status) 4193 if (hotplug_status)
4280 i9xx_hpd_irq_handler(dev, hotplug_status); 4194 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4281 } 4195 }
4282 4196
4283 I915_WRITE(IIR, iir & ~flip_mask); 4197 I915_WRITE(IIR, iir & ~flip_mask);
@@ -4288,18 +4202,18 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
4288 4202
4289 for_each_pipe(dev_priv, pipe) { 4203 for_each_pipe(dev_priv, pipe) {
4290 int plane = pipe; 4204 int plane = pipe;
4291 if (HAS_FBC(dev)) 4205 if (HAS_FBC(dev_priv))
4292 plane = !plane; 4206 plane = !plane;
4293 4207
4294 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && 4208 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4295 i915_handle_vblank(dev, plane, pipe, iir)) 4209 i915_handle_vblank(dev_priv, plane, pipe, iir))
4296 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); 4210 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4297 4211
4298 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 4212 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4299 blc_event = true; 4213 blc_event = true;
4300 4214
4301 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 4215 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4302 i9xx_pipe_crc_irq_handler(dev, pipe); 4216 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4303 4217
4304 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 4218 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4305 intel_cpu_fifo_underrun_irq_handler(dev_priv, 4219 intel_cpu_fifo_underrun_irq_handler(dev_priv,
@@ -4307,7 +4221,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
4307 } 4221 }
4308 4222
4309 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 4223 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4310 intel_opregion_asle_intr(dev); 4224 intel_opregion_asle_intr(dev_priv);
4311 4225
4312 /* With MSI, interrupts are only generated when iir 4226 /* With MSI, interrupts are only generated when iir
4313 * transitions from zero to nonzero. If another bit got 4227 * transitions from zero to nonzero. If another bit got
@@ -4335,7 +4249,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
4335 4249
4336static void i915_irq_uninstall(struct drm_device * dev) 4250static void i915_irq_uninstall(struct drm_device * dev)
4337{ 4251{
4338 struct drm_i915_private *dev_priv = dev->dev_private; 4252 struct drm_i915_private *dev_priv = to_i915(dev);
4339 int pipe; 4253 int pipe;
4340 4254
4341 if (I915_HAS_HOTPLUG(dev)) { 4255 if (I915_HAS_HOTPLUG(dev)) {
@@ -4357,7 +4271,7 @@ static void i915_irq_uninstall(struct drm_device * dev)
4357 4271
4358static void i965_irq_preinstall(struct drm_device * dev) 4272static void i965_irq_preinstall(struct drm_device * dev)
4359{ 4273{
4360 struct drm_i915_private *dev_priv = dev->dev_private; 4274 struct drm_i915_private *dev_priv = to_i915(dev);
4361 int pipe; 4275 int pipe;
4362 4276
4363 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); 4277 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
@@ -4373,7 +4287,7 @@ static void i965_irq_preinstall(struct drm_device * dev)
4373 4287
4374static int i965_irq_postinstall(struct drm_device *dev) 4288static int i965_irq_postinstall(struct drm_device *dev)
4375{ 4289{
4376 struct drm_i915_private *dev_priv = dev->dev_private; 4290 struct drm_i915_private *dev_priv = to_i915(dev);
4377 u32 enable_mask; 4291 u32 enable_mask;
4378 u32 error_mask; 4292 u32 error_mask;
4379 4293
@@ -4391,7 +4305,7 @@ static int i965_irq_postinstall(struct drm_device *dev)
4391 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); 4305 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4392 enable_mask |= I915_USER_INTERRUPT; 4306 enable_mask |= I915_USER_INTERRUPT;
4393 4307
4394 if (IS_G4X(dev)) 4308 if (IS_G4X(dev_priv))
4395 enable_mask |= I915_BSD_USER_INTERRUPT; 4309 enable_mask |= I915_BSD_USER_INTERRUPT;
4396 4310
4397 /* Interrupt setup is already guaranteed to be single-threaded, this is 4311 /* Interrupt setup is already guaranteed to be single-threaded, this is
@@ -4406,7 +4320,7 @@ static int i965_irq_postinstall(struct drm_device *dev)
4406 * Enable some error detection, note the instruction error mask 4320 * Enable some error detection, note the instruction error mask
4407 * bit is reserved, so we leave it masked. 4321 * bit is reserved, so we leave it masked.
4408 */ 4322 */
4409 if (IS_G4X(dev)) { 4323 if (IS_G4X(dev_priv)) {
4410 error_mask = ~(GM45_ERROR_PAGE_TABLE | 4324 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4411 GM45_ERROR_MEM_PRIV | 4325 GM45_ERROR_MEM_PRIV |
4412 GM45_ERROR_CP_PRIV | 4326 GM45_ERROR_CP_PRIV |
@@ -4424,26 +4338,25 @@ static int i965_irq_postinstall(struct drm_device *dev)
4424 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); 4338 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4425 POSTING_READ(PORT_HOTPLUG_EN); 4339 POSTING_READ(PORT_HOTPLUG_EN);
4426 4340
4427 i915_enable_asle_pipestat(dev); 4341 i915_enable_asle_pipestat(dev_priv);
4428 4342
4429 return 0; 4343 return 0;
4430} 4344}
4431 4345
4432static void i915_hpd_irq_setup(struct drm_device *dev) 4346static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4433{ 4347{
4434 struct drm_i915_private *dev_priv = dev->dev_private;
4435 u32 hotplug_en; 4348 u32 hotplug_en;
4436 4349
4437 assert_spin_locked(&dev_priv->irq_lock); 4350 assert_spin_locked(&dev_priv->irq_lock);
4438 4351
4439 /* Note HDMI and DP share hotplug bits */ 4352 /* Note HDMI and DP share hotplug bits */
4440 /* enable bits are the same for all generations */ 4353 /* enable bits are the same for all generations */
4441 hotplug_en = intel_hpd_enabled_irqs(dev, hpd_mask_i915); 4354 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4442 /* Programming the CRT detection parameters tends 4355 /* Programming the CRT detection parameters tends
4443 to generate a spurious hotplug event about three 4356 to generate a spurious hotplug event about three
4444 seconds later. So just do it once. 4357 seconds later. So just do it once.
4445 */ 4358 */
4446 if (IS_G4X(dev)) 4359 if (IS_G4X(dev_priv))
4447 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 4360 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4448 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 4361 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4449 4362
@@ -4458,7 +4371,7 @@ static void i915_hpd_irq_setup(struct drm_device *dev)
4458static irqreturn_t i965_irq_handler(int irq, void *arg) 4371static irqreturn_t i965_irq_handler(int irq, void *arg)
4459{ 4372{
4460 struct drm_device *dev = arg; 4373 struct drm_device *dev = arg;
4461 struct drm_i915_private *dev_priv = dev->dev_private; 4374 struct drm_i915_private *dev_priv = to_i915(dev);
4462 u32 iir, new_iir; 4375 u32 iir, new_iir;
4463 u32 pipe_stats[I915_MAX_PIPES]; 4376 u32 pipe_stats[I915_MAX_PIPES];
4464 int ret = IRQ_NONE, pipe; 4377 int ret = IRQ_NONE, pipe;
@@ -4510,7 +4423,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
4510 if (iir & I915_DISPLAY_PORT_INTERRUPT) { 4423 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4511 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv); 4424 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4512 if (hotplug_status) 4425 if (hotplug_status)
4513 i9xx_hpd_irq_handler(dev, hotplug_status); 4426 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4514 } 4427 }
4515 4428
4516 I915_WRITE(IIR, iir & ~flip_mask); 4429 I915_WRITE(IIR, iir & ~flip_mask);
@@ -4523,24 +4436,24 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
4523 4436
4524 for_each_pipe(dev_priv, pipe) { 4437 for_each_pipe(dev_priv, pipe) {
4525 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && 4438 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4526 i915_handle_vblank(dev, pipe, pipe, iir)) 4439 i915_handle_vblank(dev_priv, pipe, pipe, iir))
4527 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); 4440 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4528 4441
4529 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 4442 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4530 blc_event = true; 4443 blc_event = true;
4531 4444
4532 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 4445 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4533 i9xx_pipe_crc_irq_handler(dev, pipe); 4446 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4534 4447
4535 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 4448 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4536 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 4449 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4537 } 4450 }
4538 4451
4539 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 4452 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4540 intel_opregion_asle_intr(dev); 4453 intel_opregion_asle_intr(dev_priv);
4541 4454
4542 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 4455 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4543 gmbus_irq_handler(dev); 4456 gmbus_irq_handler(dev_priv);
4544 4457
4545 /* With MSI, interrupts are only generated when iir 4458 /* With MSI, interrupts are only generated when iir
4546 * transitions from zero to nonzero. If another bit got 4459 * transitions from zero to nonzero. If another bit got
@@ -4567,7 +4480,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
4567 4480
4568static void i965_irq_uninstall(struct drm_device * dev) 4481static void i965_irq_uninstall(struct drm_device * dev)
4569{ 4482{
4570 struct drm_i915_private *dev_priv = dev->dev_private; 4483 struct drm_i915_private *dev_priv = to_i915(dev);
4571 int pipe; 4484 int pipe;
4572 4485
4573 if (!dev_priv) 4486 if (!dev_priv)
@@ -4597,7 +4510,7 @@ static void i965_irq_uninstall(struct drm_device * dev)
4597 */ 4510 */
4598void intel_irq_init(struct drm_i915_private *dev_priv) 4511void intel_irq_init(struct drm_i915_private *dev_priv)
4599{ 4512{
4600 struct drm_device *dev = dev_priv->dev; 4513 struct drm_device *dev = &dev_priv->drm;
4601 4514
4602 intel_hpd_init_work(dev_priv); 4515 intel_hpd_init_work(dev_priv);
4603 4516
@@ -4611,6 +4524,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
4611 else 4524 else
4612 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; 4525 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4613 4526
4527 dev_priv->rps.pm_intr_keep = 0;
4528
4529 /*
4530 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4531 * if GEN6_PM_UP_EI_EXPIRED is masked.
4532 *
4533 * TODO: verify if this can be reproduced on VLV,CHV.
4534 */
4535 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4536 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4537
4538 if (INTEL_INFO(dev_priv)->gen >= 8)
4539 dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
4540
4614 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work, 4541 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4615 i915_hangcheck_elapsed); 4542 i915_hangcheck_elapsed);
4616 4543
@@ -4674,12 +4601,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
4674 dev->driver->disable_vblank = ironlake_disable_vblank; 4601 dev->driver->disable_vblank = ironlake_disable_vblank;
4675 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; 4602 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4676 } else { 4603 } else {
4677 if (INTEL_INFO(dev_priv)->gen == 2) { 4604 if (IS_GEN2(dev_priv)) {
4678 dev->driver->irq_preinstall = i8xx_irq_preinstall; 4605 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4679 dev->driver->irq_postinstall = i8xx_irq_postinstall; 4606 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4680 dev->driver->irq_handler = i8xx_irq_handler; 4607 dev->driver->irq_handler = i8xx_irq_handler;
4681 dev->driver->irq_uninstall = i8xx_irq_uninstall; 4608 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4682 } else if (INTEL_INFO(dev_priv)->gen == 3) { 4609 } else if (IS_GEN3(dev_priv)) {
4683 dev->driver->irq_preinstall = i915_irq_preinstall; 4610 dev->driver->irq_preinstall = i915_irq_preinstall;
4684 dev->driver->irq_postinstall = i915_irq_postinstall; 4611 dev->driver->irq_postinstall = i915_irq_postinstall;
4685 dev->driver->irq_uninstall = i915_irq_uninstall; 4612 dev->driver->irq_uninstall = i915_irq_uninstall;
@@ -4717,7 +4644,7 @@ int intel_irq_install(struct drm_i915_private *dev_priv)
4717 */ 4644 */
4718 dev_priv->pm.irqs_enabled = true; 4645 dev_priv->pm.irqs_enabled = true;
4719 4646
4720 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); 4647 return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4721} 4648}
4722 4649
4723/** 4650/**
@@ -4729,7 +4656,7 @@ int intel_irq_install(struct drm_i915_private *dev_priv)
4729 */ 4656 */
4730void intel_irq_uninstall(struct drm_i915_private *dev_priv) 4657void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4731{ 4658{
4732 drm_irq_uninstall(dev_priv->dev); 4659 drm_irq_uninstall(&dev_priv->drm);
4733 intel_hpd_cancel_work(dev_priv); 4660 intel_hpd_cancel_work(dev_priv);
4734 dev_priv->pm.irqs_enabled = false; 4661 dev_priv->pm.irqs_enabled = false;
4735} 4662}
@@ -4743,9 +4670,9 @@ void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4743 */ 4670 */
4744void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) 4671void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4745{ 4672{
4746 dev_priv->dev->driver->irq_uninstall(dev_priv->dev); 4673 dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4747 dev_priv->pm.irqs_enabled = false; 4674 dev_priv->pm.irqs_enabled = false;
4748 synchronize_irq(dev_priv->dev->irq); 4675 synchronize_irq(dev_priv->drm.irq);
4749} 4676}
4750 4677
4751/** 4678/**
@@ -4758,6 +4685,6 @@ void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4758void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) 4685void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4759{ 4686{
4760 dev_priv->pm.irqs_enabled = true; 4687 dev_priv->pm.irqs_enabled = true;
4761 dev_priv->dev->driver->irq_preinstall(dev_priv->dev); 4688 dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4762 dev_priv->dev->driver->irq_postinstall(dev_priv->dev); 4689 dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
4763} 4690}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 14:04:29 -0500