diff options
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_debug.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_debug.c | 92 |
1 files changed, 22 insertions, 70 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_debug.c b/drivers/gpu/drm/i915/i915_gem_debug.c index f462d1b51d97..17299d04189f 100644 --- a/drivers/gpu/drm/i915/i915_gem_debug.c +++ b/drivers/gpu/drm/i915/i915_gem_debug.c | |||
@@ -34,82 +34,34 @@ int | |||
34 | i915_verify_lists(struct drm_device *dev) | 34 | i915_verify_lists(struct drm_device *dev) |
35 | { | 35 | { |
36 | static int warned; | 36 | static int warned; |
37 | struct drm_i915_private *dev_priv = dev->dev_private; | 37 | struct drm_i915_private *dev_priv = to_i915(dev); |
38 | struct drm_i915_gem_object *obj; | 38 | struct drm_i915_gem_object *obj; |
39 | struct intel_engine_cs *ring; | ||
39 | int err = 0; | 40 | int err = 0; |
41 | int i; | ||
40 | 42 | ||
41 | if (warned) | 43 | if (warned) |
42 | return 0; | 44 | return 0; |
43 | 45 | ||
44 | list_for_each_entry(obj, &dev_priv->render_ring.active_list, list) { | 46 | for_each_ring(ring, dev_priv, i) { |
45 | if (obj->base.dev != dev || | 47 | list_for_each_entry(obj, &ring->active_list, ring_list[ring->id]) { |
46 | !atomic_read(&obj->base.refcount.refcount)) { | 48 | if (obj->base.dev != dev || |
47 | DRM_ERROR("freed render active %p\n", obj); | 49 | !atomic_read(&obj->base.refcount.refcount)) { |
48 | err++; | 50 | DRM_ERROR("%s: freed active obj %p\n", |
49 | break; | 51 | ring->name, obj); |
50 | } else if (!obj->active || | 52 | err++; |
51 | (obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) { | 53 | break; |
52 | DRM_ERROR("invalid render active %p (a %d r %x)\n", | 54 | } else if (!obj->active || |
53 | obj, | 55 | obj->last_read_req[ring->id] == NULL) { |
54 | obj->active, | 56 | DRM_ERROR("%s: invalid active obj %p\n", |
55 | obj->base.read_domains); | 57 | ring->name, obj); |
56 | err++; | 58 | err++; |
57 | } else if (obj->base.write_domain && list_empty(&obj->gpu_write_list)) { | 59 | } else if (obj->base.write_domain) { |
58 | DRM_ERROR("invalid render active %p (w %x, gwl %d)\n", | 60 | DRM_ERROR("%s: invalid write obj %p (w %x)\n", |
59 | obj, | 61 | ring->name, |
60 | obj->base.write_domain, | 62 | obj, obj->base.write_domain); |
61 | !list_empty(&obj->gpu_write_list)); | 63 | err++; |
62 | err++; | 64 | } |
63 | } | ||
64 | } | ||
65 | |||
66 | list_for_each_entry(obj, &dev_priv->mm.flushing_list, list) { | ||
67 | if (obj->base.dev != dev || | ||
68 | !atomic_read(&obj->base.refcount.refcount)) { | ||
69 | DRM_ERROR("freed flushing %p\n", obj); | ||
70 | err++; | ||
71 | break; | ||
72 | } else if (!obj->active || | ||
73 | (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0 || | ||
74 | list_empty(&obj->gpu_write_list)) { | ||
75 | DRM_ERROR("invalid flushing %p (a %d w %x gwl %d)\n", | ||
76 | obj, | ||
77 | obj->active, | ||
78 | obj->base.write_domain, | ||
79 | !list_empty(&obj->gpu_write_list)); | ||
80 | err++; | ||
81 | } | ||
82 | } | ||
83 | |||
84 | list_for_each_entry(obj, &dev_priv->mm.gpu_write_list, gpu_write_list) { | ||
85 | if (obj->base.dev != dev || | ||
86 | !atomic_read(&obj->base.refcount.refcount)) { | ||
87 | DRM_ERROR("freed gpu write %p\n", obj); | ||
88 | err++; | ||
89 | break; | ||
90 | } else if (!obj->active || | ||
91 | (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) { | ||
92 | DRM_ERROR("invalid gpu write %p (a %d w %x)\n", | ||
93 | obj, | ||
94 | obj->active, | ||
95 | obj->base.write_domain); | ||
96 | err++; | ||
97 | } | ||
98 | } | ||
99 | |||
100 | list_for_each_entry(obj, &i915_gtt_vm->inactive_list, list) { | ||
101 | if (obj->base.dev != dev || | ||
102 | !atomic_read(&obj->base.refcount.refcount)) { | ||
103 | DRM_ERROR("freed inactive %p\n", obj); | ||
104 | err++; | ||
105 | break; | ||
106 | } else if (obj->pin_count || obj->active || | ||
107 | (obj->base.write_domain & I915_GEM_GPU_DOMAINS)) { | ||
108 | DRM_ERROR("invalid inactive %p (p %d a %d w %x)\n", | ||
109 | obj, | ||
110 | obj->pin_count, obj->active, | ||
111 | obj->base.write_domain); | ||
112 | err++; | ||
113 | } | 65 | } |
114 | } | 66 | } |
115 | 67 | ||