1 files changed, 42 insertions, 16 deletions

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 4c478b38e420..3f907701ef4d 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -687,7 +687,6 @@ static void reset_prepare_engine(struct intel_engine_cs *engine)
          * written to the powercontext is undefined and so we may lose
          * GPU state upon resume, i.e. fail to restart after a reset.
          */
-        intel_engine_pm_get(engine);
         intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
         engine->reset.prepare(engine);
 }
@@ -718,16 +717,21 @@ static void revoke_mmaps(struct drm_i915_private *i915)
         }
 }
 
-static void reset_prepare(struct drm_i915_private *i915)
+static intel_engine_mask_t reset_prepare(struct drm_i915_private *i915)
 {
         struct intel_engine_cs *engine;
+        intel_engine_mask_t awake = 0;
         enum intel_engine_id id;
 
-        intel_gt_pm_get(i915);
-        for_each_engine(engine, i915, id)
+        for_each_engine(engine, i915, id) {
+                if (intel_engine_pm_get_if_awake(engine))
+                        awake |= engine->mask;
                 reset_prepare_engine(engine);
+        }
 
         intel_uc_reset_prepare(i915);
+
+        return awake;
 }
 
 static void gt_revoke(struct drm_i915_private *i915)
@@ -761,20 +765,22 @@ static int gt_reset(struct drm_i915_private *i915,
 static void reset_finish_engine(struct intel_engine_cs *engine)
 {
         engine->reset.finish(engine);
-        intel_engine_pm_put(engine);
         intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
+
+        intel_engine_signal_breadcrumbs(engine);
 }
 
-static void reset_finish(struct drm_i915_private *i915)
+static void reset_finish(struct drm_i915_private *i915,
+                         intel_engine_mask_t awake)
 {
         struct intel_engine_cs *engine;
         enum intel_engine_id id;
 
         for_each_engine(engine, i915, id) {
                 reset_finish_engine(engine);
-                intel_engine_signal_breadcrumbs(engine);
+                if (awake & engine->mask)
+                        intel_engine_pm_put(engine);
         }
-        intel_gt_pm_put(i915);
 }
 
 static void nop_submit_request(struct i915_request *request)
@@ -798,6 +804,7 @@ static void __i915_gem_set_wedged(struct drm_i915_private *i915)
 {
         struct i915_gpu_error *error = &i915->gpu_error;
         struct intel_engine_cs *engine;
+        intel_engine_mask_t awake;
         enum intel_engine_id id;
 
         if (test_bit(I915_WEDGED, &error->flags))
@@ -817,7 +824,7 @@ static void __i915_gem_set_wedged(struct drm_i915_private *i915)
          * rolling the global seqno forward (since this would complete requests
          * for which we haven't set the fence error to EIO yet).
          */
-        reset_prepare(i915);
+        awake = reset_prepare(i915);
 
         /* Even if the GPU reset fails, it should still stop the engines */
         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
@@ -841,7 +848,7 @@ static void __i915_gem_set_wedged(struct drm_i915_private *i915)
         for_each_engine(engine, i915, id)
                 engine->cancel_requests(engine);
 
-        reset_finish(i915);
+        reset_finish(i915, awake);
 
         GEM_TRACE("end\n");
 }
@@ -951,6 +958,21 @@ static int do_reset(struct drm_i915_private *i915,
         return gt_reset(i915, stalled_mask);
 }
 
+static int resume(struct drm_i915_private *i915)
+{
+        struct intel_engine_cs *engine;
+        enum intel_engine_id id;
+        int ret;
+
+        for_each_engine(engine, i915, id) {
+                ret = engine->resume(engine);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
+}
+
 /**
  * i915_reset - reset chip after a hang
  * @i915: #drm_i915_private to reset
@@ -973,6 +995,7 @@ void i915_reset(struct drm_i915_private *i915,
                 const char *reason)
 {
         struct i915_gpu_error *error = &i915->gpu_error;
+        intel_engine_mask_t awake;
         int ret;
 
         GEM_TRACE("flags=%lx\n", error->flags);
@@ -989,7 +1012,7 @@ void i915_reset(struct drm_i915_private *i915,
                 dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
         error->reset_count++;
 
-        reset_prepare(i915);
+        awake = reset_prepare(i915);
 
         if (!intel_has_gpu_reset(i915)) {
                 if (i915_modparams.reset)
@@ -1024,13 +1047,17 @@ void i915_reset(struct drm_i915_private *i915,
         if (ret) {
                 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
                           ret);
-                goto error;
+                goto taint;
         }
 
+        ret = resume(i915);
+        if (ret)
+                goto taint;
+
         i915_queue_hangcheck(i915);
 
 finish:
-        reset_finish(i915);
+        reset_finish(i915, awake);
 unlock:
         mutex_unlock(&error->wedge_mutex);
         return;
@@ -1081,7 +1108,7 @@ int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
         GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
 
-        if (!intel_wakeref_active(&engine->wakeref))
+        if (!intel_engine_pm_get_if_awake(engine))
                 return 0;
 
         reset_prepare_engine(engine);
@@ -1116,12 +1143,11 @@ int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
          * process to program RING_MODE, HWSP and re-enable submission.
          */
         ret = engine->resume(engine);
-        if (ret)
-                goto out;
 
 out:
         intel_engine_cancel_stop_cs(engine);
         reset_finish_engine(engine);
+        intel_engine_pm_put(engine);
         return ret;
 }