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-rw-r--r--drivers/gpu/drm/arm/malidp_hw.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h
index 0d7f9ea0ade8..3ab133d49bba 100644
--- a/drivers/gpu/drm/arm/malidp_hw.h
+++ b/drivers/gpu/drm/arm/malidp_hw.h
@@ -36,6 +36,12 @@ enum {
36 SE_MEMWRITE = BIT(5), 36 SE_MEMWRITE = BIT(5),
37}; 37};
38 38
39enum rotation_features {
40 ROTATE_NONE, /* does not support rotation at all */
41 ROTATE_ANY, /* supports rotation on any buffers */
42 ROTATE_COMPRESSED, /* supports rotation only on compressed buffers */
43};
44
39struct malidp_format_id { 45struct malidp_format_id {
40 u32 format; /* DRM fourcc */ 46 u32 format; /* DRM fourcc */
41 u8 layer; /* bitmask of layers supporting it */ 47 u8 layer; /* bitmask of layers supporting it */
@@ -63,6 +69,7 @@ struct malidp_layer {
63 u16 stride_offset; /* offset to the first stride register. */ 69 u16 stride_offset; /* offset to the first stride register. */
64 s16 yuv2rgb_offset; /* offset to the YUV->RGB matrix entries */ 70 s16 yuv2rgb_offset; /* offset to the YUV->RGB matrix entries */
65 u16 mmu_ctrl_offset; /* offset to the MMU control register */ 71 u16 mmu_ctrl_offset; /* offset to the MMU control register */
72 enum rotation_features rot; /* type of rotation supported */
66}; 73};
67 74
68enum malidp_scaling_coeff_set { 75enum malidp_scaling_coeff_set {