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-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c17
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c28
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c15
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_process.c70
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_topology.c2
-rw-r--r--drivers/gpu/drm/amd/include/atombios.h72
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c6
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h1
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c256
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h3
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c6
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c18
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c43
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h32
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c1
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h16
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c91
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h1
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h1
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu74.h75
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h42
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c50
31 files changed, 654 insertions, 237 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 01c36b8d6222..e055d5be1c3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -799,7 +799,6 @@ struct amdgpu_ring {
799 unsigned cond_exe_offs; 799 unsigned cond_exe_offs;
800 u64 cond_exe_gpu_addr; 800 u64 cond_exe_gpu_addr;
801 volatile u32 *cond_exe_cpu_addr; 801 volatile u32 *cond_exe_cpu_addr;
802 int vmid;
803}; 802};
804 803
805/* 804/*
@@ -937,8 +936,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
937 unsigned vm_id, uint64_t pd_addr, 936 unsigned vm_id, uint64_t pd_addr,
938 uint32_t gds_base, uint32_t gds_size, 937 uint32_t gds_base, uint32_t gds_size,
939 uint32_t gws_base, uint32_t gws_size, 938 uint32_t gws_base, uint32_t gws_size,
940 uint32_t oa_base, uint32_t oa_size, 939 uint32_t oa_base, uint32_t oa_size);
941 bool vmid_switch);
942void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); 940void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
943uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 941uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
944int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 942int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
@@ -1822,6 +1820,8 @@ struct amdgpu_asic_funcs {
1822 /* MM block clocks */ 1820 /* MM block clocks */
1823 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1821 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1824 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1822 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1823 /* query virtual capabilities */
1824 u32 (*get_virtual_caps)(struct amdgpu_device *adev);
1825}; 1825};
1826 1826
1827/* 1827/*
@@ -1916,8 +1916,12 @@ void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
1916 1916
1917 1917
1918/* GPU virtualization */ 1918/* GPU virtualization */
1919#define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0)
1920#define AMDGPU_VIRT_CAPS_IS_VF (1 << 1)
1919struct amdgpu_virtualization { 1921struct amdgpu_virtualization {
1920 bool supports_sr_iov; 1922 bool supports_sr_iov;
1923 bool is_virtual;
1924 u32 caps;
1921}; 1925};
1922 1926
1923/* 1927/*
@@ -2206,6 +2210,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2206#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2210#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2207#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2211#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2208#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2212#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2213#define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev)))
2209#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 2214#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2210#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2215#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2211#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 2216#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 8943099eb135..cf6f49fc1c75 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -909,7 +909,7 @@ static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
909 struct cgs_acpi_method_argument *argument = NULL; 909 struct cgs_acpi_method_argument *argument = NULL;
910 uint32_t i, count; 910 uint32_t i, count;
911 acpi_status status; 911 acpi_status status;
912 int result; 912 int result = 0;
913 uint32_t func_no = 0xFFFFFFFF; 913 uint32_t func_no = 0xFFFFFFFF;
914 914
915 handle = ACPI_HANDLE(&adev->pdev->dev); 915 handle = ACPI_HANDLE(&adev->pdev->dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 964f31404f17..6e920086af46 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1385,6 +1385,15 @@ static int amdgpu_resume(struct amdgpu_device *adev)
1385 return 0; 1385 return 0;
1386} 1386}
1387 1387
1388static bool amdgpu_device_is_virtual(void)
1389{
1390#ifdef CONFIG_X86
1391 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
1392#else
1393 return false;
1394#endif
1395}
1396
1388/** 1397/**
1389 * amdgpu_device_init - initialize the driver 1398 * amdgpu_device_init - initialize the driver
1390 * 1399 *
@@ -1519,8 +1528,14 @@ int amdgpu_device_init(struct amdgpu_device *adev,
1519 adev->virtualization.supports_sr_iov = 1528 adev->virtualization.supports_sr_iov =
1520 amdgpu_atombios_has_gpu_virtualization_table(adev); 1529 amdgpu_atombios_has_gpu_virtualization_table(adev);
1521 1530
1531 /* Check if we are executing in a virtualized environment */
1532 adev->virtualization.is_virtual = amdgpu_device_is_virtual();
1533 adev->virtualization.caps = amdgpu_asic_get_virtual_caps(adev);
1534
1522 /* Post card if necessary */ 1535 /* Post card if necessary */
1523 if (!amdgpu_card_posted(adev)) { 1536 if (!amdgpu_card_posted(adev) ||
1537 (adev->virtualization.is_virtual &&
1538 !(adev->virtualization.caps & AMDGPU_VIRT_CAPS_SRIOV_EN))) {
1524 if (!adev->bios) { 1539 if (!adev->bios) {
1525 dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n"); 1540 dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
1526 return -EINVAL; 1541 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 7a0b1e50f293..34e35423b78e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -122,7 +122,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
122 bool skip_preamble, need_ctx_switch; 122 bool skip_preamble, need_ctx_switch;
123 unsigned patch_offset = ~0; 123 unsigned patch_offset = ~0;
124 struct amdgpu_vm *vm; 124 struct amdgpu_vm *vm;
125 int vmid = 0, old_vmid = ring->vmid;
126 struct fence *hwf; 125 struct fence *hwf;
127 uint64_t ctx; 126 uint64_t ctx;
128 127
@@ -136,11 +135,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
136 if (job) { 135 if (job) {
137 vm = job->vm; 136 vm = job->vm;
138 ctx = job->ctx; 137 ctx = job->ctx;
139 vmid = job->vm_id;
140 } else { 138 } else {
141 vm = NULL; 139 vm = NULL;
142 ctx = 0; 140 ctx = 0;
143 vmid = 0;
144 } 141 }
145 142
146 if (!ring->ready) { 143 if (!ring->ready) {
@@ -166,8 +163,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
166 r = amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr, 163 r = amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr,
167 job->gds_base, job->gds_size, 164 job->gds_base, job->gds_size,
168 job->gws_base, job->gws_size, 165 job->gws_base, job->gws_size,
169 job->oa_base, job->oa_size, 166 job->oa_base, job->oa_size);
170 (ring->current_ctx == ctx) && (old_vmid != vmid));
171 if (r) { 167 if (r) {
172 amdgpu_ring_undo(ring); 168 amdgpu_ring_undo(ring);
173 return r; 169 return r;
@@ -184,6 +180,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
184 need_ctx_switch = ring->current_ctx != ctx; 180 need_ctx_switch = ring->current_ctx != ctx;
185 for (i = 0; i < num_ibs; ++i) { 181 for (i = 0; i < num_ibs; ++i) {
186 ib = &ibs[i]; 182 ib = &ibs[i];
183
187 /* drop preamble IBs if we don't have a context switch */ 184 /* drop preamble IBs if we don't have a context switch */
188 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble) 185 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble)
189 continue; 186 continue;
@@ -191,7 +188,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
191 amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0, 188 amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
192 need_ctx_switch); 189 need_ctx_switch);
193 need_ctx_switch = false; 190 need_ctx_switch = false;
194 ring->vmid = vmid;
195 } 191 }
196 192
197 if (ring->funcs->emit_hdp_invalidate) 193 if (ring->funcs->emit_hdp_invalidate)
@@ -202,7 +198,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
202 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 198 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
203 if (job && job->vm_id) 199 if (job && job->vm_id)
204 amdgpu_vm_reset_id(adev, job->vm_id); 200 amdgpu_vm_reset_id(adev, job->vm_id);
205 ring->vmid = old_vmid;
206 amdgpu_ring_undo(ring); 201 amdgpu_ring_undo(ring);
207 return r; 202 return r;
208 } 203 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 40a23704a981..d851ea15059f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -447,7 +447,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
447 dev_info.max_memory_clock = adev->pm.default_mclk * 10; 447 dev_info.max_memory_clock = adev->pm.default_mclk * 10;
448 } 448 }
449 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 449 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
450 dev_info.num_rb_pipes = adev->gfx.config.num_rbs; 450 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
451 adev->gfx.config.max_shader_engines;
451 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 452 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
452 dev_info._pad = 0; 453 dev_info._pad = 0;
453 dev_info.ids_flags = 0; 454 dev_info.ids_flags = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 589b36e8c5cf..0e13d80d2a95 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -270,30 +270,28 @@ static ssize_t amdgpu_set_pp_force_state(struct device *dev,
270 struct drm_device *ddev = dev_get_drvdata(dev); 270 struct drm_device *ddev = dev_get_drvdata(dev);
271 struct amdgpu_device *adev = ddev->dev_private; 271 struct amdgpu_device *adev = ddev->dev_private;
272 enum amd_pm_state_type state = 0; 272 enum amd_pm_state_type state = 0;
273 long idx; 273 unsigned long idx;
274 int ret; 274 int ret;
275 275
276 if (strlen(buf) == 1) 276 if (strlen(buf) == 1)
277 adev->pp_force_state_enabled = false; 277 adev->pp_force_state_enabled = false;
278 else { 278 else if (adev->pp_enabled) {
279 ret = kstrtol(buf, 0, &idx); 279 struct pp_states_info data;
280 280
281 if (ret) { 281 ret = kstrtoul(buf, 0, &idx);
282 if (ret || idx >= ARRAY_SIZE(data.states)) {
282 count = -EINVAL; 283 count = -EINVAL;
283 goto fail; 284 goto fail;
284 } 285 }
285 286
286 if (adev->pp_enabled) { 287 amdgpu_dpm_get_pp_num_states(adev, &data);
287 struct pp_states_info data; 288 state = data.states[idx];
288 amdgpu_dpm_get_pp_num_states(adev, &data); 289 /* only set user selected power states */
289 state = data.states[idx]; 290 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
290 /* only set user selected power states */ 291 state != POWER_STATE_TYPE_DEFAULT) {
291 if (state != POWER_STATE_TYPE_INTERNAL_BOOT && 292 amdgpu_dpm_dispatch_task(adev,
292 state != POWER_STATE_TYPE_DEFAULT) { 293 AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
293 amdgpu_dpm_dispatch_task(adev, 294 adev->pp_force_state_enabled = true;
294 AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
295 adev->pp_force_state_enabled = true;
296 }
297 } 295 }
298 } 296 }
299fail: 297fail:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 62a4c127620f..9f36ed30ba11 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -298,8 +298,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
298 unsigned vm_id, uint64_t pd_addr, 298 unsigned vm_id, uint64_t pd_addr,
299 uint32_t gds_base, uint32_t gds_size, 299 uint32_t gds_base, uint32_t gds_size,
300 uint32_t gws_base, uint32_t gws_size, 300 uint32_t gws_base, uint32_t gws_size,
301 uint32_t oa_base, uint32_t oa_size, 301 uint32_t oa_base, uint32_t oa_size)
302 bool vmid_switch)
303{ 302{
304 struct amdgpu_device *adev = ring->adev; 303 struct amdgpu_device *adev = ring->adev;
305 struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; 304 struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
@@ -313,7 +312,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
313 int r; 312 int r;
314 313
315 if (ring->funcs->emit_pipeline_sync && ( 314 if (ring->funcs->emit_pipeline_sync && (
316 pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed || vmid_switch)) 315 pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed ||
316 ring->type == AMDGPU_RING_TYPE_COMPUTE))
317 amdgpu_ring_emit_pipeline_sync(ring); 317 amdgpu_ring_emit_pipeline_sync(ring);
318 318
319 if (ring->funcs->emit_vm_flush && 319 if (ring->funcs->emit_vm_flush &&
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 07bc795a4ca9..910431808542 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -962,6 +962,12 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
962 return true; 962 return true;
963} 963}
964 964
965static u32 cik_get_virtual_caps(struct amdgpu_device *adev)
966{
967 /* CIK does not support SR-IOV */
968 return 0;
969}
970
965static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = { 971static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
966 {mmGRBM_STATUS, false}, 972 {mmGRBM_STATUS, false},
967 {mmGB_ADDR_CONFIG, false}, 973 {mmGB_ADDR_CONFIG, false},
@@ -2007,6 +2013,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
2007 .get_xclk = &cik_get_xclk, 2013 .get_xclk = &cik_get_xclk,
2008 .set_uvd_clocks = &cik_set_uvd_clocks, 2014 .set_uvd_clocks = &cik_set_uvd_clocks,
2009 .set_vce_clocks = &cik_set_vce_clocks, 2015 .set_vce_clocks = &cik_set_vce_clocks,
2016 .get_virtual_caps = &cik_get_virtual_caps,
2010 /* these should be moved to their own ip modules */ 2017 /* these should be moved to their own ip modules */
2011 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, 2018 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
2012 .wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle, 2019 .wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 8c6ad1e72f02..fc8ff4d3ccf8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4833,7 +4833,7 @@ static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
4833 case 2: 4833 case 2:
4834 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4834 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4835 ring = &adev->gfx.compute_ring[i]; 4835 ring = &adev->gfx.compute_ring[i];
4836 if ((ring->me == me_id) & (ring->pipe == pipe_id)) 4836 if ((ring->me == me_id) && (ring->pipe == pipe_id))
4837 amdgpu_fence_process(ring); 4837 amdgpu_fence_process(ring);
4838 } 4838 }
4839 break; 4839 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 9f6f8669edc3..1a5cbaff1e34 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -297,7 +297,8 @@ static const u32 polaris11_golden_common_all[] =
297static const u32 golden_settings_polaris10_a11[] = 297static const u32 golden_settings_polaris10_a11[] =
298{ 298{
299 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200, 299 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
300 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00006208, 300 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
301 mmCB_HW_CONTROL_2, 0, 0x0f000000,
301 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, 302 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
302 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 303 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
303 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 304 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 2c88d0b66cf3..a65c96029476 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -421,6 +421,20 @@ static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
421 return true; 421 return true;
422} 422}
423 423
424static u32 vi_get_virtual_caps(struct amdgpu_device *adev)
425{
426 u32 caps = 0;
427 u32 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
428
429 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))
430 caps |= AMDGPU_VIRT_CAPS_SRIOV_EN;
431
432 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))
433 caps |= AMDGPU_VIRT_CAPS_IS_VF;
434
435 return caps;
436}
437
424static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = { 438static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
425 {mmGB_MACROTILE_MODE7, true}, 439 {mmGB_MACROTILE_MODE7, true},
426}; 440};
@@ -1118,6 +1132,7 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
1118 .get_xclk = &vi_get_xclk, 1132 .get_xclk = &vi_get_xclk,
1119 .set_uvd_clocks = &vi_set_uvd_clocks, 1133 .set_uvd_clocks = &vi_set_uvd_clocks,
1120 .set_vce_clocks = &vi_set_vce_clocks, 1134 .set_vce_clocks = &vi_set_vce_clocks,
1135 .get_virtual_caps = &vi_get_virtual_caps,
1121 /* these should be moved to their own ip modules */ 1136 /* these should be moved to their own ip modules */
1122 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter, 1137 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
1123 .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle, 1138 .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index ac005796b71c..7708d90b9da9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -242,13 +242,19 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn,
242 pqm_uninit(&p->pqm); 242 pqm_uninit(&p->pqm);
243 243
244 /* Iterate over all process device data structure and check 244 /* Iterate over all process device data structure and check
245 * if we should reset all wavefronts */ 245 * if we should delete debug managers and reset all wavefronts
246 list_for_each_entry(pdd, &p->per_device_data, per_device_list) 246 */
247 list_for_each_entry(pdd, &p->per_device_data, per_device_list) {
248 if ((pdd->dev->dbgmgr) &&
249 (pdd->dev->dbgmgr->pasid == p->pasid))
250 kfd_dbgmgr_destroy(pdd->dev->dbgmgr);
251
247 if (pdd->reset_wavefronts) { 252 if (pdd->reset_wavefronts) {
248 pr_warn("amdkfd: Resetting all wave fronts\n"); 253 pr_warn("amdkfd: Resetting all wave fronts\n");
249 dbgdev_wave_reset_wavefronts(pdd->dev, p); 254 dbgdev_wave_reset_wavefronts(pdd->dev, p);
250 pdd->reset_wavefronts = false; 255 pdd->reset_wavefronts = false;
251 } 256 }
257 }
252 258
253 mutex_unlock(&p->mutex); 259 mutex_unlock(&p->mutex);
254 260
@@ -404,42 +410,52 @@ void kfd_unbind_process_from_device(struct kfd_dev *dev, unsigned int pasid)
404 410
405 idx = srcu_read_lock(&kfd_processes_srcu); 411 idx = srcu_read_lock(&kfd_processes_srcu);
406 412
413 /*
414 * Look for the process that matches the pasid. If there is no such
415 * process, we either released it in amdkfd's own notifier, or there
416 * is a bug. Unfortunately, there is no way to tell...
417 */
407 hash_for_each_rcu(kfd_processes_table, i, p, kfd_processes) 418 hash_for_each_rcu(kfd_processes_table, i, p, kfd_processes)
408 if (p->pasid == pasid) 419 if (p->pasid == pasid) {
409 break;
410 420
411 srcu_read_unlock(&kfd_processes_srcu, idx); 421 srcu_read_unlock(&kfd_processes_srcu, idx);
412 422
413 BUG_ON(p->pasid != pasid); 423 pr_debug("Unbinding process %d from IOMMU\n", pasid);
414 424
415 mutex_lock(&p->mutex); 425 mutex_lock(&p->mutex);
416 426
417 if ((dev->dbgmgr) && (dev->dbgmgr->pasid == p->pasid)) 427 if ((dev->dbgmgr) && (dev->dbgmgr->pasid == p->pasid))
418 kfd_dbgmgr_destroy(dev->dbgmgr); 428 kfd_dbgmgr_destroy(dev->dbgmgr);
419 429
420 pqm_uninit(&p->pqm); 430 pqm_uninit(&p->pqm);
421 431
422 pdd = kfd_get_process_device_data(dev, p); 432 pdd = kfd_get_process_device_data(dev, p);
423 433
424 if (!pdd) { 434 if (!pdd) {
425 mutex_unlock(&p->mutex); 435 mutex_unlock(&p->mutex);
426 return; 436 return;
427 } 437 }
428 438
429 if (pdd->reset_wavefronts) { 439 if (pdd->reset_wavefronts) {
430 dbgdev_wave_reset_wavefronts(pdd->dev, p); 440 dbgdev_wave_reset_wavefronts(pdd->dev, p);
431 pdd->reset_wavefronts = false; 441 pdd->reset_wavefronts = false;
432 } 442 }
433 443
434 /* 444 /*
435 * Just mark pdd as unbound, because we still need it to call 445 * Just mark pdd as unbound, because we still need it
436 * amd_iommu_unbind_pasid() in when the process exits. 446 * to call amd_iommu_unbind_pasid() in when the
437 * We don't call amd_iommu_unbind_pasid() here 447 * process exits.
438 * because the IOMMU called us. 448 * We don't call amd_iommu_unbind_pasid() here
439 */ 449 * because the IOMMU called us.
440 pdd->bound = false; 450 */
451 pdd->bound = false;
441 452
442 mutex_unlock(&p->mutex); 453 mutex_unlock(&p->mutex);
454
455 return;
456 }
457
458 srcu_read_unlock(&kfd_processes_srcu, idx);
443} 459}
444 460
445struct kfd_process_device *kfd_get_first_process_device_data(struct kfd_process *p) 461struct kfd_process_device *kfd_get_first_process_device_data(struct kfd_process *p)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 74909e72a009..884c96f50c3d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -666,7 +666,7 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
666 dev->node_props.simd_count); 666 dev->node_props.simd_count);
667 667
668 if (dev->mem_bank_count < dev->node_props.mem_banks_count) { 668 if (dev->mem_bank_count < dev->node_props.mem_banks_count) {
669 pr_warn("kfd: mem_banks_count truncated from %d to %d\n", 669 pr_info_once("kfd: mem_banks_count truncated from %d to %d\n",
670 dev->node_props.mem_banks_count, 670 dev->node_props.mem_banks_count,
671 dev->mem_bank_count); 671 dev->mem_bank_count);
672 sysfs_show_32bit_prop(buffer, "mem_banks_count", 672 sysfs_show_32bit_prop(buffer, "mem_banks_count",
diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h
index 32f3e345de08..3493da5c8f0e 100644
--- a/drivers/gpu/drm/amd/include/atombios.h
+++ b/drivers/gpu/drm/amd/include/atombios.h
@@ -5538,6 +5538,78 @@ typedef struct _ATOM_ASIC_PROFILING_INFO_V3_5
5538 ULONG ulReserved[12]; 5538 ULONG ulReserved[12];
5539}ATOM_ASIC_PROFILING_INFO_V3_5; 5539}ATOM_ASIC_PROFILING_INFO_V3_5;
5540 5540
5541/* for Polars10/11 AVFS parameters */
5542typedef struct _ATOM_ASIC_PROFILING_INFO_V3_6
5543{
5544 ATOM_COMMON_TABLE_HEADER asHeader;
5545 ULONG ulMaxVddc;
5546 ULONG ulMinVddc;
5547 USHORT usLkgEuseIndex;
5548 UCHAR ucLkgEfuseBitLSB;
5549 UCHAR ucLkgEfuseLength;
5550 ULONG ulLkgEncodeLn_MaxDivMin;
5551 ULONG ulLkgEncodeMax;
5552 ULONG ulLkgEncodeMin;
5553 EFUSE_LINEAR_FUNC_PARAM sRoFuse;
5554 ULONG ulEvvDefaultVddc;
5555 ULONG ulEvvNoCalcVddc;
5556 ULONG ulSpeed_Model;
5557 ULONG ulSM_A0;
5558 ULONG ulSM_A1;
5559 ULONG ulSM_A2;
5560 ULONG ulSM_A3;
5561 ULONG ulSM_A4;
5562 ULONG ulSM_A5;
5563 ULONG ulSM_A6;
5564 ULONG ulSM_A7;
5565 UCHAR ucSM_A0_sign;
5566 UCHAR ucSM_A1_sign;
5567 UCHAR ucSM_A2_sign;
5568 UCHAR ucSM_A3_sign;
5569 UCHAR ucSM_A4_sign;
5570 UCHAR ucSM_A5_sign;
5571 UCHAR ucSM_A6_sign;
5572 UCHAR ucSM_A7_sign;
5573 ULONG ulMargin_RO_a;
5574 ULONG ulMargin_RO_b;
5575 ULONG ulMargin_RO_c;
5576 ULONG ulMargin_fixed;
5577 ULONG ulMargin_Fmax_mean;
5578 ULONG ulMargin_plat_mean;
5579 ULONG ulMargin_Fmax_sigma;
5580 ULONG ulMargin_plat_sigma;
5581 ULONG ulMargin_DC_sigma;
5582 ULONG ulLoadLineSlop;
5583 ULONG ulaTDClimitPerDPM[8];
5584 ULONG ulaNoCalcVddcPerDPM[8];
5585 ULONG ulAVFS_meanNsigma_Acontant0;
5586 ULONG ulAVFS_meanNsigma_Acontant1;
5587 ULONG ulAVFS_meanNsigma_Acontant2;
5588 USHORT usAVFS_meanNsigma_DC_tol_sigma;
5589 USHORT usAVFS_meanNsigma_Platform_mean;
5590 USHORT usAVFS_meanNsigma_Platform_sigma;
5591 ULONG ulGB_VDROOP_TABLE_CKSOFF_a0;
5592 ULONG ulGB_VDROOP_TABLE_CKSOFF_a1;
5593 ULONG ulGB_VDROOP_TABLE_CKSOFF_a2;
5594 ULONG ulGB_VDROOP_TABLE_CKSON_a0;
5595 ULONG ulGB_VDROOP_TABLE_CKSON_a1;
5596 ULONG ulGB_VDROOP_TABLE_CKSON_a2;
5597 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
5598 USHORT usAVFSGB_FUSE_TABLE_CKSOFF_m2;
5599 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_b;
5600 ULONG ulAVFSGB_FUSE_TABLE_CKSON_m1;
5601 USHORT usAVFSGB_FUSE_TABLE_CKSON_m2;
5602 ULONG ulAVFSGB_FUSE_TABLE_CKSON_b;
5603 USHORT usMaxVoltage_0_25mv;
5604 UCHAR ucEnableGB_VDROOP_TABLE_CKSOFF;
5605 UCHAR ucEnableGB_VDROOP_TABLE_CKSON;
5606 UCHAR ucEnableGB_FUSE_TABLE_CKSOFF;
5607 UCHAR ucEnableGB_FUSE_TABLE_CKSON;
5608 USHORT usPSM_Age_ComFactor;
5609 UCHAR ucEnableApplyAVFS_CKS_OFF_Voltage;
5610 UCHAR ucReserved;
5611}ATOM_ASIC_PROFILING_INFO_V3_6;
5612
5541 5613
5542typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{ 5614typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{
5543 ULONG ulMaxSclkFreq; 5615 ULONG ulMaxSclkFreq;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index 586f73276226..92912ab20944 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -633,6 +633,8 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
633 data->vddci_control = FIJI_VOLTAGE_CONTROL_NONE; 633 data->vddci_control = FIJI_VOLTAGE_CONTROL_NONE;
634 data->mvdd_control = FIJI_VOLTAGE_CONTROL_NONE; 634 data->mvdd_control = FIJI_VOLTAGE_CONTROL_NONE;
635 635
636 data->force_pcie_gen = PP_PCIEGenInvalid;
637
636 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, 638 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
637 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) 639 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
638 data->voltage_control = FIJI_VOLTAGE_CONTROL_BY_SVID2; 640 data->voltage_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index fa208ada6892..efb77eda7508 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -306,10 +306,14 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
306{ 306{
307 PHM_FUNC_CHECK(hwmgr); 307 PHM_FUNC_CHECK(hwmgr);
308 308
309 if (hwmgr->hwmgr_func->store_cc6_data == NULL) 309 if (display_config == NULL)
310 return -EINVAL; 310 return -EINVAL;
311 311
312 hwmgr->display_config = *display_config; 312 hwmgr->display_config = *display_config;
313
314 if (hwmgr->hwmgr_func->store_cc6_data == NULL)
315 return -EINVAL;
316
313 /* to do pass other display configuration in furture */ 317 /* to do pass other display configuration in furture */
314 318
315 if (hwmgr->hwmgr_func->store_cc6_data) 319 if (hwmgr->hwmgr_func->store_cc6_data)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
index 347fef127ce9..2930a3355948 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
@@ -39,6 +39,7 @@ struct phm_ppt_v1_clock_voltage_dependency_record {
39 uint8_t phases; 39 uint8_t phases;
40 uint8_t cks_enable; 40 uint8_t cks_enable;
41 uint8_t cks_voffset; 41 uint8_t cks_voffset;
42 uint32_t sclk_offset;
42}; 43};
43 44
44typedef struct phm_ppt_v1_clock_voltage_dependency_record phm_ppt_v1_clock_voltage_dependency_record; 45typedef struct phm_ppt_v1_clock_voltage_dependency_record phm_ppt_v1_clock_voltage_dependency_record;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index aa6be033f21b..64ee78f7d41e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -999,7 +999,7 @@ static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
999 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table), 999 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1000 (dep_table->entries[i].vddc - 1000 (dep_table->entries[i].vddc -
1001 (uint16_t)data->vddc_vddci_delta)); 1001 (uint16_t)data->vddc_vddci_delta));
1002 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; 1002 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1003 } 1003 }
1004 1004
1005 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) 1005 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
@@ -1296,7 +1296,6 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1296 } 1296 }
1297 1297
1298 mem_level->MclkFrequency = clock; 1298 mem_level->MclkFrequency = clock;
1299 mem_level->StutterEnable = 0;
1300 mem_level->EnabledForThrottle = 1; 1299 mem_level->EnabledForThrottle = 1;
1301 mem_level->EnabledForActivity = 0; 1300 mem_level->EnabledForActivity = 0;
1302 mem_level->UpHyst = 0; 1301 mem_level->UpHyst = 0;
@@ -1304,7 +1303,6 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1304 mem_level->VoltageDownHyst = 0; 1303 mem_level->VoltageDownHyst = 0;
1305 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target; 1304 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1306 mem_level->StutterEnable = false; 1305 mem_level->StutterEnable = false;
1307
1308 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 1306 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1309 1307
1310 data->display_timing.num_existing_displays = info.display_count; 1308 data->display_timing.num_existing_displays = info.display_count;
@@ -1363,7 +1361,7 @@ static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1363 * a higher state by default such that we are not effected by 1361 * a higher state by default such that we are not effected by
1364 * up threshold or and MCLK DPM latency. 1362 * up threshold or and MCLK DPM latency.
1365 */ 1363 */
1366 levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target; 1364 levels[0].ActivityLevel = 0x1f;
1367 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel); 1365 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1368 1366
1369 data->smc_state_table.MemoryDpmLevelCount = 1367 data->smc_state_table.MemoryDpmLevelCount =
@@ -1761,12 +1759,9 @@ static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1761 1759
1762static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) 1760static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1763{ 1761{
1764 uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks, 1762 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1765 volt_with_cks, value;
1766 uint16_t clock_freq_u16;
1767 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); 1763 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1768 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2, 1764 uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1769 volt_offset = 0;
1770 struct phm_ppt_v1_information *table_info = 1765 struct phm_ppt_v1_information *table_info =
1771 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1766 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1772 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = 1767 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
@@ -1778,50 +1773,38 @@ static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1778 * if the part is SS or FF. if RO >= 1660MHz, part is FF. 1773 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1779 */ 1774 */
1780 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1775 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1781 ixSMU_EFUSE_0 + (146 * 4)); 1776 ixSMU_EFUSE_0 + (67 * 4));
1782 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1783 ixSMU_EFUSE_0 + (148 * 4));
1784 efuse &= 0xFF000000; 1777 efuse &= 0xFF000000;
1785 efuse = efuse >> 24; 1778 efuse = efuse >> 24;
1786 efuse2 &= 0xF;
1787
1788 if (efuse2 == 1)
1789 ro = (2300 - 1350) * efuse / 255 + 1350;
1790 else
1791 ro = (2500 - 1000) * efuse / 255 + 1000;
1792 1779
1793 if (ro >= 1660) 1780 if (hwmgr->chip_id == CHIP_POLARIS10) {
1794 type = 0; 1781 min = 1000;
1795 else 1782 max = 2300;
1796 type = 1; 1783 } else {
1784 min = 1100;
1785 max = 2100;
1786 }
1797 1787
1798 /* Populate Stretch amount */ 1788 ro = efuse * (max -min)/255 + min;
1799 data->smc_state_table.ClockStretcherAmount = stretch_amount;
1800 1789
1801 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */ 1790 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1802 for (i = 0; i < sclk_table->count; i++) { 1791 for (i = 0; i < sclk_table->count; i++) {
1803 data->smc_state_table.Sclk_CKS_masterEn0_7 |= 1792 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1804 sclk_table->entries[i].cks_enable << i; 1793 sclk_table->entries[i].cks_enable << i;
1805 volt_without_cks = (uint32_t)((14041 * 1794
1806 (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 / 1795 volt_without_cks = (uint32_t)(((ro - 40) * 1000 - 2753594 - sclk_table->entries[i].clk/100 * 136418 /1000) / \
1807 (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000))); 1796 (sclk_table->entries[i].clk/100 * 1132925 /10000 - 242418)/100);
1808 volt_with_cks = (uint32_t)((13946 * 1797
1809 (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 / 1798 volt_with_cks = (uint32_t)((ro * 1000 -2396351 - sclk_table->entries[i].clk/100 * 329021/1000) / \
1810 (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000))); 1799 (sclk_table->entries[i].clk/10000 * 649434 /1000 - 18005)/10);
1800
1811 if (volt_without_cks >= volt_with_cks) 1801 if (volt_without_cks >= volt_with_cks)
1812 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks + 1802 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1813 sclk_table->entries[i].cks_voffset) * 100 / 625) + 1); 1803 sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1804
1814 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset; 1805 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1815 } 1806 }
1816 1807
1817 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1818 STRETCH_ENABLE, 0x0);
1819 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1820 masterReset, 0x1);
1821 /* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */
1822 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1823 masterReset, 0x0);
1824
1825 /* Populate CKS Lookup Table */ 1808 /* Populate CKS Lookup Table */
1826 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5) 1809 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1827 stretch_amount2 = 0; 1810 stretch_amount2 = 0;
@@ -1835,69 +1818,6 @@ static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1835 return -EINVAL); 1818 return -EINVAL);
1836 } 1819 }
1837 1820
1838 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1839 ixPWR_CKS_CNTL);
1840 value &= 0xFFC2FF87;
1841 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
1842 polaris10_clock_stretcher_lookup_table[stretch_amount2][0];
1843 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
1844 polaris10_clock_stretcher_lookup_table[stretch_amount2][1];
1845 clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
1846 GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100);
1847 if (polaris10_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16
1848 && polaris10_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) {
1849 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
1850 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
1851 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
1852 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
1853 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
1854 value |= (polaris10_clock_stretch_amount_conversion
1855 [polaris10_clock_stretcher_lookup_table[stretch_amount2][3]]
1856 [stretch_amount]) << 3;
1857 }
1858 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq);
1859 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq);
1860 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
1861 polaris10_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
1862 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
1863 (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
1864
1865 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1866 ixPWR_CKS_CNTL, value);
1867
1868 /* Populate DDT Lookup Table */
1869 for (i = 0; i < 4; i++) {
1870 /* Assign the minimum and maximum VID stored
1871 * in the last row of Clock Stretcher Voltage Table.
1872 */
1873 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID =
1874 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][2];
1875 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID =
1876 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][3];
1877 /* Loop through each SCLK and check the frequency
1878 * to see if it lies within the frequency for clock stretcher.
1879 */
1880 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
1881 cks_setting = 0;
1882 clock_freq = PP_SMC_TO_HOST_UL(
1883 data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency);
1884 /* Check the allowed frequency against the sclk level[j].
1885 * Sclk's endianness has already been converted,
1886 * and it's in 10Khz unit,
1887 * as opposed to Data table, which is in Mhz unit.
1888 */
1889 if (clock_freq >= (polaris10_clock_stretcher_ddt_table[type][i][0]) * 100) {
1890 cks_setting |= 0x2;
1891 if (clock_freq < (polaris10_clock_stretcher_ddt_table[type][i][1]) * 100)
1892 cks_setting |= 0x1;
1893 }
1894 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting
1895 |= cks_setting << (j * 2);
1896 }
1897 CONVERT_FROM_HOST_TO_SMC_US(
1898 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting);
1899 }
1900
1901 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL); 1821 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1902 value &= 0xFFFFFFFE; 1822 value &= 0xFFFFFFFE;
1903 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value); 1823 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
@@ -1956,6 +1876,90 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1956 return 0; 1876 return 0;
1957} 1877}
1958 1878
1879
1880int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1881{
1882 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1883 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1884 int result = 0;
1885 struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1886 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1887 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1888 uint32_t tmp, i;
1889 struct pp_smumgr *smumgr = hwmgr->smumgr;
1890 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1891
1892 struct phm_ppt_v1_information *table_info =
1893 (struct phm_ppt_v1_information *)hwmgr->pptable;
1894 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1895 table_info->vdd_dep_on_sclk;
1896
1897
1898 if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1899 return result;
1900
1901 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1902
1903 if (0 == result) {
1904 table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1905 table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1906 table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1907 table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1908 table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1909 table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1910 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1911 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1912 table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1913 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1914 table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;
1915 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1916 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1917 table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1918 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1919 table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;
1920 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1921 AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1922 AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1923 AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1924 AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1925 AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1926 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1927 AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1928
1929 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1930 AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1931 AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1932 }
1933
1934 result = polaris10_read_smc_sram_dword(smumgr,
1935 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1936 &tmp, data->sram_end);
1937
1938 polaris10_copy_bytes_to_smc(smumgr,
1939 tmp,
1940 (uint8_t *)&AVFS_meanNsigma,
1941 sizeof(AVFS_meanNsigma_t),
1942 data->sram_end);
1943
1944 result = polaris10_read_smc_sram_dword(smumgr,
1945 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1946 &tmp, data->sram_end);
1947 polaris10_copy_bytes_to_smc(smumgr,
1948 tmp,
1949 (uint8_t *)&AVFS_SclkOffset,
1950 sizeof(AVFS_Sclk_Offset_t),
1951 data->sram_end);
1952
1953 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1954 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1955 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1956 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1957 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1958 }
1959 return result;
1960}
1961
1962
1959/** 1963/**
1960* Initializes the SMC table and uploads it 1964* Initializes the SMC table and uploads it
1961* 1965*
@@ -2056,6 +2060,10 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
2056 "Failed to populate Clock Stretcher Data Table!", 2060 "Failed to populate Clock Stretcher Data Table!",
2057 return result); 2061 return result);
2058 } 2062 }
2063
2064 result = polaris10_populate_avfs_parameters(hwmgr);
2065 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2066
2059 table->CurrSclkPllRange = 0xff; 2067 table->CurrSclkPllRange = 0xff;
2060 table->GraphicsVoltageChangeEnable = 1; 2068 table->GraphicsVoltageChangeEnable = 1;
2061 table->GraphicsThermThrottleEnable = 1; 2069 table->GraphicsThermThrottleEnable = 1;
@@ -2252,6 +2260,9 @@ static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2252static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 2260static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2253{ 2261{
2254 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); 2262 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2263 uint32_t soft_register_value = 0;
2264 uint32_t handshake_disables_offset = data->soft_regs_start
2265 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
2255 2266
2256 /* enable SCLK dpm */ 2267 /* enable SCLK dpm */
2257 if (!data->sclk_dpm_key_disabled) 2268 if (!data->sclk_dpm_key_disabled)
@@ -2262,6 +2273,12 @@ static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2262 2273
2263 /* enable MCLK dpm */ 2274 /* enable MCLK dpm */
2264 if (0 == data->mclk_dpm_key_disabled) { 2275 if (0 == data->mclk_dpm_key_disabled) {
2276/* Disable UVD - SMU handshake for MCLK. */
2277 soft_register_value = cgs_read_ind_register(hwmgr->device,
2278 CGS_IND_REG__SMC, handshake_disables_offset);
2279 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2280 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2281 handshake_disables_offset, soft_register_value);
2265 2282
2266 PP_ASSERT_WITH_CODE( 2283 PP_ASSERT_WITH_CODE(
2267 (0 == smum_send_msg_to_smc(hwmgr->smumgr, 2284 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
@@ -2269,7 +2286,6 @@ static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2269 "Failed to enable MCLK DPM during DPM Start Function!", 2286 "Failed to enable MCLK DPM during DPM Start Function!",
2270 return -1); 2287 return -1);
2271 2288
2272
2273 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); 2289 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2274 2290
2275 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5); 2291 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
@@ -2606,6 +2622,7 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2606 2622
2607 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 2623 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2608 PHM_PlatformCaps_FanSpeedInTableIsRPM); 2624 PHM_PlatformCaps_FanSpeedInTableIsRPM);
2625
2609 if (hwmgr->chip_id == CHIP_POLARIS11) 2626 if (hwmgr->chip_id == CHIP_POLARIS11)
2610 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 2627 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2611 PHM_PlatformCaps_SPLLShutdownSupport); 2628 PHM_PlatformCaps_SPLLShutdownSupport);
@@ -2938,6 +2955,11 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2938 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE; 2955 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2939 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE; 2956 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2940 2957
2958 data->enable_tdc_limit_feature = true;
2959 data->enable_pkg_pwr_tracking_feature = true;
2960 data->force_pcie_gen = PP_PCIEGenInvalid;
2961 data->mclk_stutter_mode_threshold = 40000;
2962
2941 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, 2963 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2942 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) 2964 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
2943 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2; 2965 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
@@ -2962,6 +2984,10 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2962 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2; 2984 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2963 } 2985 }
2964 2986
2987 if (table_info->cac_dtp_table->usClockStretchAmount != 0)
2988 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2989 PHM_PlatformCaps_ClockStretcher);
2990
2965 polaris10_set_features_platform_caps(hwmgr); 2991 polaris10_set_features_platform_caps(hwmgr);
2966 2992
2967 polaris10_init_dpm_defaults(hwmgr); 2993 polaris10_init_dpm_defaults(hwmgr);
@@ -3520,10 +3546,11 @@ static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3520 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state; 3546 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3521 ATOM_Tonga_POWERPLAYTABLE *powerplay_table = 3547 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3522 (ATOM_Tonga_POWERPLAYTABLE *)pp_table; 3548 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3523 ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table = 3549 PPTable_Generic_SubTable_Header *sclk_dep_table =
3524 (ATOM_Tonga_SCLK_Dependency_Table *) 3550 (PPTable_Generic_SubTable_Header *)
3525 (((unsigned long)powerplay_table) + 3551 (((unsigned long)powerplay_table) +
3526 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)); 3552 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3553
3527 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = 3554 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3528 (ATOM_Tonga_MCLK_Dependency_Table *) 3555 (ATOM_Tonga_MCLK_Dependency_Table *)
3529 (((unsigned long)powerplay_table) + 3556 (((unsigned long)powerplay_table) +
@@ -3575,7 +3602,11 @@ static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3575 /* Performance levels are arranged from low to high. */ 3602 /* Performance levels are arranged from low to high. */
3576 performance_level->memory_clock = mclk_dep_table->entries 3603 performance_level->memory_clock = mclk_dep_table->entries
3577 [state_entry->ucMemoryClockIndexLow].ulMclk; 3604 [state_entry->ucMemoryClockIndexLow].ulMclk;
3578 performance_level->engine_clock = sclk_dep_table->entries 3605 if (sclk_dep_table->ucRevId == 0)
3606 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3607 [state_entry->ucEngineClockIndexLow].ulSclk;
3608 else if (sclk_dep_table->ucRevId == 1)
3609 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3579 [state_entry->ucEngineClockIndexLow].ulSclk; 3610 [state_entry->ucEngineClockIndexLow].ulSclk;
3580 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, 3611 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3581 state_entry->ucPCIEGenLow); 3612 state_entry->ucPCIEGenLow);
@@ -3586,8 +3617,14 @@ static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3586 [polaris10_power_state->performance_level_count++]); 3617 [polaris10_power_state->performance_level_count++]);
3587 performance_level->memory_clock = mclk_dep_table->entries 3618 performance_level->memory_clock = mclk_dep_table->entries
3588 [state_entry->ucMemoryClockIndexHigh].ulMclk; 3619 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3589 performance_level->engine_clock = sclk_dep_table->entries 3620
3621 if (sclk_dep_table->ucRevId == 0)
3622 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3590 [state_entry->ucEngineClockIndexHigh].ulSclk; 3623 [state_entry->ucEngineClockIndexHigh].ulSclk;
3624 else if (sclk_dep_table->ucRevId == 1)
3625 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3626 [state_entry->ucEngineClockIndexHigh].ulSclk;
3627
3591 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, 3628 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3592 state_entry->ucPCIEGenHigh); 3629 state_entry->ucPCIEGenHigh);
3593 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, 3630 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
@@ -3645,7 +3682,6 @@ static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3645 switch (state->classification.ui_label) { 3682 switch (state->classification.ui_label) {
3646 case PP_StateUILabel_Performance: 3683 case PP_StateUILabel_Performance:
3647 data->use_pcie_performance_levels = true; 3684 data->use_pcie_performance_levels = true;
3648
3649 for (i = 0; i < ps->performance_level_count; i++) { 3685 for (i = 0; i < ps->performance_level_count; i++) {
3650 if (data->pcie_gen_performance.max < 3686 if (data->pcie_gen_performance.max <
3651 ps->performance_levels[i].pcie_gen) 3687 ps->performance_levels[i].pcie_gen)
@@ -3661,7 +3697,6 @@ static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3661 ps->performance_levels[i].pcie_lane) 3697 ps->performance_levels[i].pcie_lane)
3662 data->pcie_lane_performance.max = 3698 data->pcie_lane_performance.max =
3663 ps->performance_levels[i].pcie_lane; 3699 ps->performance_levels[i].pcie_lane;
3664
3665 if (data->pcie_lane_performance.min > 3700 if (data->pcie_lane_performance.min >
3666 ps->performance_levels[i].pcie_lane) 3701 ps->performance_levels[i].pcie_lane)
3667 data->pcie_lane_performance.min = 3702 data->pcie_lane_performance.min =
@@ -4187,12 +4222,9 @@ int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4187{ 4222{
4188 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); 4223 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4189 uint32_t mm_boot_level_offset, mm_boot_level_value; 4224 uint32_t mm_boot_level_offset, mm_boot_level_value;
4190 struct phm_ppt_v1_information *table_info =
4191 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4192 4225
4193 if (!bgate) { 4226 if (!bgate) {
4194 data->smc_state_table.SamuBootLevel = 4227 data->smc_state_table.SamuBootLevel = 0;
4195 (uint8_t) (table_info->mm_dep_table->count - 1);
4196 mm_boot_level_offset = data->dpm_table_start + 4228 mm_boot_level_offset = data->dpm_table_start +
4197 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel); 4229 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4198 mm_boot_level_offset /= 4; 4230 mm_boot_level_offset /= 4;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
index beedf35cbfa6..d717789441f5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
@@ -312,6 +312,9 @@ struct polaris10_hwmgr {
312 312
313 /* soft pptable for re-uploading into smu */ 313 /* soft pptable for re-uploading into smu */
314 void *soft_pp_table; 314 void *soft_pp_table;
315
316 uint32_t avfs_vdroop_override_setting;
317 bool apply_avfs_cks_off_voltage;
315}; 318};
316 319
317/* To convert to Q8.8 format for firmware */ 320/* To convert to Q8.8 format for firmware */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
index aba167f7d167..b206632d4650 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
@@ -625,10 +625,14 @@ static int tf_polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
625 int ret; 625 int ret;
626 struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr); 626 struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr);
627 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); 627 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
628 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
628 629
629 if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS) 630 if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
630 return 0; 631 return 0;
631 632
633 ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
634 PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting);
635
632 ret = (smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs) == 0) ? 636 ret = (smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs) == 0) ?
633 0 : -1; 637 0 : -1;
634 638
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
index 58742e0d1492..a3c38bbd1e94 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
@@ -44,6 +44,20 @@ bool acpi_atcs_functions_supported(void *device, uint32_t index)
44 return result == 0 ? (output_buf.function_bits & (1 << (index - 1))) != 0 : false; 44 return result == 0 ? (output_buf.function_bits & (1 << (index - 1))) != 0 : false;
45} 45}
46 46
47bool acpi_atcs_notify_pcie_device_ready(void *device)
48{
49 int32_t temp_buffer = 1;
50
51 return cgs_call_acpi_method(device, CGS_ACPI_METHOD_ATCS,
52 ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION,
53 &temp_buffer,
54 NULL,
55 0,
56 sizeof(temp_buffer),
57 0);
58}
59
60
47int acpi_pcie_perf_request(void *device, uint8_t perf_req, bool advertise) 61int acpi_pcie_perf_request(void *device, uint8_t perf_req, bool advertise)
48{ 62{
49 struct atcs_pref_req_input atcs_input; 63 struct atcs_pref_req_input atcs_input;
@@ -52,7 +66,7 @@ int acpi_pcie_perf_request(void *device, uint8_t perf_req, bool advertise)
52 int result; 66 int result;
53 struct cgs_system_info info = {0}; 67 struct cgs_system_info info = {0};
54 68
55 if (!acpi_atcs_functions_supported(device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST)) 69 if( 0 != acpi_atcs_notify_pcie_device_ready(device))
56 return -EINVAL; 70 return -EINVAL;
57 71
58 info.size = sizeof(struct cgs_system_info); 72 info.size = sizeof(struct cgs_system_info);
@@ -77,7 +91,7 @@ int acpi_pcie_perf_request(void *device, uint8_t perf_req, bool advertise)
77 ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST, 91 ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST,
78 &atcs_input, 92 &atcs_input,
79 &atcs_output, 93 &atcs_output,
80 0, 94 1,
81 sizeof(atcs_input), 95 sizeof(atcs_input),
82 sizeof(atcs_output)); 96 sizeof(atcs_output));
83 if (result != 0) 97 if (result != 0)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
index da9f5f1b6dc2..bf4e18fd3872 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
@@ -1302,3 +1302,46 @@ int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctr
1302 1302
1303 return 0; 1303 return 0;
1304} 1304}
1305
1306int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param)
1307{
1308 ATOM_ASIC_PROFILING_INFO_V3_6 *profile = NULL;
1309
1310 if (param == NULL)
1311 return -EINVAL;
1312
1313 profile = (ATOM_ASIC_PROFILING_INFO_V3_6 *)
1314 cgs_atom_get_data_table(hwmgr->device,
1315 GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),
1316 NULL, NULL, NULL);
1317 if (!profile)
1318 return -1;
1319
1320 param->ulAVFS_meanNsigma_Acontant0 = profile->ulAVFS_meanNsigma_Acontant0;
1321 param->ulAVFS_meanNsigma_Acontant1 = profile->ulAVFS_meanNsigma_Acontant1;
1322 param->ulAVFS_meanNsigma_Acontant2 = profile->ulAVFS_meanNsigma_Acontant2;
1323 param->usAVFS_meanNsigma_DC_tol_sigma = profile->usAVFS_meanNsigma_DC_tol_sigma;
1324 param->usAVFS_meanNsigma_Platform_mean = profile->usAVFS_meanNsigma_Platform_mean;
1325 param->usAVFS_meanNsigma_Platform_sigma = profile->usAVFS_meanNsigma_Platform_sigma;
1326 param->ulGB_VDROOP_TABLE_CKSOFF_a0 = profile->ulGB_VDROOP_TABLE_CKSOFF_a0;
1327 param->ulGB_VDROOP_TABLE_CKSOFF_a1 = profile->ulGB_VDROOP_TABLE_CKSOFF_a1;
1328 param->ulGB_VDROOP_TABLE_CKSOFF_a2 = profile->ulGB_VDROOP_TABLE_CKSOFF_a2;
1329 param->ulGB_VDROOP_TABLE_CKSON_a0 = profile->ulGB_VDROOP_TABLE_CKSON_a0;
1330 param->ulGB_VDROOP_TABLE_CKSON_a1 = profile->ulGB_VDROOP_TABLE_CKSON_a1;
1331 param->ulGB_VDROOP_TABLE_CKSON_a2 = profile->ulGB_VDROOP_TABLE_CKSON_a2;
1332 param->ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = profile->ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
1333 param->usAVFSGB_FUSE_TABLE_CKSOFF_m2 = profile->usAVFSGB_FUSE_TABLE_CKSOFF_m2;
1334 param->ulAVFSGB_FUSE_TABLE_CKSOFF_b = profile->ulAVFSGB_FUSE_TABLE_CKSOFF_b;
1335 param->ulAVFSGB_FUSE_TABLE_CKSON_m1 = profile->ulAVFSGB_FUSE_TABLE_CKSON_m1;
1336 param->usAVFSGB_FUSE_TABLE_CKSON_m2 = profile->usAVFSGB_FUSE_TABLE_CKSON_m2;
1337 param->ulAVFSGB_FUSE_TABLE_CKSON_b = profile->ulAVFSGB_FUSE_TABLE_CKSON_b;
1338 param->usMaxVoltage_0_25mv = profile->usMaxVoltage_0_25mv;
1339 param->ucEnableGB_VDROOP_TABLE_CKSOFF = profile->ucEnableGB_VDROOP_TABLE_CKSOFF;
1340 param->ucEnableGB_VDROOP_TABLE_CKSON = profile->ucEnableGB_VDROOP_TABLE_CKSON;
1341 param->ucEnableGB_FUSE_TABLE_CKSOFF = profile->ucEnableGB_FUSE_TABLE_CKSOFF;
1342 param->ucEnableGB_FUSE_TABLE_CKSON = profile->ucEnableGB_FUSE_TABLE_CKSON;
1343 param->usPSM_Age_ComFactor = profile->usPSM_Age_ComFactor;
1344 param->ucEnableApplyAVFS_CKS_OFF_Voltage = profile->ucEnableApplyAVFS_CKS_OFF_Voltage;
1345
1346 return 0;
1347}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
index d24ebb566905..248c5db5f380 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
@@ -250,6 +250,35 @@ struct pp_atomctrl_gpio_pin_assignment {
250}; 250};
251typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment; 251typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment;
252 252
253struct pp_atom_ctrl__avfs_parameters {
254 uint32_t ulAVFS_meanNsigma_Acontant0;
255 uint32_t ulAVFS_meanNsigma_Acontant1;
256 uint32_t ulAVFS_meanNsigma_Acontant2;
257 uint16_t usAVFS_meanNsigma_DC_tol_sigma;
258 uint16_t usAVFS_meanNsigma_Platform_mean;
259 uint16_t usAVFS_meanNsigma_Platform_sigma;
260 uint32_t ulGB_VDROOP_TABLE_CKSOFF_a0;
261 uint32_t ulGB_VDROOP_TABLE_CKSOFF_a1;
262 uint32_t ulGB_VDROOP_TABLE_CKSOFF_a2;
263 uint32_t ulGB_VDROOP_TABLE_CKSON_a0;
264 uint32_t ulGB_VDROOP_TABLE_CKSON_a1;
265 uint32_t ulGB_VDROOP_TABLE_CKSON_a2;
266 uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
267 uint16_t usAVFSGB_FUSE_TABLE_CKSOFF_m2;
268 uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_b;
269 uint32_t ulAVFSGB_FUSE_TABLE_CKSON_m1;
270 uint16_t usAVFSGB_FUSE_TABLE_CKSON_m2;
271 uint32_t ulAVFSGB_FUSE_TABLE_CKSON_b;
272 uint16_t usMaxVoltage_0_25mv;
273 uint8_t ucEnableGB_VDROOP_TABLE_CKSOFF;
274 uint8_t ucEnableGB_VDROOP_TABLE_CKSON;
275 uint8_t ucEnableGB_FUSE_TABLE_CKSOFF;
276 uint8_t ucEnableGB_FUSE_TABLE_CKSON;
277 uint16_t usPSM_Age_ComFactor;
278 uint8_t ucEnableApplyAVFS_CKS_OFF_Voltage;
279 uint8_t ucReserved;
280};
281
253extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment); 282extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment);
254extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage); 283extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
255extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr); 284extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
@@ -278,5 +307,8 @@ extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clo
278extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 307extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
279 uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage); 308 uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
280extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table); 309extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table);
310
311extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param);
312
281#endif 313#endif
282 314
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index d27e8c40602a..233eb7f36c1d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -4489,6 +4489,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
4489 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_NONE; 4489 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_NONE;
4490 data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_NONE; 4490 data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_NONE;
4491 data->mvdd_control = TONGA_VOLTAGE_CONTROL_NONE; 4491 data->mvdd_control = TONGA_VOLTAGE_CONTROL_NONE;
4492 data->force_pcie_gen = PP_PCIEGenInvalid;
4492 4493
4493 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, 4494 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4494 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) { 4495 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
index 1b44f4e9b8f5..f127198aafc4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
@@ -197,6 +197,22 @@ typedef struct _ATOM_Tonga_SCLK_Dependency_Table {
197 ATOM_Tonga_SCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ 197 ATOM_Tonga_SCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */
198} ATOM_Tonga_SCLK_Dependency_Table; 198} ATOM_Tonga_SCLK_Dependency_Table;
199 199
200typedef struct _ATOM_Polaris_SCLK_Dependency_Record {
201 UCHAR ucVddInd; /* Base voltage */
202 USHORT usVddcOffset; /* Offset relative to base voltage */
203 ULONG ulSclk;
204 USHORT usEdcCurrent;
205 UCHAR ucReliabilityTemperature;
206 UCHAR ucCKSVOffsetandDisable; /* Bits 0~6: Voltage offset for CKS, Bit 7: Disable/enable for the SCLK level. */
207 ULONG ulSclkOffset;
208} ATOM_Polaris_SCLK_Dependency_Record;
209
210typedef struct _ATOM_Polaris_SCLK_Dependency_Table {
211 UCHAR ucRevId;
212 UCHAR ucNumEntries; /* Number of entries. */
213 ATOM_Polaris_SCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */
214} ATOM_Polaris_SCLK_Dependency_Table;
215
200typedef struct _ATOM_Tonga_PCIE_Record { 216typedef struct _ATOM_Tonga_PCIE_Record {
201 UCHAR ucPCIEGenSpeed; 217 UCHAR ucPCIEGenSpeed;
202 UCHAR usPCIELaneWidth; 218 UCHAR usPCIELaneWidth;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
index 296ec7ef6d45..671fdb4d615a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
@@ -408,41 +408,78 @@ static int get_mclk_voltage_dependency_table(
408static int get_sclk_voltage_dependency_table( 408static int get_sclk_voltage_dependency_table(
409 struct pp_hwmgr *hwmgr, 409 struct pp_hwmgr *hwmgr,
410 phm_ppt_v1_clock_voltage_dependency_table **pp_tonga_sclk_dep_table, 410 phm_ppt_v1_clock_voltage_dependency_table **pp_tonga_sclk_dep_table,
411 const ATOM_Tonga_SCLK_Dependency_Table * sclk_dep_table 411 const PPTable_Generic_SubTable_Header *sclk_dep_table
412 ) 412 )
413{ 413{
414 uint32_t table_size, i; 414 uint32_t table_size, i;
415 phm_ppt_v1_clock_voltage_dependency_table *sclk_table; 415 phm_ppt_v1_clock_voltage_dependency_table *sclk_table;
416 416
417 PP_ASSERT_WITH_CODE((0 != sclk_dep_table->ucNumEntries), 417 if (sclk_dep_table->ucRevId < 1) {
418 "Invalid PowerPlay Table!", return -1); 418 const ATOM_Tonga_SCLK_Dependency_Table *tonga_table =
419 (ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table;
419 420
420 table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record) 421 PP_ASSERT_WITH_CODE((0 != tonga_table->ucNumEntries),
421 * sclk_dep_table->ucNumEntries; 422 "Invalid PowerPlay Table!", return -1);
422 423
423 sclk_table = (phm_ppt_v1_clock_voltage_dependency_table *) 424 table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
424 kzalloc(table_size, GFP_KERNEL); 425 * tonga_table->ucNumEntries;
425 426
426 if (NULL == sclk_table) 427 sclk_table = (phm_ppt_v1_clock_voltage_dependency_table *)
427 return -ENOMEM; 428 kzalloc(table_size, GFP_KERNEL);
428 429
429 memset(sclk_table, 0x00, table_size); 430 if (NULL == sclk_table)
430 431 return -ENOMEM;
431 sclk_table->count = (uint32_t)sclk_dep_table->ucNumEntries; 432
432 433 memset(sclk_table, 0x00, table_size);
433 for (i = 0; i < sclk_dep_table->ucNumEntries; i++) { 434
434 sclk_table->entries[i].vddInd = 435 sclk_table->count = (uint32_t)tonga_table->ucNumEntries;
435 sclk_dep_table->entries[i].ucVddInd; 436
436 sclk_table->entries[i].vdd_offset = 437 for (i = 0; i < tonga_table->ucNumEntries; i++) {
437 sclk_dep_table->entries[i].usVddcOffset; 438 sclk_table->entries[i].vddInd =
438 sclk_table->entries[i].clk = 439 tonga_table->entries[i].ucVddInd;
439 sclk_dep_table->entries[i].ulSclk; 440 sclk_table->entries[i].vdd_offset =
440 sclk_table->entries[i].cks_enable = 441 tonga_table->entries[i].usVddcOffset;
441 (((sclk_dep_table->entries[i].ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0; 442 sclk_table->entries[i].clk =
442 sclk_table->entries[i].cks_voffset = 443 tonga_table->entries[i].ulSclk;
443 (sclk_dep_table->entries[i].ucCKSVOffsetandDisable & 0x7F); 444 sclk_table->entries[i].cks_enable =
444 } 445 (((tonga_table->entries[i].ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0;
446 sclk_table->entries[i].cks_voffset =
447 (tonga_table->entries[i].ucCKSVOffsetandDisable & 0x7F);
448 }
449 } else {
450 const ATOM_Polaris_SCLK_Dependency_Table *polaris_table =
451 (ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table;
445 452
453 PP_ASSERT_WITH_CODE((0 != polaris_table->ucNumEntries),
454 "Invalid PowerPlay Table!", return -1);
455
456 table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
457 * polaris_table->ucNumEntries;
458
459 sclk_table = (phm_ppt_v1_clock_voltage_dependency_table *)
460 kzalloc(table_size, GFP_KERNEL);
461
462 if (NULL == sclk_table)
463 return -ENOMEM;
464
465 memset(sclk_table, 0x00, table_size);
466
467 sclk_table->count = (uint32_t)polaris_table->ucNumEntries;
468
469 for (i = 0; i < polaris_table->ucNumEntries; i++) {
470 sclk_table->entries[i].vddInd =
471 polaris_table->entries[i].ucVddInd;
472 sclk_table->entries[i].vdd_offset =
473 polaris_table->entries[i].usVddcOffset;
474 sclk_table->entries[i].clk =
475 polaris_table->entries[i].ulSclk;
476 sclk_table->entries[i].cks_enable =
477 (((polaris_table->entries[i].ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0;
478 sclk_table->entries[i].cks_voffset =
479 (polaris_table->entries[i].ucCKSVOffsetandDisable & 0x7F);
480 sclk_table->entries[i].sclk_offset = polaris_table->entries[i].ulSclkOffset;
481 }
482 }
446 *pp_tonga_sclk_dep_table = sclk_table; 483 *pp_tonga_sclk_dep_table = sclk_table;
447 484
448 return 0; 485 return 0;
@@ -708,8 +745,8 @@ static int init_clock_voltage_dependency(
708 const ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = 745 const ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
709 (const ATOM_Tonga_MCLK_Dependency_Table *)(((unsigned long) powerplay_table) + 746 (const ATOM_Tonga_MCLK_Dependency_Table *)(((unsigned long) powerplay_table) +
710 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); 747 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
711 const ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table = 748 const PPTable_Generic_SubTable_Header *sclk_dep_table =
712 (const ATOM_Tonga_SCLK_Dependency_Table *)(((unsigned long) powerplay_table) + 749 (const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
713 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)); 750 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
714 const ATOM_Tonga_Hard_Limit_Table *pHardLimits = 751 const ATOM_Tonga_Hard_Limit_Table *pHardLimits =
715 (const ATOM_Tonga_Hard_Limit_Table *)(((unsigned long) powerplay_table) + 752 (const ATOM_Tonga_Hard_Limit_Table *)(((unsigned long) powerplay_table) +
diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h
index 0c6a413eaa5b..d41d37ab5b7c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h
@@ -27,6 +27,7 @@
27 27
28#pragma pack(push, 1) 28#pragma pack(push, 1)
29 29
30#define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305)
30 31
31#define PPSMC_SWSTATE_FLAG_DC 0x01 32#define PPSMC_SWSTATE_FLAG_DC 0x01
32#define PPSMC_SWSTATE_FLAG_UVD 0x02 33#define PPSMC_SWSTATE_FLAG_UVD 0x02
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h b/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h
index 3bd5e69b9045..3df5de2cdab0 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h
@@ -26,3 +26,4 @@ extern bool acpi_atcs_functions_supported(void *device,
26extern int acpi_pcie_perf_request(void *device, 26extern int acpi_pcie_perf_request(void *device,
27 uint8_t perf_req, 27 uint8_t perf_req,
28 bool advertise); 28 bool advertise);
29extern bool acpi_atcs_notify_pcie_device_ready(void *device);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74.h b/drivers/gpu/drm/amd/powerplay/inc/smu74.h
index 1a12d85b8e97..fd10a9fa843d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu74.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu74.h
@@ -34,6 +34,30 @@
34#define SMU__NUM_LCLK_DPM_LEVELS 8 34#define SMU__NUM_LCLK_DPM_LEVELS 8
35#define SMU__NUM_PCIE_DPM_LEVELS 8 35#define SMU__NUM_PCIE_DPM_LEVELS 8
36 36
37#define EXP_M1 35
38#define EXP_M2 92821
39#define EXP_B 66629747
40
41#define EXP_M1_1 365
42#define EXP_M2_1 658700
43#define EXP_B_1 305506134
44
45#define EXP_M1_2 189
46#define EXP_M2_2 379692
47#define EXP_B_2 194609469
48
49#define EXP_M1_3 99
50#define EXP_M2_3 217915
51#define EXP_B_3 122255994
52
53#define EXP_M1_4 51
54#define EXP_M2_4 122643
55#define EXP_B_4 74893384
56
57#define EXP_M1_5 423
58#define EXP_M2_5 1103326
59#define EXP_B_5 728122621
60
37enum SID_OPTION { 61enum SID_OPTION {
38 SID_OPTION_HI, 62 SID_OPTION_HI,
39 SID_OPTION_LO, 63 SID_OPTION_LO,
@@ -548,20 +572,20 @@ struct SMU74_Firmware_Header {
548 uint32_t CacConfigTable; 572 uint32_t CacConfigTable;
549 uint32_t CacStatusTable; 573 uint32_t CacStatusTable;
550 574
551
552 uint32_t mcRegisterTable; 575 uint32_t mcRegisterTable;
553 576
554
555 uint32_t mcArbDramTimingTable; 577 uint32_t mcArbDramTimingTable;
556 578
557
558
559
560 uint32_t PmFuseTable; 579 uint32_t PmFuseTable;
561 uint32_t Globals; 580 uint32_t Globals;
562 uint32_t ClockStretcherTable; 581 uint32_t ClockStretcherTable;
563 uint32_t VftTable; 582 uint32_t VftTable;
564 uint32_t Reserved[21]; 583 uint32_t Reserved1;
584 uint32_t AvfsTable;
585 uint32_t AvfsCksOffGbvTable;
586 uint32_t AvfsMeanNSigma;
587 uint32_t AvfsSclkOffsetTable;
588 uint32_t Reserved[16];
565 uint32_t Signature; 589 uint32_t Signature;
566}; 590};
567 591
@@ -701,8 +725,6 @@ VR Config info is contained in dpmTable.VRConfig */
701struct SMU_ClockStretcherDataTableEntry { 725struct SMU_ClockStretcherDataTableEntry {
702 uint8_t minVID; 726 uint8_t minVID;
703 uint8_t maxVID; 727 uint8_t maxVID;
704
705
706 uint16_t setting; 728 uint16_t setting;
707}; 729};
708typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry; 730typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
@@ -769,6 +791,43 @@ struct VFT_TABLE_t {
769typedef struct VFT_TABLE_t VFT_TABLE_t; 791typedef struct VFT_TABLE_t VFT_TABLE_t;
770 792
771 793
794/* Total margin, root mean square of Fmax + DC + Platform */
795struct AVFS_Margin_t {
796 VFT_CELL_t Cell[NUM_VFT_COLUMNS];
797};
798typedef struct AVFS_Margin_t AVFS_Margin_t;
799
800#define BTCGB_VDROOP_TABLE_MAX_ENTRIES 2
801#define AVFSGB_VDROOP_TABLE_MAX_ENTRIES 2
802
803struct GB_VDROOP_TABLE_t {
804 int32_t a0;
805 int32_t a1;
806 int32_t a2;
807 uint32_t spare;
808};
809typedef struct GB_VDROOP_TABLE_t GB_VDROOP_TABLE_t;
810
811struct AVFS_CksOff_Gbv_t {
812 VFT_CELL_t Cell[NUM_VFT_COLUMNS];
813};
814typedef struct AVFS_CksOff_Gbv_t AVFS_CksOff_Gbv_t;
815
816struct AVFS_meanNsigma_t {
817 uint32_t Aconstant[3];
818 uint16_t DC_tol_sigma;
819 uint16_t Platform_mean;
820 uint16_t Platform_sigma;
821 uint16_t PSM_Age_CompFactor;
822 uint8_t Static_Voltage_Offset[NUM_VFT_COLUMNS];
823};
824typedef struct AVFS_meanNsigma_t AVFS_meanNsigma_t;
825
826struct AVFS_Sclk_Offset_t {
827 uint16_t Sclk_Offset[8];
828};
829typedef struct AVFS_Sclk_Offset_t AVFS_Sclk_Offset_t;
830
772#endif 831#endif
773 832
774 833
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
index 0dfe82336dc7..b85ff5400e57 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
@@ -223,6 +223,16 @@ struct SMU74_Discrete_StateInfo {
223 223
224typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo; 224typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo;
225 225
226struct SMU_QuadraticCoeffs {
227 int32_t m1;
228 uint32_t b;
229
230 int16_t m2;
231 uint8_t m1_shift;
232 uint8_t m2_shift;
233};
234typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
235
226struct SMU74_Discrete_DpmTable { 236struct SMU74_Discrete_DpmTable {
227 237
228 SMU74_PIDController GraphicsPIDController; 238 SMU74_PIDController GraphicsPIDController;
@@ -258,7 +268,14 @@ struct SMU74_Discrete_DpmTable {
258 uint8_t ThermOutPolarity; 268 uint8_t ThermOutPolarity;
259 uint8_t ThermOutMode; 269 uint8_t ThermOutMode;
260 uint8_t BootPhases; 270 uint8_t BootPhases;
261 uint32_t Reserved[4]; 271
272 uint8_t VRHotLevel;
273 uint8_t Reserved1[3];
274 uint16_t FanStartTemperature;
275 uint16_t FanStopTemperature;
276 uint16_t MaxVoltage;
277 uint16_t Reserved2;
278 uint32_t Reserved[1];
262 279
263 SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS]; 280 SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];
264 SMU74_Discrete_MemoryLevel MemoryACPILevel; 281 SMU74_Discrete_MemoryLevel MemoryACPILevel;
@@ -347,6 +364,8 @@ struct SMU74_Discrete_DpmTable {
347 364
348 uint32_t CurrSclkPllRange; 365 uint32_t CurrSclkPllRange;
349 sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE]; 366 sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE];
367 GB_VDROOP_TABLE_t BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES];
368 SMU_QuadraticCoeffs AVFSGB_VDROOP_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES];
350}; 369};
351 370
352typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable; 371typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable;
@@ -550,16 +569,6 @@ struct SMU7_AcpiScoreboard {
550 569
551typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard; 570typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
552 571
553struct SMU_QuadraticCoeffs {
554 int32_t m1;
555 uint32_t b;
556
557 int16_t m2;
558 uint8_t m1_shift;
559 uint8_t m2_shift;
560};
561typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
562
563struct SMU74_Discrete_PmFuses { 572struct SMU74_Discrete_PmFuses {
564 uint8_t BapmVddCVidHiSidd[8]; 573 uint8_t BapmVddCVidHiSidd[8];
565 uint8_t BapmVddCVidLoSidd[8]; 574 uint8_t BapmVddCVidLoSidd[8];
@@ -821,6 +830,17 @@ typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
821#define DB_PCC_SHIFT 26 830#define DB_PCC_SHIFT 26
822#define DB_EDC_SHIFT 27 831#define DB_EDC_SHIFT 27
823 832
833#define BTCGB0_Vdroop_Enable_MASK 0x1
834#define BTCGB1_Vdroop_Enable_MASK 0x2
835#define AVFSGB0_Vdroop_Enable_MASK 0x4
836#define AVFSGB1_Vdroop_Enable_MASK 0x8
837
838#define BTCGB0_Vdroop_Enable_SHIFT 0
839#define BTCGB1_Vdroop_Enable_SHIFT 1
840#define AVFSGB0_Vdroop_Enable_SHIFT 2
841#define AVFSGB1_Vdroop_Enable_SHIFT 3
842
843
824#pragma pack(pop) 844#pragma pack(pop)
825 845
826 846
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 043b6ac09d5f..5dba7c509710 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -52,19 +52,18 @@
52static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = { 52static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
53 /* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */ 53 /* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */
54 /* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */ 54 /* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
55 { 0x3c0fd047, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x30750000, 0, 0, 0, 0, 0, 0, 0 } }, 55 { 0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000, 0x3000, 0, 0x2600, 0, 0, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
56 { 0xa00fd047, 0x01, 0x04, 0x1e00, 0x00800510, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x409c0000, 0, 0, 0, 0, 0, 0, 0 } }, 56 { 0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000, 0x2000, 0, 0x1e00, 1, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
57 { 0x0410d047, 0x01, 0x00, 0x1e00, 0x00600410, 0x87020000, 0, 0, 0x0e, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x50c30000, 0, 0, 0, 0, 0, 0, 0 } }, 57 { 0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000, 0x2800, 0, 0x2000, 1, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } },
58 { 0x6810d047, 0x01, 0x00, 0x1e00, 0x00800410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x60ea0000, 0, 0, 0, 0, 0, 0, 0 } }, 58 { 0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000, 0x3000, 0, 0x2600, 1, 1, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
59 { 0xcc10d047, 0x01, 0x00, 0x1e00, 0x00e00410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xe8fd0000, 0, 0, 0, 0, 0, 0, 0 } }, 59 { 0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100, 0x3800, 0, 0x2c00, 1, 1, 0x0004, 0x1203, 0xffff, 0x3600, 0xc9e2, 0x2e00 } },
60 { 0x3011d047, 0x01, 0x00, 0x1e00, 0x00400510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x70110100, 0, 0, 0, 0, 0, 0, 0 } }, 60 { 0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100, 0x2000, 0, 0x1e00, 2, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
61 { 0x9411d047, 0x01, 0x00, 0x1e00, 0x00a00510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xf8240100, 0, 0, 0, 0, 0, 0, 0 } }, 61 { 0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100, 0x2400, 0, 0x1e00, 2, 1, 0x0004, 0x8901, 0xffff, 0x2300, 0x314c, 0x1d00 } },
62 { 0xf811d047, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x80380100, 0, 0, 0, 0, 0, 0, 0 } } 62 { 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }
63}; 63};
64 64
65static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = 65static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 =
66 {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00, 66 {0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
67 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00};
68 67
69/** 68/**
70* Set the address for reading/writing the SMC SRAM space. 69* Set the address for reading/writing the SMC SRAM space.
@@ -219,6 +218,18 @@ bool polaris10_is_smc_ram_running(struct pp_smumgr *smumgr)
219 && (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C))); 218 && (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
220} 219}
221 220
221static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr)
222{
223 uint32_t efuse;
224
225 efuse = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
226 efuse &= 0x00000001;
227 if (efuse)
228 return true;
229
230 return false;
231}
232
222/** 233/**
223* Send a message to the SMC, and wait for its response. 234* Send a message to the SMC, and wait for its response.
224* 235*
@@ -228,21 +239,27 @@ bool polaris10_is_smc_ram_running(struct pp_smumgr *smumgr)
228*/ 239*/
229int polaris10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) 240int polaris10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
230{ 241{
242 int ret;
243
231 if (!polaris10_is_smc_ram_running(smumgr)) 244 if (!polaris10_is_smc_ram_running(smumgr))
232 return -1; 245 return -1;
233 246
247
234 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); 248 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
235 249
236 if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) 250 ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
237 printk("Failed to send Previous Message.\n");
238 251
252 if (ret != 1)
253 printk("\n failed to send pre message %x ret is %d \n", msg, ret);
239 254
240 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); 255 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
241 256
242 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); 257 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
243 258
244 if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) 259 ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
245 printk("Failed to send Message.\n"); 260
261 if (ret != 1)
262 printk("\n failed to send message %x ret is %d \n", msg, ret);
246 263
247 return 0; 264 return 0;
248} 265}
@@ -953,6 +970,11 @@ static int polaris10_smu_init(struct pp_smumgr *smumgr)
953 (cgs_handle_t)smu_data->smu_buffer.handle); 970 (cgs_handle_t)smu_data->smu_buffer.handle);
954 return -1;); 971 return -1;);
955 972
973 if (polaris10_is_hw_avfs_present(smumgr))
974 smu_data->avfs.avfs_btc_status = AVFS_BTC_BOOT;
975 else
976 smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED;
977
956 return 0; 978 return 0;
957} 979}
958 980
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-26 00:33:40 -0400