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-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c89
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c26
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_object.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c13
-rw-r--r--drivers/gpu/drm/amd/amdgpu/atombios_encoders.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/atombios_encoders.h5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v6_0.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c30
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si.c22
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_dpm.c50
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c2
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c169
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c6
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c6
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc.c6
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link.c3
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c4
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_resource.c3
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_stream.c82
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc.h3
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc_stream.h2
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h10
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c38
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h3
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c1
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c91
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c18
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c2
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c2
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c1
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c65
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h3
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h3
-rw-r--r--drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c2
-rw-r--r--drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c3
-rw-r--r--drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h5
-rw-r--r--drivers/gpu/drm/amd/display/include/signal_types.h5
-rw-r--r--drivers/gpu/drm/amd/powerplay/amd_powerplay.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c18
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c11
52 files changed, 524 insertions, 363 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d5a2eefd6c3e..74edba18b159 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1156,7 +1156,7 @@ static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1156/* 1156/*
1157 * Writeback 1157 * Writeback
1158 */ 1158 */
1159#define AMDGPU_MAX_WB 512 /* Reserve at most 512 WB slots for amdgpu-owned rings. */ 1159#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */
1160 1160
1161struct amdgpu_wb { 1161struct amdgpu_wb {
1162 struct amdgpu_bo *wb_obj; 1162 struct amdgpu_bo *wb_obj;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 57afad79f55d..8fa850a070e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -540,6 +540,9 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
540 size_t size; 540 size_t size;
541 u32 retry = 3; 541 u32 retry = 3;
542 542
543 if (amdgpu_acpi_pcie_notify_device_ready(adev))
544 return -EINVAL;
545
543 /* Get the device handle */ 546 /* Get the device handle */
544 handle = ACPI_HANDLE(&adev->pdev->dev); 547 handle = ACPI_HANDLE(&adev->pdev->dev);
545 if (!handle) 548 if (!handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index 8ca3783f2deb..7a073ac5f9c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -69,25 +69,18 @@ void amdgpu_connector_hotplug(struct drm_connector *connector)
69 /* don't do anything if sink is not display port, i.e., 69 /* don't do anything if sink is not display port, i.e.,
70 * passive dp->(dvi|hdmi) adaptor 70 * passive dp->(dvi|hdmi) adaptor
71 */ 71 */
72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
73 int saved_dpms = connector->dpms; 73 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
74 /* Only turn off the display if it's physically disconnected */ 74 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
75 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 75 /* Don't start link training before we have the DPCD */
76 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 76 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
77 } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 77 return;
78 /* Don't try to start link training before we 78
79 * have the dpcd */ 79 /* Turn the connector off and back on immediately, which
80 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 80 * will trigger link training
81 return; 81 */
82 82 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
83 /* set it to OFF so that drm_helper_connector_dpms() 83 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
84 * won't return immediately since the current state
85 * is ON at this point.
86 */
87 connector->dpms = DRM_MODE_DPMS_OFF;
88 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
89 }
90 connector->dpms = saved_dpms;
91 } 84 }
92 } 85 }
93} 86}
@@ -736,9 +729,11 @@ amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
736 enum drm_connector_status ret = connector_status_disconnected; 729 enum drm_connector_status ret = connector_status_disconnected;
737 int r; 730 int r;
738 731
739 r = pm_runtime_get_sync(connector->dev->dev); 732 if (!drm_kms_helper_is_poll_worker()) {
740 if (r < 0) 733 r = pm_runtime_get_sync(connector->dev->dev);
741 return connector_status_disconnected; 734 if (r < 0)
735 return connector_status_disconnected;
736 }
742 737
743 if (encoder) { 738 if (encoder) {
744 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 739 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
@@ -757,8 +752,12 @@ amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
757 /* check acpi lid status ??? */ 752 /* check acpi lid status ??? */
758 753
759 amdgpu_connector_update_scratch_regs(connector, ret); 754 amdgpu_connector_update_scratch_regs(connector, ret);
760 pm_runtime_mark_last_busy(connector->dev->dev); 755
761 pm_runtime_put_autosuspend(connector->dev->dev); 756 if (!drm_kms_helper_is_poll_worker()) {
757 pm_runtime_mark_last_busy(connector->dev->dev);
758 pm_runtime_put_autosuspend(connector->dev->dev);
759 }
760
762 return ret; 761 return ret;
763} 762}
764 763
@@ -868,9 +867,11 @@ amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
868 enum drm_connector_status ret = connector_status_disconnected; 867 enum drm_connector_status ret = connector_status_disconnected;
869 int r; 868 int r;
870 869
871 r = pm_runtime_get_sync(connector->dev->dev); 870 if (!drm_kms_helper_is_poll_worker()) {
872 if (r < 0) 871 r = pm_runtime_get_sync(connector->dev->dev);
873 return connector_status_disconnected; 872 if (r < 0)
873 return connector_status_disconnected;
874 }
874 875
875 encoder = amdgpu_connector_best_single_encoder(connector); 876 encoder = amdgpu_connector_best_single_encoder(connector);
876 if (!encoder) 877 if (!encoder)
@@ -924,8 +925,10 @@ amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
924 amdgpu_connector_update_scratch_regs(connector, ret); 925 amdgpu_connector_update_scratch_regs(connector, ret);
925 926
926out: 927out:
927 pm_runtime_mark_last_busy(connector->dev->dev); 928 if (!drm_kms_helper_is_poll_worker()) {
928 pm_runtime_put_autosuspend(connector->dev->dev); 929 pm_runtime_mark_last_busy(connector->dev->dev);
930 pm_runtime_put_autosuspend(connector->dev->dev);
931 }
929 932
930 return ret; 933 return ret;
931} 934}
@@ -988,9 +991,11 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
988 enum drm_connector_status ret = connector_status_disconnected; 991 enum drm_connector_status ret = connector_status_disconnected;
989 bool dret = false, broken_edid = false; 992 bool dret = false, broken_edid = false;
990 993
991 r = pm_runtime_get_sync(connector->dev->dev); 994 if (!drm_kms_helper_is_poll_worker()) {
992 if (r < 0) 995 r = pm_runtime_get_sync(connector->dev->dev);
993 return connector_status_disconnected; 996 if (r < 0)
997 return connector_status_disconnected;
998 }
994 999
995 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1000 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
996 ret = connector->status; 1001 ret = connector->status;
@@ -1115,8 +1120,10 @@ out:
1115 amdgpu_connector_update_scratch_regs(connector, ret); 1120 amdgpu_connector_update_scratch_regs(connector, ret);
1116 1121
1117exit: 1122exit:
1118 pm_runtime_mark_last_busy(connector->dev->dev); 1123 if (!drm_kms_helper_is_poll_worker()) {
1119 pm_runtime_put_autosuspend(connector->dev->dev); 1124 pm_runtime_mark_last_busy(connector->dev->dev);
1125 pm_runtime_put_autosuspend(connector->dev->dev);
1126 }
1120 1127
1121 return ret; 1128 return ret;
1122} 1129}
@@ -1359,9 +1366,11 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1359 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1366 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1360 int r; 1367 int r;
1361 1368
1362 r = pm_runtime_get_sync(connector->dev->dev); 1369 if (!drm_kms_helper_is_poll_worker()) {
1363 if (r < 0) 1370 r = pm_runtime_get_sync(connector->dev->dev);
1364 return connector_status_disconnected; 1371 if (r < 0)
1372 return connector_status_disconnected;
1373 }
1365 1374
1366 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1375 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1367 ret = connector->status; 1376 ret = connector->status;
@@ -1429,8 +1438,10 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1429 1438
1430 amdgpu_connector_update_scratch_regs(connector, ret); 1439 amdgpu_connector_update_scratch_regs(connector, ret);
1431out: 1440out:
1432 pm_runtime_mark_last_busy(connector->dev->dev); 1441 if (!drm_kms_helper_is_poll_worker()) {
1433 pm_runtime_put_autosuspend(connector->dev->dev); 1442 pm_runtime_mark_last_busy(connector->dev->dev);
1443 pm_runtime_put_autosuspend(connector->dev->dev);
1444 }
1434 1445
1435 return ret; 1446 return ret;
1436} 1447}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 00a50cc5ec9a..af1b879a9ee9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -492,7 +492,7 @@ static int amdgpu_device_wb_init(struct amdgpu_device *adev)
492 memset(&adev->wb.used, 0, sizeof(adev->wb.used)); 492 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
493 493
494 /* clear wb memory */ 494 /* clear wb memory */
495 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t)); 495 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
496 } 496 }
497 497
498 return 0; 498 return 0;
@@ -530,8 +530,9 @@ int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
530 */ 530 */
531void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) 531void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
532{ 532{
533 wb >>= 3;
533 if (wb < adev->wb.num_wb) 534 if (wb < adev->wb.num_wb)
534 __clear_bit(wb >> 3, adev->wb.used); 535 __clear_bit(wb, adev->wb.used);
535} 536}
536 537
537/** 538/**
@@ -1455,11 +1456,6 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1455 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1456 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1456 if (!adev->ip_blocks[i].status.hw) 1457 if (!adev->ip_blocks[i].status.hw)
1457 continue; 1458 continue;
1458 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1459 amdgpu_free_static_csa(adev);
1460 amdgpu_device_wb_fini(adev);
1461 amdgpu_device_vram_scratch_fini(adev);
1462 }
1463 1459
1464 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && 1460 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1465 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { 1461 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
@@ -1486,6 +1482,13 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1486 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1482 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1487 if (!adev->ip_blocks[i].status.sw) 1483 if (!adev->ip_blocks[i].status.sw)
1488 continue; 1484 continue;
1485
1486 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1487 amdgpu_free_static_csa(adev);
1488 amdgpu_device_wb_fini(adev);
1489 amdgpu_device_vram_scratch_fini(adev);
1490 }
1491
1489 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); 1492 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1490 /* XXX handle errors */ 1493 /* XXX handle errors */
1491 if (r) { 1494 if (r) {
@@ -2284,14 +2287,6 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2284 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 2287 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2285 } 2288 }
2286 drm_modeset_unlock_all(dev); 2289 drm_modeset_unlock_all(dev);
2287 } else {
2288 /*
2289 * There is no equivalent atomic helper to turn on
2290 * display, so we defined our own function for this,
2291 * once suspend resume is supported by the atomic
2292 * framework this will be reworked
2293 */
2294 amdgpu_dm_display_resume(adev);
2295 } 2290 }
2296 } 2291 }
2297 2292
@@ -2726,7 +2721,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
2726 if (amdgpu_device_has_dc_support(adev)) { 2721 if (amdgpu_device_has_dc_support(adev)) {
2727 if (drm_atomic_helper_resume(adev->ddev, state)) 2722 if (drm_atomic_helper_resume(adev->ddev, state))
2728 dev_info(adev->dev, "drm resume failed:%d\n", r); 2723 dev_info(adev->dev, "drm resume failed:%d\n", r);
2729 amdgpu_dm_display_resume(adev);
2730 } else { 2724 } else {
2731 drm_helper_resume_force_mode(adev->ddev); 2725 drm_helper_resume_force_mode(adev->ddev);
2732 } 2726 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index e48b4ec88c8c..ca6c931dabfa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -36,8 +36,6 @@ void amdgpu_gem_object_free(struct drm_gem_object *gobj)
36 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 36 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
37 37
38 if (robj) { 38 if (robj) {
39 if (robj->gem_base.import_attach)
40 drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
41 amdgpu_mn_unregister(robj); 39 amdgpu_mn_unregister(robj);
42 amdgpu_bo_unref(&robj); 40 amdgpu_bo_unref(&robj);
43 } 41 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index e14ab34d8262..7c2be32c5aea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -75,7 +75,7 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager *man,
75static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man) 75static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
76{ 76{
77 struct amdgpu_gtt_mgr *mgr = man->priv; 77 struct amdgpu_gtt_mgr *mgr = man->priv;
78 78 spin_lock(&mgr->lock);
79 drm_mm_takedown(&mgr->mm); 79 drm_mm_takedown(&mgr->mm);
80 spin_unlock(&mgr->lock); 80 spin_unlock(&mgr->lock);
81 kfree(mgr); 81 kfree(mgr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 56bcd59c3399..36483e0d3c97 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -257,7 +257,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
257 r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq); 257 r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
258 if (r) { 258 if (r) {
259 adev->irq.installed = false; 259 adev->irq.installed = false;
260 flush_work(&adev->hotplug_work); 260 if (!amdgpu_device_has_dc_support(adev))
261 flush_work(&adev->hotplug_work);
261 cancel_work_sync(&adev->reset_work); 262 cancel_work_sync(&adev->reset_work);
262 return r; 263 return r;
263 } 264 }
@@ -282,7 +283,8 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
282 adev->irq.installed = false; 283 adev->irq.installed = false;
283 if (adev->irq.msi_enabled) 284 if (adev->irq.msi_enabled)
284 pci_disable_msi(adev->pdev); 285 pci_disable_msi(adev->pdev);
285 flush_work(&adev->hotplug_work); 286 if (!amdgpu_device_has_dc_support(adev))
287 flush_work(&adev->hotplug_work);
286 cancel_work_sync(&adev->reset_work); 288 cancel_work_sync(&adev->reset_work);
287 } 289 }
288 290
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 54f06c959340..2264c5c97009 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -352,6 +352,7 @@ struct amdgpu_mode_info {
352 u16 firmware_flags; 352 u16 firmware_flags;
353 /* pointer to backlight encoder */ 353 /* pointer to backlight encoder */
354 struct amdgpu_encoder *bl_encoder; 354 struct amdgpu_encoder *bl_encoder;
355 u8 bl_level; /* saved backlight level */
355 struct amdgpu_audio audio; /* audio stuff */ 356 struct amdgpu_audio audio; /* audio stuff */
356 int num_crtc; /* number of crtcs */ 357 int num_crtc; /* number of crtcs */
357 int num_hpd; /* number of hpd pins */ 358 int num_hpd; /* number of hpd pins */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 5c4c3e0d527b..1220322c1680 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -56,6 +56,8 @@ static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
56 56
57 amdgpu_bo_kunmap(bo); 57 amdgpu_bo_kunmap(bo);
58 58
59 if (bo->gem_base.import_attach)
60 drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
59 drm_gem_object_release(&bo->gem_base); 61 drm_gem_object_release(&bo->gem_base);
60 amdgpu_bo_unref(&bo->parent); 62 amdgpu_bo_unref(&bo->parent);
61 if (!list_empty(&bo->shadow_list)) { 63 if (!list_empty(&bo->shadow_list)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 13044e66dcaf..561d3312af32 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -481,7 +481,7 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
481 result = 0; 481 result = 0;
482 482
483 if (*pos < 12) { 483 if (*pos < 12) {
484 early[0] = amdgpu_ring_get_rptr(ring); 484 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
485 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; 485 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
486 early[2] = ring->wptr & ring->buf_mask; 486 early[2] = ring->wptr & ring->buf_mask;
487 for (i = *pos / 4; i < 3 && size; i++) { 487 for (i = *pos / 4; i < 3 && size; i++) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index b2eae86bf906..5c26a8e806b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -299,12 +299,15 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
299 299
300 cancel_delayed_work_sync(&adev->uvd.idle_work); 300 cancel_delayed_work_sync(&adev->uvd.idle_work);
301 301
302 for (i = 0; i < adev->uvd.max_handles; ++i) 302 /* only valid for physical mode */
303 if (atomic_read(&adev->uvd.handles[i])) 303 if (adev->asic_type < CHIP_POLARIS10) {
304 break; 304 for (i = 0; i < adev->uvd.max_handles; ++i)
305 if (atomic_read(&adev->uvd.handles[i]))
306 break;
305 307
306 if (i == AMDGPU_MAX_UVD_HANDLES) 308 if (i == adev->uvd.max_handles)
307 return 0; 309 return 0;
310 }
308 311
309 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 312 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
310 ptr = adev->uvd.cpu_addr; 313 ptr = adev->uvd.cpu_addr;
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
index 2af26d2da127..d702fb8e3427 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
@@ -34,7 +34,7 @@
34#include <linux/backlight.h> 34#include <linux/backlight.h>
35#include "bif/bif_4_1_d.h" 35#include "bif/bif_4_1_d.h"
36 36
37static u8 37u8
38amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev) 38amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev)
39{ 39{
40 u8 backlight_level; 40 u8 backlight_level;
@@ -48,7 +48,7 @@ amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev)
48 return backlight_level; 48 return backlight_level;
49} 49}
50 50
51static void 51void
52amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev, 52amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev,
53 u8 backlight_level) 53 u8 backlight_level)
54{ 54{
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h
index 2bdec40515ce..f77cbdef679e 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h
@@ -25,6 +25,11 @@
25#define __ATOMBIOS_ENCODER_H__ 25#define __ATOMBIOS_ENCODER_H__
26 26
27u8 27u8
28amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev);
29void
30amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev,
31 u8 backlight_level);
32u8
28amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder); 33amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder);
29void 34void
30amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder, 35amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index f34bc68aadfb..022f303463fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2921,6 +2921,11 @@ static int dce_v10_0_hw_fini(void *handle)
2921 2921
2922static int dce_v10_0_suspend(void *handle) 2922static int dce_v10_0_suspend(void *handle)
2923{ 2923{
2924 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2925
2926 adev->mode_info.bl_level =
2927 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2928
2924 return dce_v10_0_hw_fini(handle); 2929 return dce_v10_0_hw_fini(handle);
2925} 2930}
2926 2931
@@ -2929,6 +2934,9 @@ static int dce_v10_0_resume(void *handle)
2929 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2934 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2930 int ret; 2935 int ret;
2931 2936
2937 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2938 adev->mode_info.bl_level);
2939
2932 ret = dce_v10_0_hw_init(handle); 2940 ret = dce_v10_0_hw_init(handle);
2933 2941
2934 /* turn on the BL */ 2942 /* turn on the BL */
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 26378bd6aba4..800a9f36ab4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3047,6 +3047,11 @@ static int dce_v11_0_hw_fini(void *handle)
3047 3047
3048static int dce_v11_0_suspend(void *handle) 3048static int dce_v11_0_suspend(void *handle)
3049{ 3049{
3050 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3051
3052 adev->mode_info.bl_level =
3053 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
3054
3050 return dce_v11_0_hw_fini(handle); 3055 return dce_v11_0_hw_fini(handle);
3051} 3056}
3052 3057
@@ -3055,6 +3060,9 @@ static int dce_v11_0_resume(void *handle)
3055 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3060 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3056 int ret; 3061 int ret;
3057 3062
3063 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
3064 adev->mode_info.bl_level);
3065
3058 ret = dce_v11_0_hw_init(handle); 3066 ret = dce_v11_0_hw_init(handle);
3059 3067
3060 /* turn on the BL */ 3068 /* turn on the BL */
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index bd2c4f727df6..b8368f69ce1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -2787,6 +2787,11 @@ static int dce_v6_0_hw_fini(void *handle)
2787 2787
2788static int dce_v6_0_suspend(void *handle) 2788static int dce_v6_0_suspend(void *handle)
2789{ 2789{
2790 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2791
2792 adev->mode_info.bl_level =
2793 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2794
2790 return dce_v6_0_hw_fini(handle); 2795 return dce_v6_0_hw_fini(handle);
2791} 2796}
2792 2797
@@ -2795,6 +2800,9 @@ static int dce_v6_0_resume(void *handle)
2795 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2800 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2796 int ret; 2801 int ret;
2797 2802
2803 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2804 adev->mode_info.bl_level);
2805
2798 ret = dce_v6_0_hw_init(handle); 2806 ret = dce_v6_0_hw_init(handle);
2799 2807
2800 /* turn on the BL */ 2808 /* turn on the BL */
@@ -3093,7 +3101,7 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
3093 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 3101 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3094 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 3102 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3095 schedule_work(&adev->hotplug_work); 3103 schedule_work(&adev->hotplug_work);
3096 DRM_INFO("IH: HPD%d\n", hpd + 1); 3104 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3097 } 3105 }
3098 3106
3099 return 0; 3107 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index c008dc030687..012e0a9ae0ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2819,6 +2819,11 @@ static int dce_v8_0_hw_fini(void *handle)
2819 2819
2820static int dce_v8_0_suspend(void *handle) 2820static int dce_v8_0_suspend(void *handle)
2821{ 2821{
2822 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2823
2824 adev->mode_info.bl_level =
2825 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2826
2822 return dce_v8_0_hw_fini(handle); 2827 return dce_v8_0_hw_fini(handle);
2823} 2828}
2824 2829
@@ -2827,6 +2832,9 @@ static int dce_v8_0_resume(void *handle)
2827 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2832 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2828 int ret; 2833 int ret;
2829 2834
2835 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2836 adev->mode_info.bl_level);
2837
2830 ret = dce_v8_0_hw_init(handle); 2838 ret = dce_v8_0_hw_init(handle);
2831 2839
2832 /* turn on the BL */ 2840 /* turn on the BL */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index a066c5eda135..a4309698e76c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4384,34 +4384,8 @@ static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4384 case CHIP_KAVERI: 4384 case CHIP_KAVERI:
4385 adev->gfx.config.max_shader_engines = 1; 4385 adev->gfx.config.max_shader_engines = 1;
4386 adev->gfx.config.max_tile_pipes = 4; 4386 adev->gfx.config.max_tile_pipes = 4;
4387 if ((adev->pdev->device == 0x1304) || 4387 adev->gfx.config.max_cu_per_sh = 8;
4388 (adev->pdev->device == 0x1305) || 4388 adev->gfx.config.max_backends_per_se = 2;
4389 (adev->pdev->device == 0x130C) ||
4390 (adev->pdev->device == 0x130F) ||
4391 (adev->pdev->device == 0x1310) ||
4392 (adev->pdev->device == 0x1311) ||
4393 (adev->pdev->device == 0x131C)) {
4394 adev->gfx.config.max_cu_per_sh = 8;
4395 adev->gfx.config.max_backends_per_se = 2;
4396 } else if ((adev->pdev->device == 0x1309) ||
4397 (adev->pdev->device == 0x130A) ||
4398 (adev->pdev->device == 0x130D) ||
4399 (adev->pdev->device == 0x1313) ||
4400 (adev->pdev->device == 0x131D)) {
4401 adev->gfx.config.max_cu_per_sh = 6;
4402 adev->gfx.config.max_backends_per_se = 2;
4403 } else if ((adev->pdev->device == 0x1306) ||
4404 (adev->pdev->device == 0x1307) ||
4405 (adev->pdev->device == 0x130B) ||
4406 (adev->pdev->device == 0x130E) ||
4407 (adev->pdev->device == 0x1315) ||
4408 (adev->pdev->device == 0x131B)) {
4409 adev->gfx.config.max_cu_per_sh = 4;
4410 adev->gfx.config.max_backends_per_se = 1;
4411 } else {
4412 adev->gfx.config.max_cu_per_sh = 3;
4413 adev->gfx.config.max_backends_per_se = 1;
4414 }
4415 adev->gfx.config.max_sh_per_se = 1; 4389 adev->gfx.config.max_sh_per_se = 1;
4416 adev->gfx.config.max_texture_channel_caches = 4; 4390 adev->gfx.config.max_texture_channel_caches = 4;
4417 adev->gfx.config.max_gprs = 256; 4391 adev->gfx.config.max_gprs = 256;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 2719937e09d6..3b7e7af09ead 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -634,7 +634,7 @@ static int gmc_v9_0_late_init(void *handle)
634 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i) 634 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
635 BUG_ON(vm_inv_eng[i] > 16); 635 BUG_ON(vm_inv_eng[i] > 16);
636 636
637 if (adev->asic_type == CHIP_VEGA10) { 637 if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {
638 r = gmc_v9_0_ecc_available(adev); 638 r = gmc_v9_0_ecc_available(adev);
639 if (r == 1) { 639 if (r == 1) {
640 DRM_INFO("ECC is active.\n"); 640 DRM_INFO("ECC is active.\n");
@@ -682,7 +682,10 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
682 adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); 682 adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
683 if (!adev->mc.vram_width) { 683 if (!adev->mc.vram_width) {
684 /* hbm memory channel size */ 684 /* hbm memory channel size */
685 chansize = 128; 685 if (adev->flags & AMD_IS_APU)
686 chansize = 64;
687 else
688 chansize = 128;
686 689
687 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); 690 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
688 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK; 691 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index e92fb372bc99..91cf95a8c39c 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -238,31 +238,27 @@ static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
238static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 238static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
239{ 239{
240 struct amdgpu_device *adev = ring->adev; 240 struct amdgpu_device *adev = ring->adev;
241 u64 *wptr = NULL; 241 u64 wptr;
242 uint64_t local_wptr = 0;
243 242
244 if (ring->use_doorbell) { 243 if (ring->use_doorbell) {
245 /* XXX check if swapping is necessary on BE */ 244 /* XXX check if swapping is necessary on BE */
246 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]); 245 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
247 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr); 246 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
248 *wptr = (*wptr) >> 2;
249 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
250 } else { 247 } else {
251 u32 lowbit, highbit; 248 u32 lowbit, highbit;
252 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; 249 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
253 250
254 wptr = &local_wptr;
255 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2; 251 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2;
256 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 252 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
257 253
258 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 254 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
259 me, highbit, lowbit); 255 me, highbit, lowbit);
260 *wptr = highbit; 256 wptr = highbit;
261 *wptr = (*wptr) << 32; 257 wptr = wptr << 32;
262 *wptr |= lowbit; 258 wptr |= lowbit;
263 } 259 }
264 260
265 return *wptr; 261 return wptr >> 2;
266} 262}
267 263
268/** 264/**
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 543101d5a5ed..2095173aaabf 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -31,6 +31,7 @@
31#include "amdgpu_uvd.h" 31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h" 32#include "amdgpu_vce.h"
33#include "atom.h" 33#include "atom.h"
34#include "amd_pcie.h"
34#include "amdgpu_powerplay.h" 35#include "amdgpu_powerplay.h"
35#include "sid.h" 36#include "sid.h"
36#include "si_ih.h" 37#include "si_ih.h"
@@ -1461,8 +1462,8 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
1461{ 1462{
1462 struct pci_dev *root = adev->pdev->bus->self; 1463 struct pci_dev *root = adev->pdev->bus->self;
1463 int bridge_pos, gpu_pos; 1464 int bridge_pos, gpu_pos;
1464 u32 speed_cntl, mask, current_data_rate; 1465 u32 speed_cntl, current_data_rate;
1465 int ret, i; 1466 int i;
1466 u16 tmp16; 1467 u16 tmp16;
1467 1468
1468 if (pci_is_root_bus(adev->pdev->bus)) 1469 if (pci_is_root_bus(adev->pdev->bus))
@@ -1474,23 +1475,20 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
1474 if (adev->flags & AMD_IS_APU) 1475 if (adev->flags & AMD_IS_APU)
1475 return; 1476 return;
1476 1477
1477 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); 1478 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1478 if (ret != 0) 1479 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
1479 return;
1480
1481 if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
1482 return; 1480 return;
1483 1481
1484 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 1482 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1485 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> 1483 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
1486 LC_CURRENT_DATA_RATE_SHIFT; 1484 LC_CURRENT_DATA_RATE_SHIFT;
1487 if (mask & DRM_PCIE_SPEED_80) { 1485 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1488 if (current_data_rate == 2) { 1486 if (current_data_rate == 2) {
1489 DRM_INFO("PCIE gen 3 link speeds already enabled\n"); 1487 DRM_INFO("PCIE gen 3 link speeds already enabled\n");
1490 return; 1488 return;
1491 } 1489 }
1492 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1490 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
1493 } else if (mask & DRM_PCIE_SPEED_50) { 1491 } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
1494 if (current_data_rate == 1) { 1492 if (current_data_rate == 1) {
1495 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 1493 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
1496 return; 1494 return;
@@ -1506,7 +1504,7 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
1506 if (!gpu_pos) 1504 if (!gpu_pos)
1507 return; 1505 return;
1508 1506
1509 if (mask & DRM_PCIE_SPEED_80) { 1507 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1510 if (current_data_rate != 2) { 1508 if (current_data_rate != 2) {
1511 u16 bridge_cfg, gpu_cfg; 1509 u16 bridge_cfg, gpu_cfg;
1512 u16 bridge_cfg2, gpu_cfg2; 1510 u16 bridge_cfg2, gpu_cfg2;
@@ -1589,9 +1587,9 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
1589 1587
1590 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 1588 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1591 tmp16 &= ~0xf; 1589 tmp16 &= ~0xf;
1592 if (mask & DRM_PCIE_SPEED_80) 1590 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1593 tmp16 |= 3; 1591 tmp16 |= 3;
1594 else if (mask & DRM_PCIE_SPEED_50) 1592 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1595 tmp16 |= 2; 1593 tmp16 |= 2;
1596 else 1594 else
1597 tmp16 |= 1; 1595 tmp16 |= 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index ce675a7f179a..22f0b7ff3ac9 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -26,6 +26,7 @@
26#include "amdgpu_pm.h" 26#include "amdgpu_pm.h"
27#include "amdgpu_dpm.h" 27#include "amdgpu_dpm.h"
28#include "amdgpu_atombios.h" 28#include "amdgpu_atombios.h"
29#include "amd_pcie.h"
29#include "sid.h" 30#include "sid.h"
30#include "r600_dpm.h" 31#include "r600_dpm.h"
31#include "si_dpm.h" 32#include "si_dpm.h"
@@ -3331,29 +3332,6 @@ static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3331 } 3332 }
3332} 3333}
3333 3334
3334static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3335 u32 sys_mask,
3336 enum amdgpu_pcie_gen asic_gen,
3337 enum amdgpu_pcie_gen default_gen)
3338{
3339 switch (asic_gen) {
3340 case AMDGPU_PCIE_GEN1:
3341 return AMDGPU_PCIE_GEN1;
3342 case AMDGPU_PCIE_GEN2:
3343 return AMDGPU_PCIE_GEN2;
3344 case AMDGPU_PCIE_GEN3:
3345 return AMDGPU_PCIE_GEN3;
3346 default:
3347 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3348 return AMDGPU_PCIE_GEN3;
3349 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3350 return AMDGPU_PCIE_GEN2;
3351 else
3352 return AMDGPU_PCIE_GEN1;
3353 }
3354 return AMDGPU_PCIE_GEN1;
3355}
3356
3357static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, 3335static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3358 u32 *p, u32 *u) 3336 u32 *p, u32 *u)
3359{ 3337{
@@ -5028,10 +5006,11 @@ static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
5028 table->ACPIState.levels[0].vddc.index, 5006 table->ACPIState.levels[0].vddc.index,
5029 &table->ACPIState.levels[0].std_vddc); 5007 &table->ACPIState.levels[0].std_vddc);
5030 } 5008 }
5031 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev, 5009 table->ACPIState.levels[0].gen2PCIE =
5032 si_pi->sys_pcie_mask, 5010 (u8)amdgpu_get_pcie_gen_support(adev,
5033 si_pi->boot_pcie_gen, 5011 si_pi->sys_pcie_mask,
5034 AMDGPU_PCIE_GEN1); 5012 si_pi->boot_pcie_gen,
5013 AMDGPU_PCIE_GEN1);
5035 5014
5036 if (si_pi->vddc_phase_shed_control) 5015 if (si_pi->vddc_phase_shed_control)
5037 si_populate_phase_shedding_value(adev, 5016 si_populate_phase_shedding_value(adev,
@@ -7168,10 +7147,10 @@ static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7168 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 7147 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7169 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 7148 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7170 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 7149 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7171 pl->pcie_gen = r600_get_pcie_gen_support(adev, 7150 pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
7172 si_pi->sys_pcie_mask, 7151 si_pi->sys_pcie_mask,
7173 si_pi->boot_pcie_gen, 7152 si_pi->boot_pcie_gen,
7174 clock_info->si.ucPCIEGen); 7153 clock_info->si.ucPCIEGen);
7175 7154
7176 /* patch up vddc if necessary */ 7155 /* patch up vddc if necessary */
7177 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, 7156 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
@@ -7326,7 +7305,6 @@ static int si_dpm_init(struct amdgpu_device *adev)
7326 struct si_power_info *si_pi; 7305 struct si_power_info *si_pi;
7327 struct atom_clock_dividers dividers; 7306 struct atom_clock_dividers dividers;
7328 int ret; 7307 int ret;
7329 u32 mask;
7330 7308
7331 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 7309 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7332 if (si_pi == NULL) 7310 if (si_pi == NULL)
@@ -7336,11 +7314,9 @@ static int si_dpm_init(struct amdgpu_device *adev)
7336 eg_pi = &ni_pi->eg; 7314 eg_pi = &ni_pi->eg;
7337 pi = &eg_pi->rv7xx; 7315 pi = &eg_pi->rv7xx;
7338 7316
7339 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); 7317 si_pi->sys_pcie_mask =
7340 if (ret) 7318 (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
7341 si_pi->sys_pcie_mask = 0; 7319 CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
7342 else
7343 si_pi->sys_pcie_mask = mask;
7344 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; 7320 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7345 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); 7321 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7346 7322
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index b2bfedaf57f1..9bab4842cd44 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1618,7 +1618,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
1618 .set_wptr = uvd_v6_0_enc_ring_set_wptr, 1618 .set_wptr = uvd_v6_0_enc_ring_set_wptr,
1619 .emit_frame_size = 1619 .emit_frame_size =
1620 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */ 1620 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
1621 6 + /* uvd_v6_0_enc_ring_emit_vm_flush */ 1621 5 + /* uvd_v6_0_enc_ring_emit_vm_flush */
1622 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */ 1622 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
1623 1, /* uvd_v6_0_enc_ring_insert_end */ 1623 1, /* uvd_v6_0_enc_ring_insert_end */
1624 .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */ 1624 .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1ce4c98385e3..c345e645f1d7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -629,11 +629,13 @@ static int dm_resume(void *handle)
629{ 629{
630 struct amdgpu_device *adev = handle; 630 struct amdgpu_device *adev = handle;
631 struct amdgpu_display_manager *dm = &adev->dm; 631 struct amdgpu_display_manager *dm = &adev->dm;
632 int ret = 0;
632 633
633 /* power on hardware */ 634 /* power on hardware */
634 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 635 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
635 636
636 return 0; 637 ret = amdgpu_dm_display_resume(adev);
638 return ret;
637} 639}
638 640
639int amdgpu_dm_display_resume(struct amdgpu_device *adev) 641int amdgpu_dm_display_resume(struct amdgpu_device *adev)
@@ -1035,6 +1037,10 @@ static void handle_hpd_rx_irq(void *param)
1035 !is_mst_root_connector) { 1037 !is_mst_root_connector) {
1036 /* Downstream Port status changed. */ 1038 /* Downstream Port status changed. */
1037 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { 1039 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1040
1041 if (aconnector->fake_enable)
1042 aconnector->fake_enable = false;
1043
1038 amdgpu_dm_update_connector_after_detect(aconnector); 1044 amdgpu_dm_update_connector_after_detect(aconnector);
1039 1045
1040 1046
@@ -2010,30 +2016,32 @@ static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2010 dst.width = stream->timing.h_addressable; 2016 dst.width = stream->timing.h_addressable;
2011 dst.height = stream->timing.v_addressable; 2017 dst.height = stream->timing.v_addressable;
2012 2018
2013 rmx_type = dm_state->scaling; 2019 if (dm_state) {
2014 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 2020 rmx_type = dm_state->scaling;
2015 if (src.width * dst.height < 2021 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2016 src.height * dst.width) { 2022 if (src.width * dst.height <
2017 /* height needs less upscaling/more downscaling */ 2023 src.height * dst.width) {
2018 dst.width = src.width * 2024 /* height needs less upscaling/more downscaling */
2019 dst.height / src.height; 2025 dst.width = src.width *
2020 } else { 2026 dst.height / src.height;
2021 /* width needs less upscaling/more downscaling */ 2027 } else {
2022 dst.height = src.height * 2028 /* width needs less upscaling/more downscaling */
2023 dst.width / src.width; 2029 dst.height = src.height *
2030 dst.width / src.width;
2031 }
2032 } else if (rmx_type == RMX_CENTER) {
2033 dst = src;
2024 } 2034 }
2025 } else if (rmx_type == RMX_CENTER) {
2026 dst = src;
2027 }
2028 2035
2029 dst.x = (stream->timing.h_addressable - dst.width) / 2; 2036 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2030 dst.y = (stream->timing.v_addressable - dst.height) / 2; 2037 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2031 2038
2032 if (dm_state->underscan_enable) { 2039 if (dm_state->underscan_enable) {
2033 dst.x += dm_state->underscan_hborder / 2; 2040 dst.x += dm_state->underscan_hborder / 2;
2034 dst.y += dm_state->underscan_vborder / 2; 2041 dst.y += dm_state->underscan_vborder / 2;
2035 dst.width -= dm_state->underscan_hborder; 2042 dst.width -= dm_state->underscan_hborder;
2036 dst.height -= dm_state->underscan_vborder; 2043 dst.height -= dm_state->underscan_vborder;
2044 }
2037 } 2045 }
2038 2046
2039 stream->src = src; 2047 stream->src = src;
@@ -2358,12 +2366,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2358 2366
2359 if (aconnector == NULL) { 2367 if (aconnector == NULL) {
2360 DRM_ERROR("aconnector is NULL!\n"); 2368 DRM_ERROR("aconnector is NULL!\n");
2361 goto drm_connector_null; 2369 return stream;
2362 }
2363
2364 if (dm_state == NULL) {
2365 DRM_ERROR("dm_state is NULL!\n");
2366 goto dm_state_null;
2367 } 2370 }
2368 2371
2369 drm_connector = &aconnector->base; 2372 drm_connector = &aconnector->base;
@@ -2375,18 +2378,18 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2375 */ 2378 */
2376 if (aconnector->mst_port) { 2379 if (aconnector->mst_port) {
2377 dm_dp_mst_dc_sink_create(drm_connector); 2380 dm_dp_mst_dc_sink_create(drm_connector);
2378 goto mst_dc_sink_create_done; 2381 return stream;
2379 } 2382 }
2380 2383
2381 if (create_fake_sink(aconnector)) 2384 if (create_fake_sink(aconnector))
2382 goto stream_create_fail; 2385 return stream;
2383 } 2386 }
2384 2387
2385 stream = dc_create_stream_for_sink(aconnector->dc_sink); 2388 stream = dc_create_stream_for_sink(aconnector->dc_sink);
2386 2389
2387 if (stream == NULL) { 2390 if (stream == NULL) {
2388 DRM_ERROR("Failed to create stream for sink!\n"); 2391 DRM_ERROR("Failed to create stream for sink!\n");
2389 goto stream_create_fail; 2392 return stream;
2390 } 2393 }
2391 2394
2392 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 2395 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
@@ -2412,9 +2415,12 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2412 } else { 2415 } else {
2413 decide_crtc_timing_for_drm_display_mode( 2416 decide_crtc_timing_for_drm_display_mode(
2414 &mode, preferred_mode, 2417 &mode, preferred_mode,
2415 dm_state->scaling != RMX_OFF); 2418 dm_state ? (dm_state->scaling != RMX_OFF) : false);
2416 } 2419 }
2417 2420
2421 if (!dm_state)
2422 drm_mode_set_crtcinfo(&mode, 0);
2423
2418 fill_stream_properties_from_drm_display_mode(stream, 2424 fill_stream_properties_from_drm_display_mode(stream,
2419 &mode, &aconnector->base); 2425 &mode, &aconnector->base);
2420 update_stream_scaling_settings(&mode, dm_state, stream); 2426 update_stream_scaling_settings(&mode, dm_state, stream);
@@ -2424,10 +2430,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2424 drm_connector, 2430 drm_connector,
2425 aconnector->dc_sink); 2431 aconnector->dc_sink);
2426 2432
2427stream_create_fail: 2433 update_stream_signal(stream);
2428dm_state_null: 2434
2429drm_connector_null:
2430mst_dc_sink_create_done:
2431 return stream; 2435 return stream;
2432} 2436}
2433 2437
@@ -2495,6 +2499,27 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
2495 return &state->base; 2499 return &state->base;
2496} 2500}
2497 2501
2502
2503static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
2504{
2505 enum dc_irq_source irq_source;
2506 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2507 struct amdgpu_device *adev = crtc->dev->dev_private;
2508
2509 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2510 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2511}
2512
2513static int dm_enable_vblank(struct drm_crtc *crtc)
2514{
2515 return dm_set_vblank(crtc, true);
2516}
2517
2518static void dm_disable_vblank(struct drm_crtc *crtc)
2519{
2520 dm_set_vblank(crtc, false);
2521}
2522
2498/* Implemented only the options currently availible for the driver */ 2523/* Implemented only the options currently availible for the driver */
2499static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 2524static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2500 .reset = dm_crtc_reset_state, 2525 .reset = dm_crtc_reset_state,
@@ -2504,6 +2529,8 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2504 .page_flip = drm_atomic_helper_page_flip, 2529 .page_flip = drm_atomic_helper_page_flip,
2505 .atomic_duplicate_state = dm_crtc_duplicate_state, 2530 .atomic_duplicate_state = dm_crtc_duplicate_state,
2506 .atomic_destroy_state = dm_crtc_destroy_state, 2531 .atomic_destroy_state = dm_crtc_destroy_state,
2532 .enable_vblank = dm_enable_vblank,
2533 .disable_vblank = dm_disable_vblank,
2507}; 2534};
2508 2535
2509static enum drm_connector_status 2536static enum drm_connector_status
@@ -2798,7 +2825,7 @@ int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2798 goto fail; 2825 goto fail;
2799 } 2826 }
2800 2827
2801 stream = dc_create_stream_for_sink(dc_sink); 2828 stream = create_stream_for_sink(aconnector, mode, NULL);
2802 if (stream == NULL) { 2829 if (stream == NULL) {
2803 DRM_ERROR("Failed to create stream for sink!\n"); 2830 DRM_ERROR("Failed to create stream for sink!\n");
2804 goto fail; 2831 goto fail;
@@ -3058,6 +3085,9 @@ static int dm_plane_atomic_check(struct drm_plane *plane,
3058 if (!dm_plane_state->dc_state) 3085 if (!dm_plane_state->dc_state)
3059 return 0; 3086 return 0;
3060 3087
3088 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3089 return -EINVAL;
3090
3061 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 3091 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
3062 return 0; 3092 return 0;
3063 3093
@@ -4630,8 +4660,6 @@ static int dm_update_planes_state(struct dc *dc,
4630 bool pflip_needed = !state->allow_modeset; 4660 bool pflip_needed = !state->allow_modeset;
4631 int ret = 0; 4661 int ret = 0;
4632 4662
4633 if (pflip_needed)
4634 return ret;
4635 4663
4636 /* Add new planes */ 4664 /* Add new planes */
4637 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 4665 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
@@ -4646,6 +4674,8 @@ static int dm_update_planes_state(struct dc *dc,
4646 4674
4647 /* Remove any changed/removed planes */ 4675 /* Remove any changed/removed planes */
4648 if (!enable) { 4676 if (!enable) {
4677 if (pflip_needed)
4678 continue;
4649 4679
4650 if (!old_plane_crtc) 4680 if (!old_plane_crtc)
4651 continue; 4681 continue;
@@ -4677,6 +4707,7 @@ static int dm_update_planes_state(struct dc *dc,
4677 *lock_and_validation_needed = true; 4707 *lock_and_validation_needed = true;
4678 4708
4679 } else { /* Add new planes */ 4709 } else { /* Add new planes */
4710 struct dc_plane_state *dc_new_plane_state;
4680 4711
4681 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 4712 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4682 continue; 4713 continue;
@@ -4690,38 +4721,50 @@ static int dm_update_planes_state(struct dc *dc,
4690 if (!dm_new_crtc_state->stream) 4721 if (!dm_new_crtc_state->stream)
4691 continue; 4722 continue;
4692 4723
4724 if (pflip_needed)
4725 continue;
4693 4726
4694 WARN_ON(dm_new_plane_state->dc_state); 4727 WARN_ON(dm_new_plane_state->dc_state);
4695 4728
4696 dm_new_plane_state->dc_state = dc_create_plane_state(dc); 4729 dc_new_plane_state = dc_create_plane_state(dc);
4697 4730 if (!dc_new_plane_state) {
4698 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
4699 plane->base.id, new_plane_crtc->base.id);
4700
4701 if (!dm_new_plane_state->dc_state) {
4702 ret = -EINVAL; 4731 ret = -EINVAL;
4703 return ret; 4732 return ret;
4704 } 4733 }
4705 4734
4735 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
4736 plane->base.id, new_plane_crtc->base.id);
4737
4706 ret = fill_plane_attributes( 4738 ret = fill_plane_attributes(
4707 new_plane_crtc->dev->dev_private, 4739 new_plane_crtc->dev->dev_private,
4708 dm_new_plane_state->dc_state, 4740 dc_new_plane_state,
4709 new_plane_state, 4741 new_plane_state,
4710 new_crtc_state); 4742 new_crtc_state);
4711 if (ret) 4743 if (ret) {
4744 dc_plane_state_release(dc_new_plane_state);
4712 return ret; 4745 return ret;
4746 }
4713 4747
4714 4748 /*
4749 * Any atomic check errors that occur after this will
4750 * not need a release. The plane state will be attached
4751 * to the stream, and therefore part of the atomic
4752 * state. It'll be released when the atomic state is
4753 * cleaned.
4754 */
4715 if (!dc_add_plane_to_context( 4755 if (!dc_add_plane_to_context(
4716 dc, 4756 dc,
4717 dm_new_crtc_state->stream, 4757 dm_new_crtc_state->stream,
4718 dm_new_plane_state->dc_state, 4758 dc_new_plane_state,
4719 dm_state->context)) { 4759 dm_state->context)) {
4720 4760
4761 dc_plane_state_release(dc_new_plane_state);
4721 ret = -EINVAL; 4762 ret = -EINVAL;
4722 return ret; 4763 return ret;
4723 } 4764 }
4724 4765
4766 dm_new_plane_state->dc_state = dc_new_plane_state;
4767
4725 /* Tell DC to do a full surface update every time there 4768 /* Tell DC to do a full surface update every time there
4726 * is a plane change. Inefficient, but works for now. 4769 * is a plane change. Inefficient, but works for now.
4727 */ 4770 */
@@ -4735,6 +4778,30 @@ static int dm_update_planes_state(struct dc *dc,
4735 return ret; 4778 return ret;
4736} 4779}
4737 4780
4781static int dm_atomic_check_plane_state_fb(struct drm_atomic_state *state,
4782 struct drm_crtc *crtc)
4783{
4784 struct drm_plane *plane;
4785 struct drm_crtc_state *crtc_state;
4786
4787 WARN_ON(!drm_atomic_get_new_crtc_state(state, crtc));
4788
4789 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
4790 struct drm_plane_state *plane_state =
4791 drm_atomic_get_plane_state(state, plane);
4792
4793 if (IS_ERR(plane_state))
4794 return -EDEADLK;
4795
4796 crtc_state = drm_atomic_get_crtc_state(plane_state->state, crtc);
4797 if (crtc->primary == plane && crtc_state->active) {
4798 if (!plane_state->fb)
4799 return -EINVAL;
4800 }
4801 }
4802 return 0;
4803}
4804
4738static int amdgpu_dm_atomic_check(struct drm_device *dev, 4805static int amdgpu_dm_atomic_check(struct drm_device *dev,
4739 struct drm_atomic_state *state) 4806 struct drm_atomic_state *state)
4740{ 4807{
@@ -4758,6 +4825,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
4758 goto fail; 4825 goto fail;
4759 4826
4760 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4827 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4828 ret = dm_atomic_check_plane_state_fb(state, crtc);
4829 if (ret)
4830 goto fail;
4831
4761 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 4832 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
4762 !new_crtc_state->color_mgmt_changed) 4833 !new_crtc_state->color_mgmt_changed)
4763 continue; 4834 continue;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 1874b6cee6af..422055080df4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -683,10 +683,8 @@ static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = {
683 683
684void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev) 684void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
685{ 685{
686 if (adev->mode_info.num_crtc > 0) 686
687 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; 687 adev->crtc_irq.num_types = adev->mode_info.num_crtc;
688 else
689 adev->crtc_irq.num_types = 0;
690 adev->crtc_irq.funcs = &dm_crtc_irq_funcs; 688 adev->crtc_irq.funcs = &dm_crtc_irq_funcs;
691 689
692 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; 690 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index f3d87f418d2e..93421dad21bd 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -189,6 +189,12 @@ void dm_dp_mst_dc_sink_create(struct drm_connector *connector)
189 .link = aconnector->dc_link, 189 .link = aconnector->dc_link,
190 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; 190 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
191 191
192 /*
193 * TODO: Need to further figure out why ddc.algo is NULL while MST port exists
194 */
195 if (!aconnector->port || !aconnector->port->aux.ddc.algo)
196 return;
197
192 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port); 198 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
193 199
194 if (!edid) { 200 if (!edid) {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 35e84ed031de..12868c769606 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1358,13 +1358,13 @@ enum dc_irq_source dc_interrupt_to_irq_source(
1358 return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id); 1358 return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
1359} 1359}
1360 1360
1361void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable) 1361bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
1362{ 1362{
1363 1363
1364 if (dc == NULL) 1364 if (dc == NULL)
1365 return; 1365 return false;
1366 1366
1367 dal_irq_service_set(dc->res_pool->irqs, src, enable); 1367 return dal_irq_service_set(dc->res_pool->irqs, src, enable);
1368} 1368}
1369 1369
1370void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src) 1370void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index a37428271573..be5546181fa8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1749,8 +1749,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
1749 link->link_enc, 1749 link->link_enc,
1750 pipe_ctx->clock_source->id, 1750 pipe_ctx->clock_source->id,
1751 display_color_depth, 1751 display_color_depth,
1752 pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A, 1752 pipe_ctx->stream->signal,
1753 pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK,
1754 stream->phy_pix_clk); 1753 stream->phy_pix_clk);
1755 1754
1756 if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 1755 if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 61e8c3e02d16..639421a00ab6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -718,7 +718,7 @@ static enum link_training_result perform_channel_equalization_sequence(
718 uint32_t retries_ch_eq; 718 uint32_t retries_ch_eq;
719 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; 719 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
720 union lane_align_status_updated dpcd_lane_status_updated = {{0}}; 720 union lane_align_status_updated dpcd_lane_status_updated = {{0}};
721 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {{{0}}};; 721 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {{{0}}};
722 722
723 hw_tr_pattern = get_supported_tp(link); 723 hw_tr_pattern = get_supported_tp(link);
724 724
@@ -1465,7 +1465,7 @@ void decide_link_settings(struct dc_stream_state *stream,
1465 /* MST doesn't perform link training for now 1465 /* MST doesn't perform link training for now
1466 * TODO: add MST specific link training routine 1466 * TODO: add MST specific link training routine
1467 */ 1467 */
1468 if (is_mst_supported(link)) { 1468 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1469 *link_setting = link->verified_link_cap; 1469 *link_setting = link->verified_link_cap;
1470 return; 1470 return;
1471 } 1471 }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 95b8dd0e53c6..4d07ffebfd31 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1360,9 +1360,6 @@ bool dc_is_stream_scaling_unchanged(
1360 return true; 1360 return true;
1361} 1361}
1362 1362
1363/* Maximum TMDS single link pixel clock 165MHz */
1364#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
1365
1366static void update_stream_engine_usage( 1363static void update_stream_engine_usage(
1367 struct resource_context *res_ctx, 1364 struct resource_context *res_ctx,
1368 const struct resource_pool *pool, 1365 const struct resource_pool *pool,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 261811e0c094..cd5819789d76 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -33,8 +33,7 @@
33/******************************************************************************* 33/*******************************************************************************
34 * Private functions 34 * Private functions
35 ******************************************************************************/ 35 ******************************************************************************/
36#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000 36void update_stream_signal(struct dc_stream_state *stream)
37static void update_stream_signal(struct dc_stream_state *stream)
38{ 37{
39 38
40 struct dc_sink *dc_sink = stream->sink; 39 struct dc_sink *dc_sink = stream->sink;
@@ -45,8 +44,9 @@ static void update_stream_signal(struct dc_stream_state *stream)
45 stream->signal = dc_sink->sink_signal; 44 stream->signal = dc_sink->sink_signal;
46 45
47 if (dc_is_dvi_signal(stream->signal)) { 46 if (dc_is_dvi_signal(stream->signal)) {
48 if (stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST && 47 if (stream->ctx->dc->caps.dual_link_dvi &&
49 stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) 48 stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK &&
49 stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
50 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK; 50 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
51 else 51 else
52 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 52 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
@@ -193,44 +193,20 @@ bool dc_stream_set_cursor_attributes(
193 193
194 core_dc = stream->ctx->dc; 194 core_dc = stream->ctx->dc;
195 res_ctx = &core_dc->current_state->res_ctx; 195 res_ctx = &core_dc->current_state->res_ctx;
196 stream->cursor_attributes = *attributes;
196 197
197 for (i = 0; i < MAX_PIPES; i++) { 198 for (i = 0; i < MAX_PIPES; i++) {
198 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 199 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
199 200
200 if (pipe_ctx->stream != stream || (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp)) 201 if (pipe_ctx->stream != stream || (!pipe_ctx->plane_res.xfm &&
202 !pipe_ctx->plane_res.dpp) || !pipe_ctx->plane_res.ipp)
201 continue; 203 continue;
202 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 204 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
203 continue; 205 continue;
204 206
205 207
206 if (pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes != NULL) 208 core_dc->hwss.set_cursor_attribute(pipe_ctx);
207 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
208 pipe_ctx->plane_res.ipp, attributes);
209
210 if (pipe_ctx->plane_res.hubp != NULL &&
211 pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes != NULL)
212 pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
213 pipe_ctx->plane_res.hubp, attributes);
214
215 if (pipe_ctx->plane_res.mi != NULL &&
216 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes != NULL)
217 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
218 pipe_ctx->plane_res.mi, attributes);
219
220
221 if (pipe_ctx->plane_res.xfm != NULL &&
222 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes != NULL)
223 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
224 pipe_ctx->plane_res.xfm, attributes);
225
226 if (pipe_ctx->plane_res.dpp != NULL &&
227 pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes != NULL)
228 pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
229 pipe_ctx->plane_res.dpp, attributes->color_format);
230 } 209 }
231
232 stream->cursor_attributes = *attributes;
233
234 return true; 210 return true;
235} 211}
236 212
@@ -254,55 +230,21 @@ bool dc_stream_set_cursor_position(
254 230
255 core_dc = stream->ctx->dc; 231 core_dc = stream->ctx->dc;
256 res_ctx = &core_dc->current_state->res_ctx; 232 res_ctx = &core_dc->current_state->res_ctx;
233 stream->cursor_position = *position;
257 234
258 for (i = 0; i < MAX_PIPES; i++) { 235 for (i = 0; i < MAX_PIPES; i++) {
259 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 236 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
260 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
261 struct mem_input *mi = pipe_ctx->plane_res.mi;
262 struct hubp *hubp = pipe_ctx->plane_res.hubp;
263 struct dpp *dpp = pipe_ctx->plane_res.dpp;
264 struct dc_cursor_position pos_cpy = *position;
265 struct dc_cursor_mi_param param = {
266 .pixel_clk_khz = stream->timing.pix_clk_khz,
267 .ref_clk_khz = core_dc->res_pool->ref_clock_inKhz,
268 .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
269 .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
270 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
271 };
272 237
273 if (pipe_ctx->stream != stream || 238 if (pipe_ctx->stream != stream ||
274 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || 239 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||
275 !pipe_ctx->plane_state || 240 !pipe_ctx->plane_state ||
276 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp)) 241 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||
277 continue; 242 !pipe_ctx->plane_res.ipp)
278
279 if (pipe_ctx->plane_state->address.type
280 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
281 pos_cpy.enable = false;
282
283 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
284 pos_cpy.enable = false;
285
286
287 if (ipp != NULL && ipp->funcs->ipp_cursor_set_position != NULL)
288 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
289
290 if (mi != NULL && mi->funcs->set_cursor_position != NULL)
291 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
292
293 if (!hubp)
294 continue; 243 continue;
295 244
296 if (hubp->funcs->set_cursor_position != NULL) 245 core_dc->hwss.set_cursor_position(pipe_ctx);
297 hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
298
299 if (dpp != NULL && dpp->funcs->set_cursor_position != NULL)
300 dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);
301
302 } 246 }
303 247
304 stream->cursor_position = *position;
305
306 return true; 248 return true;
307} 249}
308 250
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e2e3c9df79ea..d6d56611604e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -62,6 +62,7 @@ struct dc_caps {
62 bool dcc_const_color; 62 bool dcc_const_color;
63 bool dynamic_audio; 63 bool dynamic_audio;
64 bool is_apu; 64 bool is_apu;
65 bool dual_link_dvi;
65}; 66};
66 67
67struct dc_dcc_surface_param { 68struct dc_dcc_surface_param {
@@ -672,7 +673,7 @@ enum dc_irq_source dc_interrupt_to_irq_source(
672 struct dc *dc, 673 struct dc *dc,
673 uint32_t src_id, 674 uint32_t src_id,
674 uint32_t ext_id); 675 uint32_t ext_id);
675void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 676bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
676void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 677void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
677enum dc_irq_source dc_get_hpd_irq_source_at_index( 678enum dc_irq_source dc_get_hpd_irq_source_at_index(
678 struct dc *dc, uint32_t link_index); 679 struct dc *dc, uint32_t link_index);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 01c60f11b2bd..456e4d29eadd 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -237,6 +237,8 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
237 */ 237 */
238struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); 238struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
239 239
240void update_stream_signal(struct dc_stream_state *stream);
241
240void dc_stream_retain(struct dc_stream_state *dc_stream); 242void dc_stream_retain(struct dc_stream_state *dc_stream);
241void dc_stream_release(struct dc_stream_state *dc_stream); 243void dc_stream_release(struct dc_stream_state *dc_stream);
242 244
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index b73db9e78437..a993279a8f2d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -236,6 +236,7 @@
236 SR(D2VGA_CONTROL), \ 236 SR(D2VGA_CONTROL), \
237 SR(D3VGA_CONTROL), \ 237 SR(D3VGA_CONTROL), \
238 SR(D4VGA_CONTROL), \ 238 SR(D4VGA_CONTROL), \
239 SR(VGA_TEST_CONTROL), \
239 SR(DC_IP_REQUEST_CNTL), \ 240 SR(DC_IP_REQUEST_CNTL), \
240 BL_REG_LIST() 241 BL_REG_LIST()
241 242
@@ -337,6 +338,7 @@ struct dce_hwseq_registers {
337 uint32_t D2VGA_CONTROL; 338 uint32_t D2VGA_CONTROL;
338 uint32_t D3VGA_CONTROL; 339 uint32_t D3VGA_CONTROL;
339 uint32_t D4VGA_CONTROL; 340 uint32_t D4VGA_CONTROL;
341 uint32_t VGA_TEST_CONTROL;
340 /* MMHUB registers. read only. temporary hack */ 342 /* MMHUB registers. read only. temporary hack */
341 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; 343 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
342 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 344 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
@@ -493,6 +495,9 @@ struct dce_hwseq_registers {
493 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 495 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
494 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 496 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
495 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 497 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
498 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
499 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
500 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
496 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 501 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
497 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 502 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
498 503
@@ -583,7 +588,10 @@ struct dce_hwseq_registers {
583 type DCFCLK_GATE_DIS; \ 588 type DCFCLK_GATE_DIS; \
584 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ 589 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
585 type DENTIST_DPPCLK_WDIVIDER; \ 590 type DENTIST_DPPCLK_WDIVIDER; \
586 type DENTIST_DISPCLK_WDIVIDER; 591 type DENTIST_DISPCLK_WDIVIDER; \
592 type VGA_TEST_ENABLE; \
593 type VGA_TEST_RENDER_START; \
594 type D1VGA_MODE_ENABLE;
587 595
588struct dce_hwseq_shift { 596struct dce_hwseq_shift {
589 HWSEQ_REG_FIELD_LIST(uint8_t) 597 HWSEQ_REG_FIELD_LIST(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index a266e3f5e75f..e4741f1a2b01 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -82,13 +82,6 @@
82#define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20 82#define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
83#define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40 83#define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40
84 84
85/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
86#define TMDS_MIN_PIXEL_CLOCK 25000
87/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
88#define TMDS_MAX_PIXEL_CLOCK 165000
89/* For current ASICs pixel clock - 600MHz */
90#define MAX_ENCODER_CLOCK 600000
91
92enum { 85enum {
93 DP_MST_UPDATE_MAX_RETRY = 50 86 DP_MST_UPDATE_MAX_RETRY = 50
94}; 87};
@@ -683,6 +676,7 @@ void dce110_link_encoder_construct(
683{ 676{
684 struct bp_encoder_cap_info bp_cap_info = {0}; 677 struct bp_encoder_cap_info bp_cap_info = {0};
685 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 678 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
679 enum bp_result result = BP_RESULT_OK;
686 680
687 enc110->base.funcs = &dce110_lnk_enc_funcs; 681 enc110->base.funcs = &dce110_lnk_enc_funcs;
688 enc110->base.ctx = init_data->ctx; 682 enc110->base.ctx = init_data->ctx;
@@ -757,15 +751,24 @@ void dce110_link_encoder_construct(
757 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 751 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
758 } 752 }
759 753
754 /* default to one to mirror Windows behavior */
755 enc110->base.features.flags.bits.HDMI_6GB_EN = 1;
756
757 result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios,
758 enc110->base.id, &bp_cap_info);
759
760 /* Override features with DCE-specific values */ 760 /* Override features with DCE-specific values */
761 if (BP_RESULT_OK == bp_funcs->get_encoder_cap_info( 761 if (BP_RESULT_OK == result) {
762 enc110->base.ctx->dc_bios, enc110->base.id,
763 &bp_cap_info)) {
764 enc110->base.features.flags.bits.IS_HBR2_CAPABLE = 762 enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
765 bp_cap_info.DP_HBR2_EN; 763 bp_cap_info.DP_HBR2_EN;
766 enc110->base.features.flags.bits.IS_HBR3_CAPABLE = 764 enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
767 bp_cap_info.DP_HBR3_EN; 765 bp_cap_info.DP_HBR3_EN;
768 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 766 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
767 } else {
768 dm_logger_write(enc110->base.ctx->logger, LOG_WARNING,
769 "%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
770 __func__,
771 result);
769 } 772 }
770} 773}
771 774
@@ -904,8 +907,7 @@ void dce110_link_encoder_enable_tmds_output(
904 struct link_encoder *enc, 907 struct link_encoder *enc,
905 enum clock_source_id clock_source, 908 enum clock_source_id clock_source,
906 enum dc_color_depth color_depth, 909 enum dc_color_depth color_depth,
907 bool hdmi, 910 enum signal_type signal,
908 bool dual_link,
909 uint32_t pixel_clock) 911 uint32_t pixel_clock)
910{ 912{
911 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 913 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
@@ -919,16 +921,12 @@ void dce110_link_encoder_enable_tmds_output(
919 cntl.engine_id = enc->preferred_engine; 921 cntl.engine_id = enc->preferred_engine;
920 cntl.transmitter = enc110->base.transmitter; 922 cntl.transmitter = enc110->base.transmitter;
921 cntl.pll_id = clock_source; 923 cntl.pll_id = clock_source;
922 if (hdmi) { 924 cntl.signal = signal;
923 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 925 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
924 cntl.lanes_number = 4;
925 } else if (dual_link) {
926 cntl.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
927 cntl.lanes_number = 8; 926 cntl.lanes_number = 8;
928 } else { 927 else
929 cntl.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
930 cntl.lanes_number = 4; 928 cntl.lanes_number = 4;
931 } 929
932 cntl.hpd_sel = enc110->base.hpd_source; 930 cntl.hpd_sel = enc110->base.hpd_source;
933 931
934 cntl.pixel_clock = pixel_clock; 932 cntl.pixel_clock = pixel_clock;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index 8ca9afe47a2b..0ec3433d34b6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -210,8 +210,7 @@ void dce110_link_encoder_enable_tmds_output(
210 struct link_encoder *enc, 210 struct link_encoder *enc,
211 enum clock_source_id clock_source, 211 enum clock_source_id clock_source,
212 enum dc_color_depth color_depth, 212 enum dc_color_depth color_depth,
213 bool hdmi, 213 enum signal_type signal,
214 bool dual_link,
215 uint32_t pixel_clock); 214 uint32_t pixel_clock);
216 215
217/* enables DP PHY output */ 216/* enables DP PHY output */
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 3ea43e2a9450..442dd2d93618 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -852,6 +852,7 @@ static bool construct(
852 dc->caps.max_downscale_ratio = 200; 852 dc->caps.max_downscale_ratio = 200;
853 dc->caps.i2c_speed_in_khz = 40; 853 dc->caps.i2c_speed_in_khz = 40;
854 dc->caps.max_cursor_size = 128; 854 dc->caps.max_cursor_size = 128;
855 dc->caps.dual_link_dvi = true;
855 856
856 for (i = 0; i < pool->base.pipe_count; i++) { 857 for (i = 0; i < pool->base.pipe_count; i++) {
857 pool->base.timing_generators[i] = 858 pool->base.timing_generators[i] =
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 86cdd7b4811f..6f382a3ac90f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -688,15 +688,22 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
688 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 688 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
689 struct dc_link *link = pipe_ctx->stream->sink->link; 689 struct dc_link *link = pipe_ctx->stream->sink->link;
690 690
691 /* 1. update AVI info frame (HDMI, DP) 691
692 * we always need to update info frame
693 */
694 uint32_t active_total_with_borders; 692 uint32_t active_total_with_borders;
695 uint32_t early_control = 0; 693 uint32_t early_control = 0;
696 struct timing_generator *tg = pipe_ctx->stream_res.tg; 694 struct timing_generator *tg = pipe_ctx->stream_res.tg;
697 695
698 /* TODOFPGA may change to hwss.update_info_frame */ 696 /* For MST, there are multiply stream go to only one link.
697 * connect DIG back_end to front_end while enable_stream and
698 * disconnect them during disable_stream
699 * BY this, it is logic clean to separate stream and link */
700 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
701 pipe_ctx->stream_res.stream_enc->id, true);
702
703 /* update AVI info frame (HDMI, DP)*/
704 /* TODO: FPGA may change to hwss.update_info_frame */
699 dce110_update_info_frame(pipe_ctx); 705 dce110_update_info_frame(pipe_ctx);
706
700 /* enable early control to avoid corruption on DP monitor*/ 707 /* enable early control to avoid corruption on DP monitor*/
701 active_total_with_borders = 708 active_total_with_borders =
702 timing->h_addressable 709 timing->h_addressable
@@ -717,12 +724,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
717 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 724 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
718 } 725 }
719 726
720 /* For MST, there are multiply stream go to only one link. 727
721 * connect DIG back_end to front_end while enable_stream and 728
722 * disconnect them during disable_stream
723 * BY this, it is logic clean to separate stream and link */
724 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
725 pipe_ctx->stream_res.stream_enc->id, true);
726 729
727} 730}
728 731
@@ -1690,9 +1693,13 @@ static void apply_min_clocks(
1690 * Check if FBC can be enabled 1693 * Check if FBC can be enabled
1691 */ 1694 */
1692static bool should_enable_fbc(struct dc *dc, 1695static bool should_enable_fbc(struct dc *dc,
1693 struct dc_state *context) 1696 struct dc_state *context,
1697 uint32_t *pipe_idx)
1694{ 1698{
1695 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[0]; 1699 uint32_t i;
1700 struct pipe_ctx *pipe_ctx = NULL;
1701 struct resource_context *res_ctx = &context->res_ctx;
1702
1696 1703
1697 ASSERT(dc->fbc_compressor); 1704 ASSERT(dc->fbc_compressor);
1698 1705
@@ -1704,6 +1711,14 @@ static bool should_enable_fbc(struct dc *dc,
1704 if (context->stream_count != 1) 1711 if (context->stream_count != 1)
1705 return false; 1712 return false;
1706 1713
1714 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1715 if (res_ctx->pipe_ctx[i].stream) {
1716 pipe_ctx = &res_ctx->pipe_ctx[i];
1717 *pipe_idx = i;
1718 break;
1719 }
1720 }
1721
1707 /* Only supports eDP */ 1722 /* Only supports eDP */
1708 if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP) 1723 if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
1709 return false; 1724 return false;
@@ -1729,11 +1744,14 @@ static bool should_enable_fbc(struct dc *dc,
1729static void enable_fbc(struct dc *dc, 1744static void enable_fbc(struct dc *dc,
1730 struct dc_state *context) 1745 struct dc_state *context)
1731{ 1746{
1732 if (should_enable_fbc(dc, context)) { 1747 uint32_t pipe_idx = 0;
1748
1749 if (should_enable_fbc(dc, context, &pipe_idx)) {
1733 /* Program GRPH COMPRESSED ADDRESS and PITCH */ 1750 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1734 struct compr_addr_and_pitch_params params = {0, 0, 0}; 1751 struct compr_addr_and_pitch_params params = {0, 0, 0};
1735 struct compressor *compr = dc->fbc_compressor; 1752 struct compressor *compr = dc->fbc_compressor;
1736 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[0]; 1753 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1754
1737 1755
1738 params.source_view_width = pipe_ctx->stream->timing.h_addressable; 1756 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
1739 params.source_view_height = pipe_ctx->stream->timing.v_addressable; 1757 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
@@ -2915,6 +2933,49 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
2915 } 2933 }
2916} 2934}
2917 2935
2936void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2937{
2938 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2939 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2940 struct mem_input *mi = pipe_ctx->plane_res.mi;
2941 struct dc_cursor_mi_param param = {
2942 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
2943 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
2944 .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
2945 .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
2946 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
2947 };
2948
2949 if (pipe_ctx->plane_state->address.type
2950 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2951 pos_cpy.enable = false;
2952
2953 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2954 pos_cpy.enable = false;
2955
2956 if (ipp->funcs->ipp_cursor_set_position)
2957 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2958 if (mi->funcs->set_cursor_position)
2959 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2960}
2961
2962void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2963{
2964 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2965
2966 if (pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2967 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2968 pipe_ctx->plane_res.ipp, attributes);
2969
2970 if (pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2971 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2972 pipe_ctx->plane_res.mi, attributes);
2973
2974 if (pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2975 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2976 pipe_ctx->plane_res.xfm, attributes);
2977}
2978
2918static void ready_shared_resources(struct dc *dc, struct dc_state *context) {} 2979static void ready_shared_resources(struct dc *dc, struct dc_state *context) {}
2919 2980
2920static void optimize_shared_resources(struct dc *dc) {} 2981static void optimize_shared_resources(struct dc *dc) {}
@@ -2957,6 +3018,8 @@ static const struct hw_sequencer_funcs dce110_funcs = {
2957 .edp_backlight_control = hwss_edp_backlight_control, 3018 .edp_backlight_control = hwss_edp_backlight_control,
2958 .edp_power_control = hwss_edp_power_control, 3019 .edp_power_control = hwss_edp_power_control,
2959 .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, 3020 .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
3021 .set_cursor_position = dce110_set_cursor_position,
3022 .set_cursor_attribute = dce110_set_cursor_attribute
2960}; 3023};
2961 3024
2962void dce110_hw_sequencer_construct(struct dc *dc) 3025void dce110_hw_sequencer_construct(struct dc *dc)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 7c4779578fb7..00f18c485e1e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -846,6 +846,16 @@ static bool dce110_validate_bandwidth(
846 return result; 846 return result;
847} 847}
848 848
849enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
850 struct dc_caps *caps)
851{
852 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) ||
853 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height))
854 return DC_FAIL_SURFACE_VALIDATE;
855
856 return DC_OK;
857}
858
849static bool dce110_validate_surface_sets( 859static bool dce110_validate_surface_sets(
850 struct dc_state *context) 860 struct dc_state *context)
851{ 861{
@@ -869,6 +879,13 @@ static bool dce110_validate_surface_sets(
869 plane->src_rect.height > 1080)) 879 plane->src_rect.height > 1080))
870 return false; 880 return false;
871 881
882 /* we don't have the logic to support underlay
883 * only yet so block the use case where we get
884 * NV12 plane as top layer
885 */
886 if (j == 0)
887 return false;
888
872 /* irrespective of plane format, 889 /* irrespective of plane format,
873 * stream should be RGB encoded 890 * stream should be RGB encoded
874 */ 891 */
@@ -1021,6 +1038,7 @@ static const struct resource_funcs dce110_res_pool_funcs = {
1021 .link_enc_create = dce110_link_encoder_create, 1038 .link_enc_create = dce110_link_encoder_create,
1022 .validate_guaranteed = dce110_validate_guaranteed, 1039 .validate_guaranteed = dce110_validate_guaranteed,
1023 .validate_bandwidth = dce110_validate_bandwidth, 1040 .validate_bandwidth = dce110_validate_bandwidth,
1041 .validate_plane = dce110_validate_plane,
1024 .acquire_idle_pipe_for_layer = dce110_acquire_underlay, 1042 .acquire_idle_pipe_for_layer = dce110_acquire_underlay,
1025 .add_stream_to_ctx = dce110_add_stream_to_ctx, 1043 .add_stream_to_ctx = dce110_add_stream_to_ctx,
1026 .validate_global = dce110_validate_global 1044 .validate_global = dce110_validate_global
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 663e0a047a4b..98d9cd0109e1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1103,6 +1103,8 @@ static bool construct(
1103 dc->caps.max_downscale_ratio = 200; 1103 dc->caps.max_downscale_ratio = 200;
1104 dc->caps.i2c_speed_in_khz = 100; 1104 dc->caps.i2c_speed_in_khz = 100;
1105 dc->caps.max_cursor_size = 128; 1105 dc->caps.max_cursor_size = 128;
1106 dc->caps.dual_link_dvi = true;
1107
1106 1108
1107 /************************************************* 1109 /*************************************************
1108 * Create resources * 1110 * Create resources *
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 57cd67359567..5aab01db28ee 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -835,6 +835,8 @@ static bool construct(
835 dc->caps.max_downscale_ratio = 200; 835 dc->caps.max_downscale_ratio = 200;
836 dc->caps.i2c_speed_in_khz = 100; 836 dc->caps.i2c_speed_in_khz = 100;
837 dc->caps.max_cursor_size = 128; 837 dc->caps.max_cursor_size = 128;
838 dc->caps.dual_link_dvi = true;
839
838 dc->debug = debug_defaults; 840 dc->debug = debug_defaults;
839 841
840 /************************************************* 842 /*************************************************
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 8f2bd56f3461..25d7eb1567ae 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -793,6 +793,7 @@ static bool dce80_construct(
793 dc->caps.max_downscale_ratio = 200; 793 dc->caps.max_downscale_ratio = 200;
794 dc->caps.i2c_speed_in_khz = 40; 794 dc->caps.i2c_speed_in_khz = 40;
795 dc->caps.max_cursor_size = 128; 795 dc->caps.max_cursor_size = 128;
796 dc->caps.dual_link_dvi = true;
796 797
797 /************************************************* 798 /*************************************************
798 * Create resources * 799 * Create resources *
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 82572863acab..072e4485e85e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -238,10 +238,24 @@ static void enable_power_gating_plane(
238static void disable_vga( 238static void disable_vga(
239 struct dce_hwseq *hws) 239 struct dce_hwseq *hws)
240{ 240{
241 unsigned int in_vga_mode = 0;
242
243 REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga_mode);
244
245 if (in_vga_mode == 0)
246 return;
247
241 REG_WRITE(D1VGA_CONTROL, 0); 248 REG_WRITE(D1VGA_CONTROL, 0);
242 REG_WRITE(D2VGA_CONTROL, 0); 249
243 REG_WRITE(D3VGA_CONTROL, 0); 250 /* HW Engineer's Notes:
244 REG_WRITE(D4VGA_CONTROL, 0); 251 * During switch from vga->extended, if we set the VGA_TEST_ENABLE and
252 * then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
253 *
254 * Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
255 * VGA_TEST_ENABLE, to leave it in the same state as before.
256 */
257 REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
258 REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
245} 259}
246 260
247static void dpp_pg_control( 261static void dpp_pg_control(
@@ -1761,6 +1775,11 @@ static void update_dchubp_dpp(
1761 &pipe_ctx->plane_res.scl_data.viewport_c); 1775 &pipe_ctx->plane_res.scl_data.viewport_c);
1762 } 1776 }
1763 1777
1778 if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1779 dc->hwss.set_cursor_position(pipe_ctx);
1780 dc->hwss.set_cursor_attribute(pipe_ctx);
1781 }
1782
1764 if (plane_state->update_flags.bits.full_update) { 1783 if (plane_state->update_flags.bits.full_update) {
1765 /*gamut remap*/ 1784 /*gamut remap*/
1766 program_gamut_remap(pipe_ctx); 1785 program_gamut_remap(pipe_ctx);
@@ -2296,7 +2315,7 @@ static bool dcn10_dummy_display_power_gating(
2296 return true; 2315 return true;
2297} 2316}
2298 2317
2299void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) 2318static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2300{ 2319{
2301 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2320 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2302 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2321 struct timing_generator *tg = pipe_ctx->stream_res.tg;
@@ -2316,12 +2335,46 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2316 } 2335 }
2317} 2336}
2318 2337
2319void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data) 2338static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2320{ 2339{
2321 if (hws->ctx->dc->res_pool->hubbub != NULL) 2340 if (hws->ctx->dc->res_pool->hubbub != NULL)
2322 hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data); 2341 hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
2323} 2342}
2324 2343
2344static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
2345{
2346 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2347 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2348 struct dpp *dpp = pipe_ctx->plane_res.dpp;
2349 struct dc_cursor_mi_param param = {
2350 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
2351 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
2352 .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
2353 .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
2354 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
2355 };
2356
2357 if (pipe_ctx->plane_state->address.type
2358 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2359 pos_cpy.enable = false;
2360
2361 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2362 pos_cpy.enable = false;
2363
2364 hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
2365 dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);
2366}
2367
2368static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2369{
2370 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2371
2372 pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
2373 pipe_ctx->plane_res.hubp, attributes);
2374 pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
2375 pipe_ctx->plane_res.dpp, attributes->color_format);
2376}
2377
2325static const struct hw_sequencer_funcs dcn10_funcs = { 2378static const struct hw_sequencer_funcs dcn10_funcs = {
2326 .program_gamut_remap = program_gamut_remap, 2379 .program_gamut_remap = program_gamut_remap,
2327 .program_csc_matrix = program_csc_matrix, 2380 .program_csc_matrix = program_csc_matrix,
@@ -2362,6 +2415,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
2362 .edp_backlight_control = hwss_edp_backlight_control, 2415 .edp_backlight_control = hwss_edp_backlight_control,
2363 .edp_power_control = hwss_edp_power_control, 2416 .edp_power_control = hwss_edp_power_control,
2364 .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, 2417 .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2418 .set_cursor_position = dcn10_set_cursor_position,
2419 .set_cursor_attribute = dcn10_set_cursor_attribute
2365}; 2420};
2366 2421
2367 2422
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 0fd329deacd8..54d8a1386142 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -123,8 +123,7 @@ struct link_encoder_funcs {
123 void (*enable_tmds_output)(struct link_encoder *enc, 123 void (*enable_tmds_output)(struct link_encoder *enc,
124 enum clock_source_id clock_source, 124 enum clock_source_id clock_source,
125 enum dc_color_depth color_depth, 125 enum dc_color_depth color_depth,
126 bool hdmi, 126 enum signal_type signal,
127 bool dual_link,
128 uint32_t pixel_clock); 127 uint32_t pixel_clock);
129 void (*enable_dp_output)(struct link_encoder *enc, 128 void (*enable_dp_output)(struct link_encoder *enc,
130 const struct dc_link_settings *link_settings, 129 const struct dc_link_settings *link_settings,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 4c0aa56f7bae..379c6ecd271a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -198,6 +198,9 @@ struct hw_sequencer_funcs {
198 bool enable); 198 bool enable);
199 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 199 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
200 200
201 void (*set_cursor_position)(struct pipe_ctx *pipe);
202 void (*set_cursor_attribute)(struct pipe_ctx *pipe);
203
201}; 204};
202 205
203void color_space_to_black_color( 206void color_space_to_black_color(
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
index f7e40b292dfb..d3e1923b01a8 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
@@ -217,7 +217,7 @@ bool dce110_vblank_set(
217 core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; 217 core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
218 218
219 if (enable) { 219 if (enable) {
220 if (!tg->funcs->arm_vert_intr(tg, 2)) { 220 if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {
221 DC_ERROR("Failed to get VBLANK!\n"); 221 DC_ERROR("Failed to get VBLANK!\n");
222 return false; 222 return false;
223 } 223 }
diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
index 57a54a7b89e5..1c079ba37c30 100644
--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
@@ -42,8 +42,7 @@ static void virtual_link_encoder_enable_tmds_output(
42 struct link_encoder *enc, 42 struct link_encoder *enc,
43 enum clock_source_id clock_source, 43 enum clock_source_id clock_source,
44 enum dc_color_depth color_depth, 44 enum dc_color_depth color_depth,
45 bool hdmi, 45 enum signal_type signal,
46 bool dual_link,
47 uint32_t pixel_clock) {} 46 uint32_t pixel_clock) {}
48 47
49static void virtual_link_encoder_enable_dp_output( 48static void virtual_link_encoder_enable_dp_output(
diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
index 7a9b43f84a31..36bbad594267 100644
--- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
+++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
@@ -419,11 +419,6 @@ struct bios_event_info {
419 bool backlight_changed; 419 bool backlight_changed;
420}; 420};
421 421
422enum {
423 HDMI_PIXEL_CLOCK_IN_KHZ_297 = 297000,
424 TMDS_PIXEL_CLOCK_IN_KHZ_165 = 165000
425};
426
427/* 422/*
428 * DFS-bypass flag 423 * DFS-bypass flag
429 */ 424 */
diff --git a/drivers/gpu/drm/amd/display/include/signal_types.h b/drivers/gpu/drm/amd/display/include/signal_types.h
index b5ebde642207..199c5db67cbc 100644
--- a/drivers/gpu/drm/amd/display/include/signal_types.h
+++ b/drivers/gpu/drm/amd/display/include/signal_types.h
@@ -26,6 +26,11 @@
26#ifndef __DC_SIGNAL_TYPES_H__ 26#ifndef __DC_SIGNAL_TYPES_H__
27#define __DC_SIGNAL_TYPES_H__ 27#define __DC_SIGNAL_TYPES_H__
28 28
29/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
30#define TMDS_MIN_PIXEL_CLOCK 25000
31/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
32#define TMDS_MAX_PIXEL_CLOCK 165000
33
29enum signal_type { 34enum signal_type {
30 SIGNAL_TYPE_NONE = 0L, /* no signal */ 35 SIGNAL_TYPE_NONE = 0L, /* no signal */
31 SIGNAL_TYPE_DVI_SINGLE_LINK = (1 << 0), 36 SIGNAL_TYPE_DVI_SINGLE_LINK = (1 << 0),
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 4c3223a4d62b..adb6e7b9280c 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -162,7 +162,7 @@ static int pp_hw_init(void *handle)
162 if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) { 162 if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
163 pr_err("smc start failed\n"); 163 pr_err("smc start failed\n");
164 hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); 164 hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
165 return -EINVAL;; 165 return -EINVAL;
166 } 166 }
167 if (ret == PP_DPM_DISABLED) 167 if (ret == PP_DPM_DISABLED)
168 goto exit; 168 goto exit;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 41e42beff213..08e8a793714f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2756,10 +2756,13 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
2756 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); 2756 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
2757 2757
2758 2758
2759 disable_mclk_switching = ((1 < info.display_count) || 2759 if (info.display_count == 0)
2760 disable_mclk_switching_for_frame_lock || 2760 disable_mclk_switching = false;
2761 smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) || 2761 else
2762 (mode_info.refresh_rate > 120)); 2762 disable_mclk_switching = ((1 < info.display_count) ||
2763 disable_mclk_switching_for_frame_lock ||
2764 smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
2765 (mode_info.refresh_rate > 120));
2763 2766
2764 sclk = smu7_ps->performance_levels[0].engine_clock; 2767 sclk = smu7_ps->performance_levels[0].engine_clock;
2765 mclk = smu7_ps->performance_levels[0].memory_clock; 2768 mclk = smu7_ps->performance_levels[0].memory_clock;
@@ -4534,13 +4537,6 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
4534 int tmp_result, result = 0; 4537 int tmp_result, result = 0;
4535 uint32_t sclk_mask = 0, mclk_mask = 0; 4538 uint32_t sclk_mask = 0, mclk_mask = 0;
4536 4539
4537 if (hwmgr->chip_id == CHIP_FIJI) {
4538 if (request->type == AMD_PP_GFX_PROFILE)
4539 smu7_enable_power_containment(hwmgr);
4540 else if (request->type == AMD_PP_COMPUTE_PROFILE)
4541 smu7_disable_power_containment(hwmgr);
4542 }
4543
4544 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO) 4540 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO)
4545 return -EINVAL; 4541 return -EINVAL;
4546 4542
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 2d55dabc77d4..5f9c3efb532f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3168,10 +3168,13 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3168 disable_mclk_switching_for_vr = PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR); 3168 disable_mclk_switching_for_vr = PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
3169 force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh); 3169 force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
3170 3170
3171 disable_mclk_switching = (info.display_count > 1) || 3171 if (info.display_count == 0)
3172 disable_mclk_switching_for_frame_lock || 3172 disable_mclk_switching = false;
3173 disable_mclk_switching_for_vr || 3173 else
3174 force_mclk_high; 3174 disable_mclk_switching = (info.display_count > 1) ||
3175 disable_mclk_switching_for_frame_lock ||
3176 disable_mclk_switching_for_vr ||
3177 force_mclk_high;
3175 3178
3176 sclk = vega10_ps->performance_levels[0].gfx_clock; 3179 sclk = vega10_ps->performance_levels[0].gfx_clock;
3177 mclk = vega10_ps->performance_levels[0].mem_clock; 3180 mclk = vega10_ps->performance_levels[0].mem_clock;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 18:11:59 -0400