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-rw-r--r--drivers/gpu/drm/amd/acp/include/acp_gfx_if.h1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c111
-rw-r--r--drivers/gpu/drm/amd/display/dc/os_types.h2
-rw-r--r--drivers/gpu/drm/amd/include/cgs_common.h1
-rw-r--r--drivers/gpu/drm/amd/include/cgs_linux.h119
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c46
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c75
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h7
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c35
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c48
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/hwmgr.h5
11 files changed, 86 insertions, 364 deletions
diff --git a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
index a72ddb2f69ac..feab8eb7f2a8 100644
--- a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
+++ b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
@@ -25,7 +25,6 @@
25#define _ACP_GFX_IF_H 25#define _ACP_GFX_IF_H
26 26
27#include <linux/types.h> 27#include <linux/types.h>
28#include "cgs_linux.h"
29#include "cgs_common.h" 28#include "cgs_common.h"
30 29
31int amd_acp_hw_init(struct cgs_device *cgs_device, 30int amd_acp_hw_init(struct cgs_device *cgs_device,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index a8a0fd927da2..71a57b2f7f04 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -28,7 +28,6 @@
28#include <linux/firmware.h> 28#include <linux/firmware.h>
29#include <drm/amdgpu_drm.h> 29#include <drm/amdgpu_drm.h>
30#include "amdgpu.h" 30#include "amdgpu.h"
31#include "cgs_linux.h"
32#include "atom.h" 31#include "atom.h"
33#include "amdgpu_ucode.h" 32#include "amdgpu_ucode.h"
34 33
@@ -182,109 +181,6 @@ static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigne
182 adev->mode_info.atom_context, table, args); 181 adev->mode_info.atom_context, table, args);
183} 182}
184 183
185struct cgs_irq_params {
186 unsigned src_id;
187 cgs_irq_source_set_func_t set;
188 cgs_irq_handler_func_t handler;
189 void *private_data;
190};
191
192static int cgs_set_irq_state(struct amdgpu_device *adev,
193 struct amdgpu_irq_src *src,
194 unsigned type,
195 enum amdgpu_interrupt_state state)
196{
197 struct cgs_irq_params *irq_params =
198 (struct cgs_irq_params *)src->data;
199 if (!irq_params)
200 return -EINVAL;
201 if (!irq_params->set)
202 return -EINVAL;
203 return irq_params->set(irq_params->private_data,
204 irq_params->src_id,
205 type,
206 (int)state);
207}
208
209static int cgs_process_irq(struct amdgpu_device *adev,
210 struct amdgpu_irq_src *source,
211 struct amdgpu_iv_entry *entry)
212{
213 struct cgs_irq_params *irq_params =
214 (struct cgs_irq_params *)source->data;
215 if (!irq_params)
216 return -EINVAL;
217 if (!irq_params->handler)
218 return -EINVAL;
219 return irq_params->handler(irq_params->private_data,
220 irq_params->src_id,
221 entry->iv_entry);
222}
223
224static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
225 .set = cgs_set_irq_state,
226 .process = cgs_process_irq,
227};
228
229static int amdgpu_cgs_add_irq_source(void *cgs_device,
230 unsigned client_id,
231 unsigned src_id,
232 unsigned num_types,
233 cgs_irq_source_set_func_t set,
234 cgs_irq_handler_func_t handler,
235 void *private_data)
236{
237 CGS_FUNC_ADEV;
238 int ret = 0;
239 struct cgs_irq_params *irq_params;
240 struct amdgpu_irq_src *source =
241 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
242 if (!source)
243 return -ENOMEM;
244 irq_params =
245 kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
246 if (!irq_params) {
247 kfree(source);
248 return -ENOMEM;
249 }
250 source->num_types = num_types;
251 source->funcs = &cgs_irq_funcs;
252 irq_params->src_id = src_id;
253 irq_params->set = set;
254 irq_params->handler = handler;
255 irq_params->private_data = private_data;
256 source->data = (void *)irq_params;
257 ret = amdgpu_irq_add_id(adev, client_id, src_id, source);
258 if (ret) {
259 kfree(irq_params);
260 kfree(source);
261 }
262
263 return ret;
264}
265
266static int amdgpu_cgs_irq_get(void *cgs_device, unsigned client_id,
267 unsigned src_id, unsigned type)
268{
269 CGS_FUNC_ADEV;
270
271 if (!adev->irq.client[client_id].sources)
272 return -EINVAL;
273
274 return amdgpu_irq_get(adev, adev->irq.client[client_id].sources[src_id], type);
275}
276
277static int amdgpu_cgs_irq_put(void *cgs_device, unsigned client_id,
278 unsigned src_id, unsigned type)
279{
280 CGS_FUNC_ADEV;
281
282 if (!adev->irq.client[client_id].sources)
283 return -EINVAL;
284
285 return amdgpu_irq_put(adev, adev->irq.client[client_id].sources[src_id], type);
286}
287
288static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device, 184static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
289 enum amd_ip_block_type block_type, 185 enum amd_ip_block_type block_type,
290 enum amd_clockgating_state state) 186 enum amd_clockgating_state state)
@@ -795,12 +691,6 @@ static const struct cgs_ops amdgpu_cgs_ops = {
795 .lock_grbm_idx = amdgpu_cgs_lock_grbm_idx, 691 .lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
796}; 692};
797 693
798static const struct cgs_os_ops amdgpu_cgs_os_ops = {
799 .add_irq_source = amdgpu_cgs_add_irq_source,
800 .irq_get = amdgpu_cgs_irq_get,
801 .irq_put = amdgpu_cgs_irq_put
802};
803
804struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev) 694struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
805{ 695{
806 struct amdgpu_cgs_device *cgs_device = 696 struct amdgpu_cgs_device *cgs_device =
@@ -812,7 +702,6 @@ struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
812 } 702 }
813 703
814 cgs_device->base.ops = &amdgpu_cgs_ops; 704 cgs_device->base.ops = &amdgpu_cgs_ops;
815 cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
816 cgs_device->adev = adev; 705 cgs_device->adev = adev;
817 706
818 return (struct cgs_device *)cgs_device; 707 return (struct cgs_device *)cgs_device;
diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h
index 1fcbc99e63b5..a407892905af 100644
--- a/drivers/gpu/drm/amd/display/dc/os_types.h
+++ b/drivers/gpu/drm/amd/display/dc/os_types.h
@@ -32,7 +32,7 @@
32 32
33#include <linux/kref.h> 33#include <linux/kref.h>
34 34
35#include "cgs_linux.h" 35#include "cgs_common.h"
36 36
37#if defined(__BIG_ENDIAN) && !defined(BIGENDIAN_CPU) 37#if defined(__BIG_ENDIAN) && !defined(BIGENDIAN_CPU)
38#define BIGENDIAN_CPU 38#define BIGENDIAN_CPU
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
index 6ff8f35123c2..f2814ae7ecdd 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -290,7 +290,6 @@ struct cgs_os_ops; /* To be define in OS-specific CGS header */
290struct cgs_device 290struct cgs_device
291{ 291{
292 const struct cgs_ops *ops; 292 const struct cgs_ops *ops;
293 const struct cgs_os_ops *os_ops;
294 /* to be embedded at the start of driver private structure */ 293 /* to be embedded at the start of driver private structure */
295}; 294};
296 295
diff --git a/drivers/gpu/drm/amd/include/cgs_linux.h b/drivers/gpu/drm/amd/include/cgs_linux.h
deleted file mode 100644
index bc7446c1d22e..000000000000
--- a/drivers/gpu/drm/amd/include/cgs_linux.h
+++ /dev/null
@@ -1,119 +0,0 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#ifndef _CGS_LINUX_H
25#define _CGS_LINUX_H
26
27#include "cgs_common.h"
28
29/**
30 * cgs_irq_source_set_func() - Callback for enabling/disabling interrupt sources
31 * @private_data: private data provided to cgs_add_irq_source
32 * @src_id: interrupt source ID
33 * @type: interrupt type
34 * @enabled: 0 = disable source, non-0 = enable source
35 *
36 * Return: 0 on success, -errno otherwise
37 */
38typedef int (*cgs_irq_source_set_func_t)(void *private_data,
39 unsigned src_id, unsigned type,
40 int enabled);
41
42/**
43 * cgs_irq_handler_func() - Interrupt handler callback
44 * @private_data: private data provided to cgs_add_irq_source
45 * @src_id: interrupt source ID
46 * @iv_entry: pointer to raw ih ring entry
47 *
48 * This callback runs in interrupt context.
49 *
50 * Return: 0 on success, -errno otherwise
51 */
52typedef int (*cgs_irq_handler_func_t)(void *private_data,
53 unsigned src_id, const uint32_t *iv_entry);
54
55/**
56 * cgs_add_irq_source() - Add an IRQ source
57 * @cgs_device: opaque device handle
58 * @src_id: interrupt source ID
59 * @num_types: number of interrupt types that can be independently enabled
60 * @set: callback function to enable/disable an interrupt type
61 * @handler: interrupt handler callback
62 * @private_data: private data to pass to callback functions
63 *
64 * The same IRQ source can be added only once. Adding an IRQ source
65 * indicates ownership of that IRQ source and all its IRQ types.
66 *
67 * Return: 0 on success, -errno otherwise
68 */
69typedef int (*cgs_add_irq_source_t)(void *cgs_device, unsigned client_id,
70 unsigned src_id,
71 unsigned num_types,
72 cgs_irq_source_set_func_t set,
73 cgs_irq_handler_func_t handler,
74 void *private_data);
75
76/**
77 * cgs_irq_get() - Request enabling an IRQ source and type
78 * @cgs_device: opaque device handle
79 * @src_id: interrupt source ID
80 * @type: interrupt type
81 *
82 * cgs_irq_get and cgs_irq_put calls must be balanced. They count
83 * "references" to IRQ sources.
84 *
85 * Return: 0 on success, -errno otherwise
86 */
87typedef int (*cgs_irq_get_t)(void *cgs_device, unsigned client_id, unsigned src_id, unsigned type);
88
89/**
90 * cgs_irq_put() - Indicate IRQ source is no longer needed
91 * @cgs_device: opaque device handle
92 * @src_id: interrupt source ID
93 * @type: interrupt type
94 *
95 * cgs_irq_get and cgs_irq_put calls must be balanced. They count
96 * "references" to IRQ sources. Even after cgs_irq_put is called, the
97 * IRQ handler may still be called if there are more refecences to
98 * the IRQ source.
99 *
100 * Return: 0 on success, -errno otherwise
101 */
102typedef int (*cgs_irq_put_t)(void *cgs_device, unsigned client_id, unsigned src_id, unsigned type);
103
104struct cgs_os_ops {
105 /* IRQ handling */
106 cgs_add_irq_source_t add_irq_source;
107 cgs_irq_get_t irq_get;
108 cgs_irq_put_t irq_put;
109};
110
111#define cgs_add_irq_source(dev,client_id,src_id,num_types,set,handler,private_data) \
112 CGS_OS_CALL(add_irq_source,dev,client_id,src_id,num_types,set,handler, \
113 private_data)
114#define cgs_irq_get(dev,client_id,src_id,type) \
115 CGS_OS_CALL(irq_get,dev,client_id,src_id,type)
116#define cgs_irq_put(dev,client_id,src_id,type) \
117 CGS_OS_CALL(irq_put,dev,client_id,src_id,type)
118
119#endif /* _CGS_LINUX_H */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 8f032e693842..ce581ae1103a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -58,50 +58,6 @@ static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
58static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr); 58static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
59static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr); 59static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
60 60
61static int phm_thermal_l2h_irq(void *private_data,
62 unsigned src_id, const uint32_t *iv_entry)
63{
64 struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
65 struct amdgpu_device *adev = hwmgr->adev;
66
67 pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
68 PCI_BUS_NUM(adev->pdev->devfn),
69 PCI_SLOT(adev->pdev->devfn),
70 PCI_FUNC(adev->pdev->devfn));
71 return 0;
72}
73
74static int phm_thermal_h2l_irq(void *private_data,
75 unsigned src_id, const uint32_t *iv_entry)
76{
77 struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
78 struct amdgpu_device *adev = hwmgr->adev;
79
80 pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
81 PCI_BUS_NUM(adev->pdev->devfn),
82 PCI_SLOT(adev->pdev->devfn),
83 PCI_FUNC(adev->pdev->devfn));
84 return 0;
85}
86
87static int phm_ctf_irq(void *private_data,
88 unsigned src_id, const uint32_t *iv_entry)
89{
90 struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
91 struct amdgpu_device *adev = hwmgr->adev;
92
93 pr_warn("GPU Critical Temperature Fault detected on PCIe %d:%d.%d!\n",
94 PCI_BUS_NUM(adev->pdev->devfn),
95 PCI_SLOT(adev->pdev->devfn),
96 PCI_FUNC(adev->pdev->devfn));
97 return 0;
98}
99
100static const struct cgs_irq_src_funcs thermal_irq_src[3] = {
101 { .handler = phm_thermal_l2h_irq },
102 { .handler = phm_thermal_h2l_irq },
103 { .handler = phm_ctf_irq }
104};
105 61
106static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr) 62static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
107{ 63{
@@ -250,7 +206,7 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
250 if (ret) 206 if (ret)
251 goto err2; 207 goto err2;
252 208
253 ret = phm_register_thermal_interrupt(hwmgr, &thermal_irq_src); 209 ret = phm_register_thermal_interrupt(hwmgr, NULL);
254 if (ret) 210 if (ret)
255 goto err2; 211 goto err2;
256 212
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
index e11daf5cbf80..1f6d481826ff 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
@@ -534,3 +534,78 @@ int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
534} 534}
535 535
536 536
537int phm_irq_process(struct amdgpu_device *adev,
538 struct amdgpu_irq_src *source,
539 struct amdgpu_iv_entry *entry)
540{
541 uint32_t client_id = entry->client_id;
542 uint32_t src_id = entry->src_id;
543
544 if (client_id == AMDGPU_IH_CLIENTID_LEGACY) {
545 if (src_id == 230)
546 pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
547 PCI_BUS_NUM(adev->pdev->devfn),
548 PCI_SLOT(adev->pdev->devfn),
549 PCI_FUNC(adev->pdev->devfn));
550 else if (src_id == 231)
551 pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
552 PCI_BUS_NUM(adev->pdev->devfn),
553 PCI_SLOT(adev->pdev->devfn),
554 PCI_FUNC(adev->pdev->devfn));
555 else if (src_id == 83)
556 pr_warn("GPU Critical Temperature Fault detected on PCIe %d:%d.%d!\n",
557 PCI_BUS_NUM(adev->pdev->devfn),
558 PCI_SLOT(adev->pdev->devfn),
559 PCI_FUNC(adev->pdev->devfn));
560 } else if (client_id == SOC15_IH_CLIENTID_THM) {
561 if (src_id == 0)
562 pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
563 PCI_BUS_NUM(adev->pdev->devfn),
564 PCI_SLOT(adev->pdev->devfn),
565 PCI_FUNC(adev->pdev->devfn));
566 else
567 pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
568 PCI_BUS_NUM(adev->pdev->devfn),
569 PCI_SLOT(adev->pdev->devfn),
570 PCI_FUNC(adev->pdev->devfn));
571 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO)
572 pr_warn("GPU Critical Temperature Fault detected on PCIe %d:%d.%d!\n",
573 PCI_BUS_NUM(adev->pdev->devfn),
574 PCI_SLOT(adev->pdev->devfn),
575 PCI_FUNC(adev->pdev->devfn));
576
577 return 0;
578}
579
580static const struct amdgpu_irq_src_funcs smu9_irq_funcs = {
581 .process = phm_irq_process,
582};
583
584int smu9_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
585 const void *info)
586{
587 struct amdgpu_irq_src *source =
588 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
589
590 if (!source)
591 return -ENOMEM;
592
593 source->funcs = &smu9_irq_funcs;
594
595 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
596 SOC15_IH_CLIENTID_THM,
597 0,
598 source);
599 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
600 SOC15_IH_CLIENTID_THM,
601 1,
602 source);
603
604 /* Register CTF(GPIO_19) interrupt */
605 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
606 SOC15_IH_CLIENTID_ROM_SMUIO,
607 83,
608 source);
609
610 return 0;
611}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
index a1a491300348..6a43a2ac5304 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
@@ -73,6 +73,13 @@ extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
73 uint32_t value, 73 uint32_t value,
74 uint32_t mask); 74 uint32_t mask);
75 75
76int phm_irq_process(struct amdgpu_device *adev,
77 struct amdgpu_irq_src *source,
78 struct amdgpu_iv_entry *entry);
79
80int smu9_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
81 const void *info);
82
76#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 83#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
77#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK 84#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
78 85
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 5521137cd639..bb2eb1cd05a9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -44,7 +44,6 @@
44#include "vega10_thermal.h" 44#include "vega10_thermal.h"
45#include "pp_debug.h" 45#include "pp_debug.h"
46#include "amd_pcie_helpers.h" 46#include "amd_pcie_helpers.h"
47#include "cgs_linux.h"
48#include "ppinterrupt.h" 47#include "ppinterrupt.h"
49#include "pp_overdriver.h" 48#include "pp_overdriver.h"
50#include "pp_thermal.h" 49#include "pp_thermal.h"
@@ -4816,38 +4815,6 @@ static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
4816 return 0; 4815 return 0;
4817} 4816}
4818 4817
4819static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
4820 const void *info)
4821{
4822 struct cgs_irq_src_funcs *irq_src =
4823 (struct cgs_irq_src_funcs *)info;
4824
4825 if (hwmgr->thermal_controller.ucType ==
4826 ATOM_VEGA10_PP_THERMALCONTROLLER_VEGA10 ||
4827 hwmgr->thermal_controller.ucType ==
4828 ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
4829 PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
4830 SOC15_IH_CLIENTID_THM,
4831 0, 0, irq_src[0].set, irq_src[0].handler, hwmgr),
4832 "Failed to register high thermal interrupt!",
4833 return -EINVAL);
4834 PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
4835 SOC15_IH_CLIENTID_THM,
4836 1, 0, irq_src[1].set, irq_src[1].handler, hwmgr),
4837 "Failed to register low thermal interrupt!",
4838 return -EINVAL);
4839 }
4840
4841 /* Register CTF(GPIO_19) interrupt */
4842 PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
4843 SOC15_IH_CLIENTID_ROM_SMUIO,
4844 83, 0, irq_src[2].set, irq_src[2].handler, hwmgr),
4845 "Failed to register CTF thermal interrupt!",
4846 return -EINVAL);
4847
4848 return 0;
4849}
4850
4851static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 4818static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
4852{ 4819{
4853 struct vega10_hwmgr *data = hwmgr->backend; 4820 struct vega10_hwmgr *data = hwmgr->backend;
@@ -4972,7 +4939,7 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
4972 .avfs_control = vega10_avfs_enable, 4939 .avfs_control = vega10_avfs_enable,
4973 .notify_cac_buffer_info = vega10_notify_cac_buffer_info, 4940 .notify_cac_buffer_info = vega10_notify_cac_buffer_info,
4974 .get_thermal_temperature_range = vega10_get_thermal_temperature_range, 4941 .get_thermal_temperature_range = vega10_get_thermal_temperature_range,
4975 .register_internal_thermal_interrupt = vega10_register_thermal_interrupt, 4942 .register_internal_thermal_interrupt = smu9_register_thermal_interrupt,
4976 .start_thermal_controller = vega10_start_thermal_controller, 4943 .start_thermal_controller = vega10_start_thermal_controller,
4977 .get_power_profile_mode = vega10_get_power_profile_mode, 4944 .get_power_profile_mode = vega10_get_power_profile_mode,
4978 .set_power_profile_mode = vega10_set_power_profile_mode, 4945 .set_power_profile_mode = vega10_set_power_profile_mode,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index f0bcac4be104..b9f8ec5df8a7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -44,7 +44,6 @@
44#include "vega12_ppsmc.h" 44#include "vega12_ppsmc.h"
45#include "pp_debug.h" 45#include "pp_debug.h"
46#include "amd_pcie_helpers.h" 46#include "amd_pcie_helpers.h"
47#include "cgs_linux.h"
48#include "ppinterrupt.h" 47#include "ppinterrupt.h"
49#include "pp_overdriver.h" 48#include "pp_overdriver.h"
50#include "pp_thermal.h" 49#include "pp_thermal.h"
@@ -2509,51 +2508,6 @@ static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
2509 return 0; 2508 return 0;
2510} 2509}
2511 2510
2512static int vega12_is_hardware_ctf_enabled(struct pp_hwmgr *hwmgr)
2513{
2514 uint32_t reg;
2515
2516 reg = soc15_get_register_offset(THM_HWID, 0,
2517 mmTHM_TCON_THERM_TRIP_BASE_IDX,
2518 mmTHM_TCON_THERM_TRIP);
2519
2520 return (((cgs_read_register(hwmgr->device, reg) &
2521 THM_TCON_THERM_TRIP__THERM_TP_EN_MASK) >>
2522 THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT) == 1);
2523}
2524
2525static int vega12_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
2526 const void *info)
2527{
2528 struct cgs_irq_src_funcs *irq_src =
2529 (struct cgs_irq_src_funcs *)info;
2530
2531 if (hwmgr->thermal_controller.ucType ==
2532 ATOM_VEGA12_PP_THERMALCONTROLLER_VEGA12) {
2533 PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
2534 0xf, /* AMDGPU_IH_CLIENTID_THM */
2535 0, 0, irq_src[0].set, irq_src[0].handler, hwmgr),
2536 "Failed to register high thermal interrupt!",
2537 return -EINVAL);
2538 PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
2539 0xf, /* AMDGPU_IH_CLIENTID_THM */
2540 1, 0, irq_src[1].set, irq_src[1].handler, hwmgr),
2541 "Failed to register low thermal interrupt!",
2542 return -EINVAL);
2543 }
2544
2545 if (vega12_is_hardware_ctf_enabled(hwmgr))
2546 /* Register CTF(GPIO_19) interrupt */
2547 PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
2548 0x16, /* AMDGPU_IH_CLIENTID_ROM_SMUIO, */
2549 83, 0, irq_src[2].set, irq_src[2].handler, hwmgr),
2550 "Failed to register CTF thermal interrupt!",
2551 return -EINVAL);
2552
2553 return 0;
2554}
2555
2556
2557static const struct pp_hwmgr_func vega12_hwmgr_funcs = { 2511static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
2558 .backend_init = vega12_hwmgr_backend_init, 2512 .backend_init = vega12_hwmgr_backend_init,
2559 .backend_fini = vega12_hwmgr_backend_fini, 2513 .backend_fini = vega12_hwmgr_backend_fini,
@@ -2603,7 +2557,7 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
2603#endif 2557#endif
2604 .notify_cac_buffer_info = vega12_notify_cac_buffer_info, 2558 .notify_cac_buffer_info = vega12_notify_cac_buffer_info,
2605 .get_thermal_temperature_range = vega12_get_thermal_temperature_range, 2559 .get_thermal_temperature_range = vega12_get_thermal_temperature_range,
2606 .register_internal_thermal_interrupt = vega12_register_thermal_interrupt, 2560 .register_internal_thermal_interrupt = smu9_register_thermal_interrupt,
2607 .start_thermal_controller = vega12_start_thermal_controller, 2561 .start_thermal_controller = vega12_start_thermal_controller,
2608}; 2562};
2609 2563
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 4b3b05747a3f..985fe8d5bf7d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -785,11 +785,6 @@ struct pp_hwmgr {
785 uint32_t workload_setting[Workload_Policy_Max]; 785 uint32_t workload_setting[Workload_Policy_Max];
786}; 786};
787 787
788struct cgs_irq_src_funcs {
789 cgs_irq_source_set_func_t set;
790 cgs_irq_handler_func_t handler;
791};
792
793extern int hwmgr_early_init(struct pp_hwmgr *hwmgr); 788extern int hwmgr_early_init(struct pp_hwmgr *hwmgr);
794extern int hwmgr_hw_init(struct pp_hwmgr *hwmgr); 789extern int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
795extern int hwmgr_hw_fini(struct pp_hwmgr *hwmgr); 790extern int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-28 11:39:00 -0400