aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/include
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/amd/include')
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h8
-rw-r--r--drivers/gpu/drm/amd/include/atomfirmware.h12
2 files changed, 9 insertions, 11 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h
index 88f7c69df6b9..06fac509e987 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h
@@ -36,13 +36,13 @@
36/* DF_CS_AON0_DramBaseAddress0 */ 36/* DF_CS_AON0_DramBaseAddress0 */
37#define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 37#define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
38#define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 38#define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
39#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4 39#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x2
40#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8 40#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x9
41#define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc 41#define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
42#define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L 42#define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
43#define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L 43#define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
44#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L 44#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x0000003CL
45#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L 45#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000E00L
46#define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L 46#define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
47 47
48#endif 48#endif
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index c6c1666ac120..092d800b703a 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -2026,17 +2026,15 @@ enum atom_smu11_syspll_id {
2026 SMU11_SYSPLL3_1_ID = 6, 2026 SMU11_SYSPLL3_1_ID = 6,
2027}; 2027};
2028 2028
2029
2030enum atom_smu11_syspll0_clock_id { 2029enum atom_smu11_syspll0_clock_id {
2031 SMU11_SYSPLL0_SOCCLK_ID = 0, // SOCCLK 2030 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK
2032 SMU11_SYSPLL0_MP0CLK_ID = 1, // MP0CLK 2031 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK
2033 SMU11_SYSPLL0_DCLK_ID = 2, // DCLK 2032 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
2034 SMU11_SYSPLL0_VCLK_ID = 3, // VCLK 2033 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK
2035 SMU11_SYSPLL0_ECLK_ID = 4, // ECLK 2034 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK
2036 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK 2035 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
2037}; 2036};
2038 2037
2039
2040enum atom_smu11_syspll1_0_clock_id { 2038enum atom_smu11_syspll1_0_clock_id {
2041 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a 2039 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
2042}; 2040};