15 files changed, 161 insertions, 70 deletions

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1ce10bc2d37b..d7d1245c1050 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -46,6 +46,7 @@
 #include <linux/moduleparam.h>
 #include <linux/version.h>
 #include <linux/types.h>
+#include <linux/pm_runtime.h>
 
 #include <drm/drmP.h>
 #include <drm/drm_atomic.h>
@@ -2095,12 +2096,6 @@ convert_color_depth_from_display_info(const struct drm_connector *connector)
 {
         uint32_t bpc = connector->display_info.bpc;
 
-        /* Limited color depth to 8bit
-         * TODO: Still need to handle deep color
-         */
-        if (bpc > 8)
-                bpc = 8;
-
         switch (bpc) {
         case 0:
                 /* Temporary Work around, DRM don't parse color depth for
@@ -2316,27 +2311,22 @@ decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
         }
 }
 
-static int create_fake_sink(struct amdgpu_dm_connector *aconnector)
+static struct dc_sink *
+create_fake_sink(struct amdgpu_dm_connector *aconnector)
 {
-        struct dc_sink *sink = NULL;
         struct dc_sink_init_data sink_init_data = { 0 };
-
+        struct dc_sink *sink = NULL;
         sink_init_data.link = aconnector->dc_link;
         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
 
         sink = dc_sink_create(&sink_init_data);
         if (!sink) {
                 DRM_ERROR("Failed to create sink!\n");
-                return -ENOMEM;
+                return NULL;
         }
-
         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
-        aconnector->fake_enable = true;
-
-        aconnector->dc_sink = sink;
-        aconnector->dc_link->local_sink = sink;
 
-        return 0;
+        return sink;
 }
 
 static void set_multisync_trigger_params(
@@ -2399,7 +2389,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
         struct dc_stream_state *stream = NULL;
         struct drm_display_mode mode = *drm_mode;
         bool native_mode_found = false;
-
+        struct dc_sink *sink = NULL;
         if (aconnector == NULL) {
                 DRM_ERROR("aconnector is NULL!\n");
                 return stream;
@@ -2417,15 +2407,18 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
                         return stream;
                 }
 
-                if (create_fake_sink(aconnector))
+                sink = create_fake_sink(aconnector);
+                if (!sink)
                         return stream;
+        } else {
+                sink = aconnector->dc_sink;
         }
 
-        stream = dc_create_stream_for_sink(aconnector->dc_sink);
+        stream = dc_create_stream_for_sink(sink);
 
         if (stream == NULL) {
                 DRM_ERROR("Failed to create stream for sink!\n");
-                return stream;
+                goto finish;
         }
 
         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
@@ -2464,12 +2457,15 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
         fill_audio_info(
                 &stream->audio_info,
                 drm_connector,
-                aconnector->dc_sink);
+                sink);
 
         update_stream_signal(stream);
 
         if (dm_state && dm_state->freesync_capable)
                 stream->ignore_msa_timing_param = true;
+finish:
+        if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL)
+                dc_sink_release(sink);
 
         return stream;
 }
@@ -2714,6 +2710,9 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
         struct dm_connector_state *state =
                 to_dm_connector_state(connector->state);
 
+        if (connector->state)
+                __drm_atomic_helper_connector_destroy_state(connector->state);
+
         kfree(state);
 
         state = kzalloc(sizeof(*state), GFP_KERNEL);
@@ -2724,8 +2723,7 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
                 state->underscan_hborder = 0;
                 state->underscan_vborder = 0;
 
-                connector->state = &state->base;
-                connector->state->connector = connector;
+                __drm_atomic_helper_connector_reset(connector, &state->base);
         }
 }
 
@@ -3083,17 +3081,6 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
                 }
         }
 
-        /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
-         * prepare and cleanup in drm_atomic_helper_prepare_planes
-         * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
-         * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
-         * code touching fram buffers should be avoided for DC.
-         */
-        if (plane->type == DRM_PLANE_TYPE_CURSOR) {
-                struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
-
-                acrtc->cursor_bo = obj;
-        }
         return 0;
 }
 
@@ -4281,6 +4268,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
                         if (dm_old_crtc_state->stream)
                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
 
+                        pm_runtime_get_noresume(dev->dev);
+
                         acrtc->enabled = true;
                         acrtc->hw_mode = new_crtc_state->mode;
                         crtc->hwmode = new_crtc_state->mode;
@@ -4469,6 +4458,16 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
                 drm_atomic_helper_wait_for_flip_done(dev, state);
 
         drm_atomic_helper_cleanup_planes(dev, state);
+
+        /* Finally, drop a runtime PM reference for each newly disabled CRTC,
+         * so we can put the GPU into runtime suspend if we're not driving any
+         * displays anymore
+         */
+        pm_runtime_mark_last_busy(dev->dev);
+        for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+                if (old_crtc_state->active && !new_crtc_state->active)
+                        pm_runtime_put_autosuspend(dev->dev);
+        }
 }
 
 
@@ -4768,15 +4767,16 @@ next_crtc:
                  * We want to do dc stream updates that do not require a
                  * full modeset below.
                  */
-                if (!enable || !aconnector || modereset_required(new_crtc_state))
+                if (!(enable && aconnector && new_crtc_state->enable &&
+                      new_crtc_state->active))
                         continue;
                 /*
                  * Given above conditions, the dc state cannot be NULL because:
-                 * 1. We're attempting to enable a CRTC. Which has a...
-                 * 2. Valid connector attached, and
-                 * 3. User does not want to reset it (disable or mark inactive,
-                 *    which can happen on a CRTC that's already disabled).
-                 * => It currently exists.
+                 * 1. We're in the process of enabling CRTCs (just been added
+                 *    to the dc context, or already is on the context)
+                 * 2. Has a valid connector attached, and
+                 * 3. Is currently active and enabled.
+                 * => The dc stream state currently exists.
                  */
                 BUG_ON(dm_new_crtc_state->stream == NULL);
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 4be21bf54749..a910f01838ab 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -555,6 +555,9 @@ static inline int dm_irq_state(struct amdgpu_device *adev,
                 return 0;
         }
 
+        if (acrtc->otg_inst == -1)
+                return 0;
+
         irq_source = dal_irq_type + acrtc->otg_inst;
 
         st = (state == AMDGPU_IRQ_STATE_ENABLE);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 0229c7edb8ad..5a3346124a01 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -234,6 +234,33 @@ static void pp_to_dc_clock_levels(
         }
 }
 
+static void pp_to_dc_clock_levels_with_latency(
+                const struct pp_clock_levels_with_latency *pp_clks,
+                struct dm_pp_clock_levels_with_latency *clk_level_info,
+                enum dm_pp_clock_type dc_clk_type)
+{
+        uint32_t i;
+
+        if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
+                DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
+                                DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
+                                pp_clks->num_levels,
+                                DM_PP_MAX_CLOCK_LEVELS);
+
+                clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
+        } else
+                clk_level_info->num_levels = pp_clks->num_levels;
+
+        DRM_DEBUG("DM_PPLIB: values for %s clock\n",
+                        DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
+
+        for (i = 0; i < clk_level_info->num_levels; i++) {
+                DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
+                clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
+                clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
+        }
+}
+
 bool dm_pp_get_clock_levels_by_type(
                 const struct dc_context *ctx,
                 enum dm_pp_clock_type clk_type,
@@ -311,8 +338,22 @@ bool dm_pp_get_clock_levels_by_type_with_latency(
         enum dm_pp_clock_type clk_type,
         struct dm_pp_clock_levels_with_latency *clk_level_info)
 {
-        /* TODO: to be implemented */
-        return false;
+        struct amdgpu_device *adev = ctx->driver_context;
+        void *pp_handle = adev->powerplay.pp_handle;
+        struct pp_clock_levels_with_latency pp_clks = { 0 };
+        const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+
+        if (!pp_funcs || !pp_funcs->get_clock_by_type_with_latency)
+                return false;
+
+        if (pp_funcs->get_clock_by_type_with_latency(pp_handle,
+                                                     dc_to_pp_clock_type(clk_type),
+                                                     &pp_clks))
+                return false;
+
+        pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);
+
+        return true;
 }
 
 bool dm_pp_get_clock_levels_by_type_with_voltage(
diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
index e61dd97d0928..f28989860fd8 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
@@ -449,6 +449,11 @@ static inline unsigned int clamp_ux_dy(
                 return min_clamp;
 }
 
+unsigned int dc_fixpt_u3d19(struct fixed31_32 arg)
+{
+        return ux_dy(arg.value, 3, 19);
+}
+
 unsigned int dc_fixpt_u2d19(struct fixed31_32 arg)
 {
         return ux_dy(arg.value, 2, 19);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 7d609c71394b..7857cb42b3e6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1630,17 +1630,42 @@ static enum dc_status read_hpd_rx_irq_data(
         struct dc_link *link,
         union hpd_irq_data *irq_data)
 {
+        static enum dc_status retval;
+
         /* The HW reads 16 bytes from 200h on HPD,
          * but if we get an AUX_DEFER, the HW cannot retry
          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
          * fail, so we now explicitly read 6 bytes which is
          * the req from the above mentioned test cases.
+         *
+         * For DP 1.4 we need to read those from 2002h range.
          */
-        return core_link_read_dpcd(
-        link,
-        DP_SINK_COUNT,
-        irq_data->raw,
-        sizeof(union hpd_irq_data));
+        if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
+                retval = core_link_read_dpcd(
+                        link,
+                        DP_SINK_COUNT,
+                        irq_data->raw,
+                        sizeof(union hpd_irq_data));
+        else {
+                /* Read 2 bytes at this location,... */
+                retval = core_link_read_dpcd(
+                        link,
+                        DP_SINK_COUNT_ESI,
+                        irq_data->raw,
+                        2);
+
+                if (retval != DC_OK)
+                        return retval;
+
+                /* ... then read remaining 4 at the other location */
+                retval = core_link_read_dpcd(
+                        link,
+                        DP_LANE0_1_STATUS_ESI,
+                        &irq_data->raw[2],
+                        4);
+        }
+
+        return retval;
 }
 
 static bool allow_hpd_rx_irq(const struct dc_link *link)
@@ -2278,7 +2303,7 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
 
 static bool retrieve_link_cap(struct dc_link *link)
 {
-        uint8_t dpcd_data[DP_TRAINING_AUX_RD_INTERVAL - DP_DPCD_REV + 1];
+        uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
 
         union down_stream_port_count down_strm_port_count;
         union edp_configuration_cap edp_config_cap;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index 0a6d483dc046..c0e813c7ddd4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -72,7 +72,8 @@ static void dce110_update_generic_info_packet(
         uint32_t max_retries = 50;
 
         /*we need turn on clock before programming AFMT block*/
-        REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
+        if (REG(AFMT_CNTL))
+                REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
 
         if (REG(AFMT_VBI_PACKET_CONTROL1)) {
                 if (packet_index >= 8)
@@ -719,7 +720,8 @@ static void dce110_stream_encoder_update_hdmi_info_packets(
                         const uint32_t *content =
                                 (const uint32_t *) &info_frame->avi.sb[0];
                         /*we need turn on clock before programming AFMT block*/
-                        REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
+                        if (REG(AFMT_CNTL))
+                                REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
 
                         REG_WRITE(AFMT_AVI_INFO0, content[0]);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
index 9150d2694450..e2994d337044 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -121,10 +121,10 @@ static void reset_lb_on_vblank(struct dc_context *ctx)
                 frame_count = dm_read_reg(ctx, mmCRTC_STATUS_FRAME_COUNT);
 
 
-                for (retry = 100; retry > 0; retry--) {
+                for (retry = 10000; retry > 0; retry--) {
                         if (frame_count != dm_read_reg(ctx, mmCRTC_STATUS_FRAME_COUNT))
                                 break;
-                        msleep(1);
+                        udelay(10);
                 }
                 if (!retry)
                         dm_error("Frame count did not increase for 100ms.\n");
@@ -147,14 +147,14 @@ static void wait_for_fbc_state_changed(
         uint32_t addr = mmFBC_STATUS;
         uint32_t value;
 
-        while (counter < 10) {
+        while (counter < 1000) {
                 value = dm_read_reg(cp110->base.ctx, addr);
                 if (get_reg_field_value(
                         value,
                         FBC_STATUS,
                         FBC_ENABLE_STATUS) == enabled)
                         break;
-                msleep(10);
+                udelay(100);
                 counter++;
         }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index a92fb0aa2ff3..c29052b6da5a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1004,9 +1004,9 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
                 /*don't free audio if it is from retrain or internal disable stream*/
                 if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
                         /*we have to dynamic arbitrate the audio endpoints*/
-                        pipe_ctx->stream_res.audio = NULL;
                         /*we free the resource, need reset is_audio_acquired*/
                         update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
+                        pipe_ctx->stream_res.audio = NULL;
                 }
 
                 /* TODO: notify audio driver for if audio modes list changed
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 46a35c7f01df..c69fa4bfab0a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -132,8 +132,7 @@ void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
 
 #define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19))
 
-
-bool dpp_get_optimal_number_of_taps(
+static bool dpp_get_optimal_number_of_taps(
                 struct dpp *dpp,
                 struct scaler_data *scl_data,
                 const struct scaling_taps *in_taps)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 5944a3ba0409..e862cafa6501 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -1424,12 +1424,8 @@ void dpp1_set_degamma(
                 enum ipp_degamma_mode mode);
 
 void dpp1_set_degamma_pwl(struct dpp *dpp_base,
-                                                                 const struct pwl_params *params);
+                const struct pwl_params *params);
 
-bool dpp_get_optimal_number_of_taps(
-                struct dpp *dpp,
-                struct scaler_data *scl_data,
-                const struct scaling_taps *in_taps);
 
 void dpp_read_state(struct dpp *dpp_base,
                 struct dcn_dpp_state *s);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
index 4ddd6273d5a5..f862fd148cca 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
@@ -565,16 +565,16 @@ static void dpp1_dscl_set_manual_ratio_init(
         uint32_t init_int = 0;
 
         REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
-                        SCL_H_SCALE_RATIO, dc_fixpt_u2d19(data->ratios.horz) << 5);
+                        SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) << 5);
 
         REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
-                        SCL_V_SCALE_RATIO, dc_fixpt_u2d19(data->ratios.vert) << 5);
+                        SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) << 5);
 
         REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,
-                        SCL_H_SCALE_RATIO_C, dc_fixpt_u2d19(data->ratios.horz_c) << 5);
+                        SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.horz_c) << 5);
 
         REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,
-                        SCL_V_SCALE_RATIO_C, dc_fixpt_u2d19(data->ratios.vert_c) << 5);
+                        SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.vert_c) << 5);
 
         /*
          * 0.24 format for fraction, first five bits zeroed
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index d2ab78b35a7a..c28085be39ff 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -396,11 +396,15 @@ bool hubp1_program_surface_flip_and_addr(
                 if (address->grph_stereo.right_addr.quad_part == 0)
                         break;
 
-                REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
+                REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
                                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
                                 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
                                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
-                                PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
+                                PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
+                                SECONDARY_SURFACE_TMZ, address->tmz_surface,
+                                SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
+                                SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
+                                SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
 
                 if (address->grph_stereo.right_meta_addr.quad_part != 0) {
 
@@ -459,9 +463,11 @@ void hubp1_dcc_control(struct hubp *hubp, bool enable,
         uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 
-        REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
+        REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
                         PRIMARY_SURFACE_DCC_EN, dcc_en,
-                        PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
+                        PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
+                        SECONDARY_SURFACE_DCC_EN, dcc_en,
+                        SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
 }
 
 void hubp1_program_surface_config(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index af384034398f..d901d5092969 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -312,6 +312,12 @@
         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\
         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
+        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\
+        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\
+        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\
+        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\
+        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\
+        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
         HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
         HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
         HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
@@ -489,6 +495,8 @@
         type SECONDARY_META_SURFACE_TMZ_C;\
         type PRIMARY_SURFACE_DCC_EN;\
         type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
+        type SECONDARY_SURFACE_DCC_EN;\
+        type SECONDARY_SURFACE_DCC_IND_64B_BLK;\
         type DET_BUF_PLANE1_BASE_ADDRESS;\
         type CROSSBAR_SRC_CB_B;\
         type CROSSBAR_SRC_CR_R;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index 653b7b2efe2e..c928ee4cd382 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -319,6 +319,10 @@ void enc1_stream_encoder_dp_set_stream_attribute(
                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
                                 DP_COMPONENT_PIXEL_DEPTH_12BPC);
                 break;
+        case COLOR_DEPTH_161616:
+                REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
+                                DP_COMPONENT_PIXEL_DEPTH_16BPC);
+                break;
         default:
                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
                                 DP_COMPONENT_PIXEL_DEPTH_6BPC);
diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index bb0d4ebba9f0..a981b3e99ab3 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -496,6 +496,8 @@ static inline int dc_fixpt_ceil(struct fixed31_32 arg)
  * fractional
  */
 
+unsigned int dc_fixpt_u3d19(struct fixed31_32 arg);
+
 unsigned int dc_fixpt_u2d19(struct fixed31_32 arg);
 
 unsigned int dc_fixpt_u0d19(struct fixed31_32 arg);