21 files changed, 228 insertions, 126 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 35e84ed031de..12868c769606 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1358,13 +1358,13 @@ enum dc_irq_source dc_interrupt_to_irq_source(
         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
 }
 
-void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
+bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
 {
 
         if (dc == NULL)
-                return;
+                return false;
 
-        dal_irq_service_set(dc->res_pool->irqs, src, enable);
+        return dal_irq_service_set(dc->res_pool->irqs, src, enable);
 }
 
 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index a37428271573..be5546181fa8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1749,8 +1749,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
                         link->link_enc,
                         pipe_ctx->clock_source->id,
                         display_color_depth,
-                        pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A,
-                        pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK,
+                        pipe_ctx->stream->signal,
                         stream->phy_pix_clk);
 
         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 95b8dd0e53c6..4d07ffebfd31 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1360,9 +1360,6 @@ bool dc_is_stream_scaling_unchanged(
         return true;
 }
 
-/* Maximum TMDS single link pixel clock 165MHz */
-#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
-
 static void update_stream_engine_usage(
                 struct resource_context *res_ctx,
                 const struct resource_pool *pool,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 539c3e0a6292..cd5819789d76 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -33,8 +33,7 @@
 /*******************************************************************************
  * Private functions
  ******************************************************************************/
-#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000
-static void update_stream_signal(struct dc_stream_state *stream)
+void update_stream_signal(struct dc_stream_state *stream)
 {
 
         struct dc_sink *dc_sink = stream->sink;
@@ -45,8 +44,9 @@ static void update_stream_signal(struct dc_stream_state *stream)
                 stream->signal = dc_sink->sink_signal;
 
         if (dc_is_dvi_signal(stream->signal)) {
-                if (stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST &&
-                        stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
+                if (stream->ctx->dc->caps.dual_link_dvi &&
+                    stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK &&
+                    stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
                         stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
                 else
                         stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
@@ -193,6 +193,7 @@ bool dc_stream_set_cursor_attributes(
 
         core_dc = stream->ctx->dc;
         res_ctx = &core_dc->current_state->res_ctx;
+        stream->cursor_attributes = *attributes;
 
         for (i = 0; i < MAX_PIPES; i++) {
                 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
@@ -204,34 +205,8 @@ bool dc_stream_set_cursor_attributes(
                         continue;
 
 
-                if (pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes != NULL)
-                        pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
-                                                pipe_ctx->plane_res.ipp, attributes);
-
-                if (pipe_ctx->plane_res.hubp != NULL &&
-                                pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes != NULL)
-                        pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
-                                        pipe_ctx->plane_res.hubp, attributes);
-
-                if (pipe_ctx->plane_res.mi != NULL &&
-                                pipe_ctx->plane_res.mi->funcs->set_cursor_attributes != NULL)
-                        pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
-                                        pipe_ctx->plane_res.mi, attributes);
-
-
-                if (pipe_ctx->plane_res.xfm != NULL &&
-                                pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes != NULL)
-                        pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
-                                pipe_ctx->plane_res.xfm, attributes);
-
-                if (pipe_ctx->plane_res.dpp != NULL &&
-                                pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes != NULL)
-                        pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
-                                pipe_ctx->plane_res.dpp, attributes->color_format);
+                core_dc->hwss.set_cursor_attribute(pipe_ctx);
         }
-
-        stream->cursor_attributes = *attributes;
-
         return true;
 }
 
@@ -255,21 +230,10 @@ bool dc_stream_set_cursor_position(
 
         core_dc = stream->ctx->dc;
         res_ctx = &core_dc->current_state->res_ctx;
+        stream->cursor_position = *position;
 
         for (i = 0; i < MAX_PIPES; i++) {
                 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
-                struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
-                struct mem_input *mi = pipe_ctx->plane_res.mi;
-                struct hubp *hubp = pipe_ctx->plane_res.hubp;
-                struct dpp *dpp = pipe_ctx->plane_res.dpp;
-                struct dc_cursor_position pos_cpy = *position;
-                struct dc_cursor_mi_param param = {
-                        .pixel_clk_khz = stream->timing.pix_clk_khz,
-                        .ref_clk_khz = core_dc->res_pool->ref_clock_inKhz,
-                        .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
-                        .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
-                        .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
-                };
 
                 if (pipe_ctx->stream != stream ||
                                 (!pipe_ctx->plane_res.mi  && !pipe_ctx->plane_res.hubp) ||
@@ -278,33 +242,9 @@ bool dc_stream_set_cursor_position(
                                 !pipe_ctx->plane_res.ipp)
                         continue;
 
-                if (pipe_ctx->plane_state->address.type
-                                == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
-                        pos_cpy.enable = false;
-
-                if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
-                        pos_cpy.enable = false;
-
-
-                if (ipp != NULL && ipp->funcs->ipp_cursor_set_position != NULL)
-                        ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
-
-                if (mi != NULL && mi->funcs->set_cursor_position != NULL)
-                        mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
-
-                if (!hubp)
-                        continue;
-
-                if (hubp->funcs->set_cursor_position != NULL)
-                        hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
-
-                if (dpp != NULL && dpp->funcs->set_cursor_position != NULL)
-                        dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);
-
+                core_dc->hwss.set_cursor_position(pipe_ctx);
         }
 
-        stream->cursor_position = *position;
-
         return true;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e2e3c9df79ea..d6d56611604e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -62,6 +62,7 @@ struct dc_caps {
         bool dcc_const_color;
         bool dynamic_audio;
         bool is_apu;
+        bool dual_link_dvi;
 };
 
 struct dc_dcc_surface_param {
@@ -672,7 +673,7 @@ enum dc_irq_source dc_interrupt_to_irq_source(
                 struct dc *dc,
                 uint32_t src_id,
                 uint32_t ext_id);
-void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
+bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
 enum dc_irq_source dc_get_hpd_irq_source_at_index(
                 struct dc *dc, uint32_t link_index);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 01c60f11b2bd..456e4d29eadd 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -237,6 +237,8 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
  */
 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
 
+void update_stream_signal(struct dc_stream_state *stream);
+
 void dc_stream_retain(struct dc_stream_state *dc_stream);
 void dc_stream_release(struct dc_stream_state *dc_stream);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index b73db9e78437..f11f17fe08f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -236,6 +236,7 @@
         SR(D2VGA_CONTROL), \
         SR(D3VGA_CONTROL), \
         SR(D4VGA_CONTROL), \
+        SR(VGA_TEST_CONTROL), \
         SR(DC_IP_REQUEST_CNTL), \
         BL_REG_LIST()
 
@@ -337,6 +338,7 @@ struct dce_hwseq_registers {
         uint32_t D2VGA_CONTROL;
         uint32_t D3VGA_CONTROL;
         uint32_t D4VGA_CONTROL;
+        uint32_t VGA_TEST_CONTROL;
         /* MMHUB registers. read only. temporary hack */
         uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
         uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
@@ -493,6 +495,12 @@ struct dce_hwseq_registers {
         HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
         HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+        HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
+        HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\
+        HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\
+        HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
+        HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
+        HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
         HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
 
@@ -583,7 +591,13 @@ struct dce_hwseq_registers {
         type DCFCLK_GATE_DIS; \
         type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
         type DENTIST_DPPCLK_WDIVIDER; \
-        type DENTIST_DISPCLK_WDIVIDER;
+        type DENTIST_DISPCLK_WDIVIDER; \
+        type VGA_TEST_ENABLE; \
+        type VGA_TEST_RENDER_START; \
+        type D1VGA_MODE_ENABLE; \
+        type D2VGA_MODE_ENABLE; \
+        type D3VGA_MODE_ENABLE; \
+        type D4VGA_MODE_ENABLE;
 
 struct dce_hwseq_shift {
         HWSEQ_REG_FIELD_LIST(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index a266e3f5e75f..e4741f1a2b01 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -82,13 +82,6 @@
 #define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
 #define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40
 
-/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
-#define TMDS_MIN_PIXEL_CLOCK 25000
-/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
-#define TMDS_MAX_PIXEL_CLOCK 165000
-/* For current ASICs pixel clock - 600MHz */
-#define MAX_ENCODER_CLOCK 600000
-
 enum {
         DP_MST_UPDATE_MAX_RETRY = 50
 };
@@ -683,6 +676,7 @@ void dce110_link_encoder_construct(
 {
         struct bp_encoder_cap_info bp_cap_info = {0};
         const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
+        enum bp_result result = BP_RESULT_OK;
 
         enc110->base.funcs = &dce110_lnk_enc_funcs;
         enc110->base.ctx = init_data->ctx;
@@ -757,15 +751,24 @@ void dce110_link_encoder_construct(
                 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
         }
 
+        /* default to one to mirror Windows behavior */
+        enc110->base.features.flags.bits.HDMI_6GB_EN = 1;
+
+        result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios,
+                                                enc110->base.id, &bp_cap_info);
+
         /* Override features with DCE-specific values */
-        if (BP_RESULT_OK == bp_funcs->get_encoder_cap_info(
-                        enc110->base.ctx->dc_bios, enc110->base.id,
-                        &bp_cap_info)) {
+        if (BP_RESULT_OK == result) {
                 enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
                                 bp_cap_info.DP_HBR2_EN;
                 enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
                                 bp_cap_info.DP_HBR3_EN;
                 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
+        } else {
+                dm_logger_write(enc110->base.ctx->logger, LOG_WARNING,
+                                "%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
+                                __func__,
+                                result);
         }
 }
 
@@ -904,8 +907,7 @@ void dce110_link_encoder_enable_tmds_output(
         struct link_encoder *enc,
         enum clock_source_id clock_source,
         enum dc_color_depth color_depth,
-        bool hdmi,
-        bool dual_link,
+        enum signal_type signal,
         uint32_t pixel_clock)
 {
         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
@@ -919,16 +921,12 @@ void dce110_link_encoder_enable_tmds_output(
         cntl.engine_id = enc->preferred_engine;
         cntl.transmitter = enc110->base.transmitter;
         cntl.pll_id = clock_source;
-        if (hdmi) {
-                cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
-                cntl.lanes_number = 4;
-        } else if (dual_link) {
-                cntl.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
+        cntl.signal = signal;
+        if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
                 cntl.lanes_number = 8;
-        } else {
-                cntl.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
+        else
                 cntl.lanes_number = 4;
-        }
+
         cntl.hpd_sel = enc110->base.hpd_source;
 
         cntl.pixel_clock = pixel_clock;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index 8ca9afe47a2b..0ec3433d34b6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -210,8 +210,7 @@ void dce110_link_encoder_enable_tmds_output(
         struct link_encoder *enc,
         enum clock_source_id clock_source,
         enum dc_color_depth color_depth,
-        bool hdmi,
-        bool dual_link,
+        enum signal_type signal,
         uint32_t pixel_clock);
 
 /* enables DP PHY output */
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
index 3931412ab6d3..87093894ea9e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
@@ -128,23 +128,22 @@ static void set_truncation(
                 return;
         }
         /* on other format-to do */
-        if (params->flags.TRUNCATE_ENABLED == 0 ||
-                        params->flags.TRUNCATE_DEPTH == 2)
+        if (params->flags.TRUNCATE_ENABLED == 0)
                 return;
         /*Set truncation depth and Enable truncation*/
         REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
                                 FMT_TRUNCATE_EN, 1,
                                 FMT_TRUNCATE_DEPTH,
-                                params->flags.TRUNCATE_MODE,
+                                params->flags.TRUNCATE_DEPTH,
                                 FMT_TRUNCATE_MODE,
-                                params->flags.TRUNCATE_DEPTH);
+                                params->flags.TRUNCATE_MODE);
 }
 
 
 /**
  *      set_spatial_dither
  *      1) set spatial dithering mode: pattern of seed
- *      2) set spatical dithering depth: 0 for 18bpp or 1 for 24bpp
+ *      2) set spatial dithering depth: 0 for 18bpp or 1 for 24bpp
  *      3) set random seed
  *      4) set random mode
  *              lfsr is reset every frame or not reset
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 3ea43e2a9450..442dd2d93618 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -852,6 +852,7 @@ static bool construct(
         dc->caps.max_downscale_ratio = 200;
         dc->caps.i2c_speed_in_khz = 40;
         dc->caps.max_cursor_size = 128;
+        dc->caps.dual_link_dvi = true;
 
         for (i = 0; i < pool->base.pipe_count; i++) {
                 pool->base.timing_generators[i] =
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 86cdd7b4811f..6f382a3ac90f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -688,15 +688,22 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
         struct dc_link *link = pipe_ctx->stream->sink->link;
 
-        /* 1. update AVI info frame (HDMI, DP)
-         * we always need to update info frame
-        */
+
         uint32_t active_total_with_borders;
         uint32_t early_control = 0;
         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 
-        /* TODOFPGA may change to hwss.update_info_frame */
+        /* For MST, there are multiply stream go to only one link.
+         * connect DIG back_end to front_end while enable_stream and
+         * disconnect them during disable_stream
+         * BY this, it is logic clean to separate stream and link */
+        link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
+                                                    pipe_ctx->stream_res.stream_enc->id, true);
+
+        /* update AVI info frame (HDMI, DP)*/
+        /* TODO: FPGA may change to hwss.update_info_frame */
         dce110_update_info_frame(pipe_ctx);
+
         /* enable early control to avoid corruption on DP monitor*/
         active_total_with_borders =
                         timing->h_addressable
@@ -717,12 +724,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
         }
 
-        /* For MST, there are multiply stream go to only one link.
-         * connect DIG back_end to front_end while enable_stream and
-         * disconnect them during disable_stream
-         * BY this, it is logic clean to separate stream and link */
-        link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
-                                                    pipe_ctx->stream_res.stream_enc->id, true);
+
+
 
 }
 
@@ -1690,9 +1693,13 @@ static void apply_min_clocks(
  *  Check if FBC can be enabled
  */
 static bool should_enable_fbc(struct dc *dc,
-                              struct dc_state *context)
+                              struct dc_state *context,
+                              uint32_t *pipe_idx)
 {
-        struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[0];
+        uint32_t i;
+        struct pipe_ctx *pipe_ctx = NULL;
+        struct resource_context *res_ctx = &context->res_ctx;
+
 
         ASSERT(dc->fbc_compressor);
 
@@ -1704,6 +1711,14 @@ static bool should_enable_fbc(struct dc *dc,
         if (context->stream_count != 1)
                 return false;
 
+        for (i = 0; i < dc->res_pool->pipe_count; i++) {
+                if (res_ctx->pipe_ctx[i].stream) {
+                        pipe_ctx = &res_ctx->pipe_ctx[i];
+                        *pipe_idx = i;
+                        break;
+                }
+        }
+
         /* Only supports eDP */
         if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
                 return false;
@@ -1729,11 +1744,14 @@ static bool should_enable_fbc(struct dc *dc,
 static void enable_fbc(struct dc *dc,
                        struct dc_state *context)
 {
-        if (should_enable_fbc(dc, context)) {
+        uint32_t pipe_idx = 0;
+
+        if (should_enable_fbc(dc, context, &pipe_idx)) {
                 /* Program GRPH COMPRESSED ADDRESS and PITCH */
                 struct compr_addr_and_pitch_params params = {0, 0, 0};
                 struct compressor *compr = dc->fbc_compressor;
-                struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[0];
+                struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
+
 
                 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
                 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
@@ -2915,6 +2933,49 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
         }
 }
 
+void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
+{
+        struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
+        struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
+        struct mem_input *mi = pipe_ctx->plane_res.mi;
+        struct dc_cursor_mi_param param = {
+                .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
+                .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
+                .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
+                .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
+                .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
+        };
+
+        if (pipe_ctx->plane_state->address.type
+                        == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+                pos_cpy.enable = false;
+
+        if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
+                pos_cpy.enable = false;
+
+        if (ipp->funcs->ipp_cursor_set_position)
+                ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
+        if (mi->funcs->set_cursor_position)
+                mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
+}
+
+void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
+{
+        struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
+
+        if (pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
+                pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
+                                pipe_ctx->plane_res.ipp, attributes);
+
+        if (pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
+                pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
+                                pipe_ctx->plane_res.mi, attributes);
+
+        if (pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
+                pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
+                                pipe_ctx->plane_res.xfm, attributes);
+}
+
 static void ready_shared_resources(struct dc *dc, struct dc_state *context) {}
 
 static void optimize_shared_resources(struct dc *dc) {}
@@ -2957,6 +3018,8 @@ static const struct hw_sequencer_funcs dce110_funcs = {
         .edp_backlight_control = hwss_edp_backlight_control,
         .edp_power_control = hwss_edp_power_control,
         .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
+        .set_cursor_position = dce110_set_cursor_position,
+        .set_cursor_attribute = dce110_set_cursor_attribute
 };
 
 void dce110_hw_sequencer_construct(struct dc *dc)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 7c4779578fb7..00f18c485e1e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -846,6 +846,16 @@ static bool dce110_validate_bandwidth(
         return result;
 }
 
+enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
+                                     struct dc_caps *caps)
+{
+        if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) ||
+            ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height))
+                return DC_FAIL_SURFACE_VALIDATE;
+
+        return DC_OK;
+}
+
 static bool dce110_validate_surface_sets(
                 struct dc_state *context)
 {
@@ -869,6 +879,13 @@ static bool dce110_validate_surface_sets(
                                         plane->src_rect.height > 1080))
                                         return false;
 
+                                /* we don't have the logic to support underlay
+                                 * only yet so block the use case where we get
+                                 * NV12 plane as top layer
+                                 */
+                                if (j == 0)
+                                        return false;
+
                                 /* irrespective of plane format,
                                  * stream should be RGB encoded
                                  */
@@ -1021,6 +1038,7 @@ static const struct resource_funcs dce110_res_pool_funcs = {
         .link_enc_create = dce110_link_encoder_create,
         .validate_guaranteed = dce110_validate_guaranteed,
         .validate_bandwidth = dce110_validate_bandwidth,
+        .validate_plane = dce110_validate_plane,
         .acquire_idle_pipe_for_layer = dce110_acquire_underlay,
         .add_stream_to_ctx = dce110_add_stream_to_ctx,
         .validate_global = dce110_validate_global
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 663e0a047a4b..98d9cd0109e1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1103,6 +1103,8 @@ static bool construct(
         dc->caps.max_downscale_ratio = 200;
         dc->caps.i2c_speed_in_khz = 100;
         dc->caps.max_cursor_size = 128;
+        dc->caps.dual_link_dvi = true;
+
 
         /*************************************************
          *  Create resources                             *
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 57cd67359567..5aab01db28ee 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -835,6 +835,8 @@ static bool construct(
         dc->caps.max_downscale_ratio = 200;
         dc->caps.i2c_speed_in_khz = 100;
         dc->caps.max_cursor_size = 128;
+        dc->caps.dual_link_dvi = true;
+
         dc->debug = debug_defaults;
 
         /*************************************************
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 8f2bd56f3461..25d7eb1567ae 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -793,6 +793,7 @@ static bool dce80_construct(
         dc->caps.max_downscale_ratio = 200;
         dc->caps.i2c_speed_in_khz = 40;
         dc->caps.max_cursor_size = 128;
+        dc->caps.dual_link_dvi = true;
 
         /*************************************************
          *  Create resources                             *
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 82572863acab..dc1e010725c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -238,10 +238,34 @@ static void enable_power_gating_plane(
 static void disable_vga(
         struct dce_hwseq *hws)
 {
+        unsigned int in_vga1_mode = 0;
+        unsigned int in_vga2_mode = 0;
+        unsigned int in_vga3_mode = 0;
+        unsigned int in_vga4_mode = 0;
+
+        REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
+        REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
+        REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
+        REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
+
+        if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
+                        in_vga3_mode == 0 && in_vga4_mode == 0)
+                return;
+
         REG_WRITE(D1VGA_CONTROL, 0);
         REG_WRITE(D2VGA_CONTROL, 0);
         REG_WRITE(D3VGA_CONTROL, 0);
         REG_WRITE(D4VGA_CONTROL, 0);
+
+        /* HW Engineer's Notes:
+         *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
+         *  then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
+         *
+         *  Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
+         *  VGA_TEST_ENABLE, to leave it in the same state as before.
+         */
+        REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
+        REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
 }
 
 static void dpp_pg_control(
@@ -1761,6 +1785,11 @@ static void update_dchubp_dpp(
                         &pipe_ctx->plane_res.scl_data.viewport_c);
         }
 
+        if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
+                dc->hwss.set_cursor_position(pipe_ctx);
+                dc->hwss.set_cursor_attribute(pipe_ctx);
+        }
+
         if (plane_state->update_flags.bits.full_update) {
                 /*gamut remap*/
                 program_gamut_remap(pipe_ctx);
@@ -2296,7 +2325,7 @@ static bool dcn10_dummy_display_power_gating(
         return true;
 }
 
-void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
+static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
 {
         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
         struct timing_generator *tg = pipe_ctx->stream_res.tg;
@@ -2316,12 +2345,46 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
         }
 }
 
-void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
+static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
 {
         if (hws->ctx->dc->res_pool->hubbub != NULL)
                 hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
 }
 
+static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
+{
+        struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
+        struct hubp *hubp = pipe_ctx->plane_res.hubp;
+        struct dpp *dpp = pipe_ctx->plane_res.dpp;
+        struct dc_cursor_mi_param param = {
+                .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
+                .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
+                .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
+                .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
+                .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
+        };
+
+        if (pipe_ctx->plane_state->address.type
+                        == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+                pos_cpy.enable = false;
+
+        if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
+                pos_cpy.enable = false;
+
+        hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
+        dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);
+}
+
+static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
+{
+        struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
+
+        pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
+                        pipe_ctx->plane_res.hubp, attributes);
+        pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
+                pipe_ctx->plane_res.dpp, attributes->color_format);
+}
+
 static const struct hw_sequencer_funcs dcn10_funcs = {
         .program_gamut_remap = program_gamut_remap,
         .program_csc_matrix = program_csc_matrix,
@@ -2362,6 +2425,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
         .edp_backlight_control = hwss_edp_backlight_control,
         .edp_power_control = hwss_edp_power_control,
         .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
+        .set_cursor_position = dcn10_set_cursor_position,
+        .set_cursor_attribute = dcn10_set_cursor_attribute
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 0fd329deacd8..54d8a1386142 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -123,8 +123,7 @@ struct link_encoder_funcs {
         void (*enable_tmds_output)(struct link_encoder *enc,
                 enum clock_source_id clock_source,
                 enum dc_color_depth color_depth,
-                bool hdmi,
-                bool dual_link,
+                enum signal_type signal,
                 uint32_t pixel_clock);
         void (*enable_dp_output)(struct link_encoder *enc,
                 const struct dc_link_settings *link_settings,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 4c0aa56f7bae..379c6ecd271a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -198,6 +198,9 @@ struct hw_sequencer_funcs {
                         bool enable);
         void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
 
+        void (*set_cursor_position)(struct pipe_ctx *pipe);
+        void (*set_cursor_attribute)(struct pipe_ctx *pipe);
+
 };
 
 void color_space_to_black_color(
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
index f7e40b292dfb..d3e1923b01a8 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
@@ -217,7 +217,7 @@ bool dce110_vblank_set(
                         core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
 
         if (enable) {
-                if (!tg->funcs->arm_vert_intr(tg, 2)) {
+                if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {
                         DC_ERROR("Failed to get VBLANK!\n");
                         return false;
                 }
diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
index 57a54a7b89e5..1c079ba37c30 100644
--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
@@ -42,8 +42,7 @@ static void virtual_link_encoder_enable_tmds_output(
         struct link_encoder *enc,
         enum clock_source_id clock_source,
         enum dc_color_depth color_depth,
-        bool hdmi,
-        bool dual_link,
+        enum signal_type signal,
         uint32_t pixel_clock) {}
 
 static void virtual_link_encoder_enable_dp_output(