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-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 95452c5a9df6..a15d9c0f233b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4212,6 +4212,18 @@ static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4212 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 4212 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4213} 4213}
4214 4214
4215static void gfx_v7_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
4216{
4217 struct amdgpu_device *adev = ring->adev;
4218 uint32_t value = 0;
4219
4220 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
4221 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
4222 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
4223 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
4224 WREG32(mmSQ_CMD, value);
4225}
4226
4215static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 4227static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4216{ 4228{
4217 WREG32(mmSQ_IND_INDEX, 4229 WREG32(mmSQ_IND_INDEX,
@@ -5088,6 +5100,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5088 .pad_ib = amdgpu_ring_generic_pad_ib, 5100 .pad_ib = amdgpu_ring_generic_pad_ib,
5089 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl, 5101 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
5090 .emit_wreg = gfx_v7_0_ring_emit_wreg, 5102 .emit_wreg = gfx_v7_0_ring_emit_wreg,
5103 .soft_recovery = gfx_v7_0_ring_soft_recovery,
5091}; 5104};
5092 5105
5093static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { 5106static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {