aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.h112
3 files changed, 120 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 59376fa69eba..675e12c42532 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -44,6 +44,7 @@ struct amdgpu_virt {
44 uint32_t caps; 44 uint32_t caps;
45 struct amdgpu_bo *csa_obj; 45 struct amdgpu_bo *csa_obj;
46 uint64_t csa_vmid0_addr; 46 uint64_t csa_vmid0_addr;
47 bool chained_ib_support;
47 uint32_t reg_val_offs; 48 uint32_t reg_val_offs;
48 struct mutex lock; 49 struct mutex lock;
49 struct amdgpu_irq_src ack_irq; 50 struct amdgpu_irq_src ack_irq;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 69543d4eef34..3c613c66d47d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -936,6 +936,13 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
936 goto out; 936 goto out;
937 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 937 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
938 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 938 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
939
940 /* chain ib ucode isn't formal released, just disable it by far
941 * TODO: when ucod ready we should use ucode version to judge if
942 * chain-ib support or not.
943 */
944 adev->virt.chained_ib_support = false;
945
939 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 946 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
940 947
941 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 948 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
index 575d7aed5d32..719587b8b0cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.h
+++ b/drivers/gpu/drm/amd/amdgpu/vi.h
@@ -28,4 +28,116 @@ void vi_srbm_select(struct amdgpu_device *adev,
28 u32 me, u32 pipe, u32 queue, u32 vmid); 28 u32 me, u32 pipe, u32 queue, u32 vmid);
29int vi_set_ip_blocks(struct amdgpu_device *adev); 29int vi_set_ip_blocks(struct amdgpu_device *adev);
30 30
31struct amdgpu_ce_ib_state
32{
33 uint32_t ce_ib_completion_status;
34 uint32_t ce_constegnine_count;
35 uint32_t ce_ibOffset_ib1;
36 uint32_t ce_ibOffset_ib2;
37}; /* Total of 4 DWORD */
38
39struct amdgpu_de_ib_state
40{
41 uint32_t ib_completion_status;
42 uint32_t de_constEngine_count;
43 uint32_t ib_offset_ib1;
44 uint32_t ib_offset_ib2;
45 uint32_t preamble_begin_ib1;
46 uint32_t preamble_begin_ib2;
47 uint32_t preamble_end_ib1;
48 uint32_t preamble_end_ib2;
49 uint32_t draw_indirect_baseLo;
50 uint32_t draw_indirect_baseHi;
51 uint32_t disp_indirect_baseLo;
52 uint32_t disp_indirect_baseHi;
53 uint32_t gds_backup_addrlo;
54 uint32_t gds_backup_addrhi;
55 uint32_t index_base_addrlo;
56 uint32_t index_base_addrhi;
57 uint32_t sample_cntl;
58}; /* Total of 17 DWORD */
59
60struct amdgpu_ce_ib_state_chained_ib
61{
62 /* section of non chained ib part */
63 uint32_t ce_ib_completion_status;
64 uint32_t ce_constegnine_count;
65 uint32_t ce_ibOffset_ib1;
66 uint32_t ce_ibOffset_ib2;
67
68 /* section of chained ib */
69 uint32_t ce_chainib_addrlo_ib1;
70 uint32_t ce_chainib_addrlo_ib2;
71 uint32_t ce_chainib_addrhi_ib1;
72 uint32_t ce_chainib_addrhi_ib2;
73 uint32_t ce_chainib_size_ib1;
74 uint32_t ce_chainib_size_ib2;
75}; /* total 10 DWORD */
76
77struct amdgpu_de_ib_state_chained_ib
78{
79 /* section of non chained ib part */
80 uint32_t ib_completion_status;
81 uint32_t de_constEngine_count;
82 uint32_t ib_offset_ib1;
83 uint32_t ib_offset_ib2;
84
85 /* section of chained ib */
86 uint32_t chain_ib_addrlo_ib1;
87 uint32_t chain_ib_addrlo_ib2;
88 uint32_t chain_ib_addrhi_ib1;
89 uint32_t chain_ib_addrhi_ib2;
90 uint32_t chain_ib_size_ib1;
91 uint32_t chain_ib_size_ib2;
92
93 /* section of non chained ib part */
94 uint32_t preamble_begin_ib1;
95 uint32_t preamble_begin_ib2;
96 uint32_t preamble_end_ib1;
97 uint32_t preamble_end_ib2;
98
99 /* section of chained ib */
100 uint32_t chain_ib_pream_addrlo_ib1;
101 uint32_t chain_ib_pream_addrlo_ib2;
102 uint32_t chain_ib_pream_addrhi_ib1;
103 uint32_t chain_ib_pream_addrhi_ib2;
104
105 /* section of non chained ib part */
106 uint32_t draw_indirect_baseLo;
107 uint32_t draw_indirect_baseHi;
108 uint32_t disp_indirect_baseLo;
109 uint32_t disp_indirect_baseHi;
110 uint32_t gds_backup_addrlo;
111 uint32_t gds_backup_addrhi;
112 uint32_t index_base_addrlo;
113 uint32_t index_base_addrhi;
114 uint32_t sample_cntl;
115}; /* Total of 27 DWORD */
116
117struct amdgpu_gfx_meta_data
118{
119 /* 4 DWORD, address must be 4KB aligned */
120 struct amdgpu_ce_ib_state ce_payload;
121 uint32_t reserved1[60];
122 /* 17 DWORD, address must be 64B aligned */
123 struct amdgpu_de_ib_state de_payload;
124 /* PFP IB base address which get pre-empted */
125 uint32_t DeIbBaseAddrLo;
126 uint32_t DeIbBaseAddrHi;
127 uint32_t reserved2[941];
128}; /* Total of 4K Bytes */
129
130struct amdgpu_gfx_meta_data_chained_ib
131{
132 /* 10 DWORD, address must be 4KB aligned */
133 struct amdgpu_ce_ib_state_chained_ib ce_payload;
134 uint32_t reserved1[54];
135 /* 27 DWORD, address must be 64B aligned */
136 struct amdgpu_de_ib_state_chained_ib de_payload;
137 /* PFP IB base address which get pre-empted */
138 uint32_t DeIbBaseAddrLo;
139 uint32_t DeIbBaseAddrHi;
140 uint32_t reserved2[931];
141}; /* Total of 4K Bytes */
142
31#endif 143#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-24 03:12:15 -0400