diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 50 |
1 files changed, 22 insertions, 28 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 7b660db36931..161652bb3d6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | |||
| @@ -624,36 +624,25 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, | |||
| 624 | * | 624 | * |
| 625 | * Global and local mutex must be locked! | 625 | * Global and local mutex must be locked! |
| 626 | */ | 626 | */ |
| 627 | static int amdgpu_vm_update_ptes(struct amdgpu_device *adev, | 627 | static void amdgpu_vm_update_ptes(struct amdgpu_device *adev, |
| 628 | struct amdgpu_gart *gtt, | 628 | struct amdgpu_gart *gtt, |
| 629 | uint32_t gtt_flags, | 629 | uint32_t gtt_flags, |
| 630 | struct amdgpu_vm *vm, | 630 | struct amdgpu_vm *vm, |
| 631 | struct amdgpu_ib *ib, | 631 | struct amdgpu_ib *ib, |
| 632 | uint64_t start, uint64_t end, | 632 | uint64_t start, uint64_t end, |
| 633 | uint64_t dst, uint32_t flags) | 633 | uint64_t dst, uint32_t flags) |
| 634 | { | 634 | { |
| 635 | uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; | 635 | uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; |
| 636 | uint64_t last_pte = ~0, last_dst = ~0; | 636 | uint64_t last_pte = ~0, last_dst = ~0; |
| 637 | void *owner = AMDGPU_FENCE_OWNER_VM; | ||
| 638 | unsigned count = 0; | 637 | unsigned count = 0; |
| 639 | uint64_t addr; | 638 | uint64_t addr; |
| 640 | 639 | ||
| 641 | /* sync to everything on unmapping */ | ||
| 642 | if (!(flags & AMDGPU_PTE_VALID)) | ||
| 643 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | ||
| 644 | |||
| 645 | /* walk over the address space and update the page tables */ | 640 | /* walk over the address space and update the page tables */ |
| 646 | for (addr = start; addr < end; ) { | 641 | for (addr = start; addr < end; ) { |
| 647 | uint64_t pt_idx = addr >> amdgpu_vm_block_size; | 642 | uint64_t pt_idx = addr >> amdgpu_vm_block_size; |
| 648 | struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj; | 643 | struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj; |
| 649 | unsigned nptes; | 644 | unsigned nptes; |
| 650 | uint64_t pte; | 645 | uint64_t pte; |
| 651 | int r; | ||
| 652 | |||
| 653 | amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv, owner); | ||
| 654 | r = reservation_object_reserve_shared(pt->tbo.resv); | ||
| 655 | if (r) | ||
| 656 | return r; | ||
| 657 | 646 | ||
| 658 | if ((addr & ~mask) == (end & ~mask)) | 647 | if ((addr & ~mask) == (end & ~mask)) |
| 659 | nptes = end - addr; | 648 | nptes = end - addr; |
| @@ -687,8 +676,6 @@ static int amdgpu_vm_update_ptes(struct amdgpu_device *adev, | |||
| 687 | last_pte, last_pte + 8 * count, | 676 | last_pte, last_pte + 8 * count, |
| 688 | last_dst, flags); | 677 | last_dst, flags); |
| 689 | } | 678 | } |
| 690 | |||
| 691 | return 0; | ||
| 692 | } | 679 | } |
| 693 | 680 | ||
| 694 | /** | 681 | /** |
| @@ -716,11 +703,16 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |||
| 716 | struct fence **fence) | 703 | struct fence **fence) |
| 717 | { | 704 | { |
| 718 | struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; | 705 | struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; |
| 706 | void *owner = AMDGPU_FENCE_OWNER_VM; | ||
| 719 | unsigned nptes, ncmds, ndw; | 707 | unsigned nptes, ncmds, ndw; |
| 720 | struct amdgpu_ib *ib; | 708 | struct amdgpu_ib *ib; |
| 721 | struct fence *f = NULL; | 709 | struct fence *f = NULL; |
| 722 | int r; | 710 | int r; |
| 723 | 711 | ||
| 712 | /* sync to everything on unmapping */ | ||
| 713 | if (!(flags & AMDGPU_PTE_VALID)) | ||
| 714 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | ||
| 715 | |||
| 724 | nptes = last - start + 1; | 716 | nptes = last - start + 1; |
| 725 | 717 | ||
| 726 | /* | 718 | /* |
| @@ -761,15 +753,17 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |||
| 761 | return r; | 753 | return r; |
| 762 | } | 754 | } |
| 763 | 755 | ||
| 764 | ib->length_dw = 0; | 756 | r = amdgpu_sync_resv(adev, &ib->sync, vm->page_directory->tbo.resv, |
| 757 | owner); | ||
| 758 | if (r) | ||
| 759 | goto error_free; | ||
| 765 | 760 | ||
| 766 | r = amdgpu_vm_update_ptes(adev, gtt, gtt_flags, vm, ib, start, | 761 | r = reservation_object_reserve_shared(vm->page_directory->tbo.resv); |
| 767 | last + 1, addr, flags); | 762 | if (r) |
| 768 | if (r) { | 763 | goto error_free; |
| 769 | amdgpu_ib_free(adev, ib); | 764 | |
| 770 | kfree(ib); | 765 | amdgpu_vm_update_ptes(adev, gtt, gtt_flags, vm, ib, start, last + 1, |
| 771 | return r; | 766 | addr, flags); |
| 772 | } | ||
| 773 | 767 | ||
| 774 | amdgpu_vm_pad_ib(adev, ib); | 768 | amdgpu_vm_pad_ib(adev, ib); |
| 775 | WARN_ON(ib->length_dw > ndw); | 769 | WARN_ON(ib->length_dw > ndw); |
