diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 |
4 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index b65e18101108..e860412043bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | |||
| @@ -212,6 +212,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) | |||
| 212 | } | 212 | } |
| 213 | 213 | ||
| 214 | if (amdgpu_device_is_px(dev)) { | 214 | if (amdgpu_device_is_px(dev)) { |
| 215 | dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP); | ||
| 215 | pm_runtime_use_autosuspend(dev->dev); | 216 | pm_runtime_use_autosuspend(dev->dev); |
| 216 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | 217 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); |
| 217 | pm_runtime_set_active(dev->dev); | 218 | pm_runtime_set_active(dev->dev); |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 698fd8a2f775..889e443eeee7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | |||
| @@ -406,6 +406,7 @@ struct amdgpu_crtc { | |||
| 406 | struct amdgpu_flip_work *pflip_works; | 406 | struct amdgpu_flip_work *pflip_works; |
| 407 | enum amdgpu_flip_status pflip_status; | 407 | enum amdgpu_flip_status pflip_status; |
| 408 | int deferred_flip_completion; | 408 | int deferred_flip_completion; |
| 409 | u64 last_flip_vblank; | ||
| 409 | /* pll sharing */ | 410 | /* pll sharing */ |
| 410 | struct amdgpu_atom_ss ss; | 411 | struct amdgpu_atom_ss ss; |
| 411 | bool ss_enabled; | 412 | bool ss_enabled; |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 942b5ebc6dc2..ead851413c0a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | |||
| @@ -652,12 +652,14 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, | |||
| 652 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | 652 | struct ttm_bo_global *glob = adev->mman.bdev.glob; |
| 653 | struct amdgpu_vm_bo_base *bo_base; | 653 | struct amdgpu_vm_bo_base *bo_base; |
| 654 | 654 | ||
| 655 | #if 0 | ||
| 655 | if (vm->bulk_moveable) { | 656 | if (vm->bulk_moveable) { |
| 656 | spin_lock(&glob->lru_lock); | 657 | spin_lock(&glob->lru_lock); |
| 657 | ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move); | 658 | ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move); |
| 658 | spin_unlock(&glob->lru_lock); | 659 | spin_unlock(&glob->lru_lock); |
| 659 | return; | 660 | return; |
| 660 | } | 661 | } |
| 662 | #endif | ||
| 661 | 663 | ||
| 662 | memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move)); | 664 | memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move)); |
| 663 | 665 | ||
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 127b85983e8f..c816e55d43a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | |||
| @@ -128,7 +128,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { | |||
| 128 | 128 | ||
| 129 | static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = | 129 | static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = |
| 130 | { | 130 | { |
| 131 | SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), | 131 | SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), |
| 132 | SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), | 132 | SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), |
| 133 | SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), | 133 | SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), |
| 134 | SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), | 134 | SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), |
| @@ -158,7 +158,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = | |||
| 158 | }; | 158 | }; |
| 159 | 159 | ||
| 160 | static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { | 160 | static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { |
| 161 | SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), | 161 | SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), |
| 162 | SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), | 162 | SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), |
| 163 | SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), | 163 | SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), |
| 164 | SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), | 164 | SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), |
