aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu/vi.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vi.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c988
1 files changed, 216 insertions, 772 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index c0d9aad7126f..25c0a71b257d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -121,8 +121,8 @@ static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
121 u32 r; 121 u32 r;
122 122
123 spin_lock_irqsave(&adev->smc_idx_lock, flags); 123 spin_lock_irqsave(&adev->smc_idx_lock, flags);
124 WREG32(mmSMC_IND_INDEX_0, (reg)); 124 WREG32(mmSMC_IND_INDEX_11, (reg));
125 r = RREG32(mmSMC_IND_DATA_0); 125 r = RREG32(mmSMC_IND_DATA_11);
126 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 126 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
127 return r; 127 return r;
128} 128}
@@ -132,8 +132,8 @@ static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
132 unsigned long flags; 132 unsigned long flags;
133 133
134 spin_lock_irqsave(&adev->smc_idx_lock, flags); 134 spin_lock_irqsave(&adev->smc_idx_lock, flags);
135 WREG32(mmSMC_IND_INDEX_0, (reg)); 135 WREG32(mmSMC_IND_INDEX_11, (reg));
136 WREG32(mmSMC_IND_DATA_0, (v)); 136 WREG32(mmSMC_IND_DATA_11, (v));
137 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 137 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
138} 138}
139 139
@@ -437,12 +437,12 @@ static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
437 /* take the smc lock since we are using the smc index */ 437 /* take the smc lock since we are using the smc index */
438 spin_lock_irqsave(&adev->smc_idx_lock, flags); 438 spin_lock_irqsave(&adev->smc_idx_lock, flags);
439 /* set rom index to 0 */ 439 /* set rom index to 0 */
440 WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX); 440 WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);
441 WREG32(mmSMC_IND_DATA_0, 0); 441 WREG32(mmSMC_IND_DATA_11, 0);
442 /* set index to data for continous read */ 442 /* set index to data for continous read */
443 WREG32(mmSMC_IND_INDEX_0, ixROM_DATA); 443 WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);
444 for (i = 0; i < length_dw; i++) 444 for (i = 0; i < length_dw; i++)
445 dw_ptr[i] = RREG32(mmSMC_IND_DATA_0); 445 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);
446 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 446 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
447 447
448 return true; 448 return true;
@@ -556,21 +556,100 @@ static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] =
556 {mmPA_SC_RASTER_CONFIG_1, false, true}, 556 {mmPA_SC_RASTER_CONFIG_1, false, true},
557}; 557};
558 558
559static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 559static uint32_t vi_get_register_value(struct amdgpu_device *adev,
560 u32 sh_num, u32 reg_offset) 560 bool indexed, u32 se_num,
561{ 561 u32 sh_num, u32 reg_offset)
562 uint32_t val; 562{
563 if (indexed) {
564 uint32_t val;
565 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
566 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
567
568 switch (reg_offset) {
569 case mmCC_RB_BACKEND_DISABLE:
570 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
571 case mmGC_USER_RB_BACKEND_DISABLE:
572 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
573 case mmPA_SC_RASTER_CONFIG:
574 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
575 case mmPA_SC_RASTER_CONFIG_1:
576 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
577 }
563 578
564 mutex_lock(&adev->grbm_idx_mutex); 579 mutex_lock(&adev->grbm_idx_mutex);
565 if (se_num != 0xffffffff || sh_num != 0xffffffff) 580 if (se_num != 0xffffffff || sh_num != 0xffffffff)
566 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 581 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
567 582
568 val = RREG32(reg_offset); 583 val = RREG32(reg_offset);
569 584
570 if (se_num != 0xffffffff || sh_num != 0xffffffff) 585 if (se_num != 0xffffffff || sh_num != 0xffffffff)
571 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 586 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
572 mutex_unlock(&adev->grbm_idx_mutex); 587 mutex_unlock(&adev->grbm_idx_mutex);
573 return val; 588 return val;
589 } else {
590 unsigned idx;
591
592 switch (reg_offset) {
593 case mmGB_ADDR_CONFIG:
594 return adev->gfx.config.gb_addr_config;
595 case mmMC_ARB_RAMCFG:
596 return adev->gfx.config.mc_arb_ramcfg;
597 case mmGB_TILE_MODE0:
598 case mmGB_TILE_MODE1:
599 case mmGB_TILE_MODE2:
600 case mmGB_TILE_MODE3:
601 case mmGB_TILE_MODE4:
602 case mmGB_TILE_MODE5:
603 case mmGB_TILE_MODE6:
604 case mmGB_TILE_MODE7:
605 case mmGB_TILE_MODE8:
606 case mmGB_TILE_MODE9:
607 case mmGB_TILE_MODE10:
608 case mmGB_TILE_MODE11:
609 case mmGB_TILE_MODE12:
610 case mmGB_TILE_MODE13:
611 case mmGB_TILE_MODE14:
612 case mmGB_TILE_MODE15:
613 case mmGB_TILE_MODE16:
614 case mmGB_TILE_MODE17:
615 case mmGB_TILE_MODE18:
616 case mmGB_TILE_MODE19:
617 case mmGB_TILE_MODE20:
618 case mmGB_TILE_MODE21:
619 case mmGB_TILE_MODE22:
620 case mmGB_TILE_MODE23:
621 case mmGB_TILE_MODE24:
622 case mmGB_TILE_MODE25:
623 case mmGB_TILE_MODE26:
624 case mmGB_TILE_MODE27:
625 case mmGB_TILE_MODE28:
626 case mmGB_TILE_MODE29:
627 case mmGB_TILE_MODE30:
628 case mmGB_TILE_MODE31:
629 idx = (reg_offset - mmGB_TILE_MODE0);
630 return adev->gfx.config.tile_mode_array[idx];
631 case mmGB_MACROTILE_MODE0:
632 case mmGB_MACROTILE_MODE1:
633 case mmGB_MACROTILE_MODE2:
634 case mmGB_MACROTILE_MODE3:
635 case mmGB_MACROTILE_MODE4:
636 case mmGB_MACROTILE_MODE5:
637 case mmGB_MACROTILE_MODE6:
638 case mmGB_MACROTILE_MODE7:
639 case mmGB_MACROTILE_MODE8:
640 case mmGB_MACROTILE_MODE9:
641 case mmGB_MACROTILE_MODE10:
642 case mmGB_MACROTILE_MODE11:
643 case mmGB_MACROTILE_MODE12:
644 case mmGB_MACROTILE_MODE13:
645 case mmGB_MACROTILE_MODE14:
646 case mmGB_MACROTILE_MODE15:
647 idx = (reg_offset - mmGB_MACROTILE_MODE0);
648 return adev->gfx.config.macrotile_mode_array[idx];
649 default:
650 return RREG32(reg_offset);
651 }
652 }
574} 653}
575 654
576static int vi_read_register(struct amdgpu_device *adev, u32 se_num, 655static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
@@ -605,10 +684,9 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
605 if (reg_offset != asic_register_entry->reg_offset) 684 if (reg_offset != asic_register_entry->reg_offset)
606 continue; 685 continue;
607 if (!asic_register_entry->untouched) 686 if (!asic_register_entry->untouched)
608 *value = asic_register_entry->grbm_indexed ? 687 *value = vi_get_register_value(adev,
609 vi_read_indexed_register(adev, se_num, 688 asic_register_entry->grbm_indexed,
610 sh_num, reg_offset) : 689 se_num, sh_num, reg_offset);
611 RREG32(reg_offset);
612 return 0; 690 return 0;
613 } 691 }
614 } 692 }
@@ -618,10 +696,9 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
618 continue; 696 continue;
619 697
620 if (!vi_allowed_read_registers[i].untouched) 698 if (!vi_allowed_read_registers[i].untouched)
621 *value = vi_allowed_read_registers[i].grbm_indexed ? 699 *value = vi_get_register_value(adev,
622 vi_read_indexed_register(adev, se_num, 700 vi_allowed_read_registers[i].grbm_indexed,
623 sh_num, reg_offset) : 701 se_num, sh_num, reg_offset);
624 RREG32(reg_offset);
625 return 0; 702 return 0;
626 } 703 }
627 return -EINVAL; 704 return -EINVAL;
@@ -652,18 +729,6 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
652 return -EINVAL; 729 return -EINVAL;
653} 730}
654 731
655static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
656{
657 u32 tmp = RREG32(mmBIOS_SCRATCH_3);
658
659 if (hung)
660 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
661 else
662 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
663
664 WREG32(mmBIOS_SCRATCH_3, tmp);
665}
666
667/** 732/**
668 * vi_asic_reset - soft reset GPU 733 * vi_asic_reset - soft reset GPU
669 * 734 *
@@ -677,11 +742,11 @@ static int vi_asic_reset(struct amdgpu_device *adev)
677{ 742{
678 int r; 743 int r;
679 744
680 vi_set_bios_scratch_engine_hung(adev, true); 745 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
681 746
682 r = vi_gpu_pci_config_reset(adev); 747 r = vi_gpu_pci_config_reset(adev);
683 748
684 vi_set_bios_scratch_engine_hung(adev, false); 749 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
685 750
686 return r; 751 return r;
687} 752}
@@ -781,734 +846,6 @@ static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
781 WREG32(mmBIF_DOORBELL_APER_EN, tmp); 846 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
782} 847}
783 848
784/* topaz has no DCE, UVD, VCE */
785static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
786{
787 /* ORDER MATTERS! */
788 {
789 .type = AMD_IP_BLOCK_TYPE_COMMON,
790 .major = 2,
791 .minor = 0,
792 .rev = 0,
793 .funcs = &vi_common_ip_funcs,
794 },
795 {
796 .type = AMD_IP_BLOCK_TYPE_GMC,
797 .major = 7,
798 .minor = 4,
799 .rev = 0,
800 .funcs = &gmc_v7_0_ip_funcs,
801 },
802 {
803 .type = AMD_IP_BLOCK_TYPE_IH,
804 .major = 2,
805 .minor = 4,
806 .rev = 0,
807 .funcs = &iceland_ih_ip_funcs,
808 },
809 {
810 .type = AMD_IP_BLOCK_TYPE_SMC,
811 .major = 7,
812 .minor = 1,
813 .rev = 0,
814 .funcs = &amdgpu_pp_ip_funcs,
815 },
816 {
817 .type = AMD_IP_BLOCK_TYPE_GFX,
818 .major = 8,
819 .minor = 0,
820 .rev = 0,
821 .funcs = &gfx_v8_0_ip_funcs,
822 },
823 {
824 .type = AMD_IP_BLOCK_TYPE_SDMA,
825 .major = 2,
826 .minor = 4,
827 .rev = 0,
828 .funcs = &sdma_v2_4_ip_funcs,
829 },
830};
831
832static const struct amdgpu_ip_block_version topaz_ip_blocks_vd[] =
833{
834 /* ORDER MATTERS! */
835 {
836 .type = AMD_IP_BLOCK_TYPE_COMMON,
837 .major = 2,
838 .minor = 0,
839 .rev = 0,
840 .funcs = &vi_common_ip_funcs,
841 },
842 {
843 .type = AMD_IP_BLOCK_TYPE_GMC,
844 .major = 7,
845 .minor = 4,
846 .rev = 0,
847 .funcs = &gmc_v7_0_ip_funcs,
848 },
849 {
850 .type = AMD_IP_BLOCK_TYPE_IH,
851 .major = 2,
852 .minor = 4,
853 .rev = 0,
854 .funcs = &iceland_ih_ip_funcs,
855 },
856 {
857 .type = AMD_IP_BLOCK_TYPE_SMC,
858 .major = 7,
859 .minor = 1,
860 .rev = 0,
861 .funcs = &amdgpu_pp_ip_funcs,
862 },
863 {
864 .type = AMD_IP_BLOCK_TYPE_DCE,
865 .major = 1,
866 .minor = 0,
867 .rev = 0,
868 .funcs = &dce_virtual_ip_funcs,
869 },
870 {
871 .type = AMD_IP_BLOCK_TYPE_GFX,
872 .major = 8,
873 .minor = 0,
874 .rev = 0,
875 .funcs = &gfx_v8_0_ip_funcs,
876 },
877 {
878 .type = AMD_IP_BLOCK_TYPE_SDMA,
879 .major = 2,
880 .minor = 4,
881 .rev = 0,
882 .funcs = &sdma_v2_4_ip_funcs,
883 },
884};
885
886static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
887{
888 /* ORDER MATTERS! */
889 {
890 .type = AMD_IP_BLOCK_TYPE_COMMON,
891 .major = 2,
892 .minor = 0,
893 .rev = 0,
894 .funcs = &vi_common_ip_funcs,
895 },
896 {
897 .type = AMD_IP_BLOCK_TYPE_GMC,
898 .major = 8,
899 .minor = 0,
900 .rev = 0,
901 .funcs = &gmc_v8_0_ip_funcs,
902 },
903 {
904 .type = AMD_IP_BLOCK_TYPE_IH,
905 .major = 3,
906 .minor = 0,
907 .rev = 0,
908 .funcs = &tonga_ih_ip_funcs,
909 },
910 {
911 .type = AMD_IP_BLOCK_TYPE_SMC,
912 .major = 7,
913 .minor = 1,
914 .rev = 0,
915 .funcs = &amdgpu_pp_ip_funcs,
916 },
917 {
918 .type = AMD_IP_BLOCK_TYPE_DCE,
919 .major = 10,
920 .minor = 0,
921 .rev = 0,
922 .funcs = &dce_v10_0_ip_funcs,
923 },
924 {
925 .type = AMD_IP_BLOCK_TYPE_GFX,
926 .major = 8,
927 .minor = 0,
928 .rev = 0,
929 .funcs = &gfx_v8_0_ip_funcs,
930 },
931 {
932 .type = AMD_IP_BLOCK_TYPE_SDMA,
933 .major = 3,
934 .minor = 0,
935 .rev = 0,
936 .funcs = &sdma_v3_0_ip_funcs,
937 },
938 {
939 .type = AMD_IP_BLOCK_TYPE_UVD,
940 .major = 5,
941 .minor = 0,
942 .rev = 0,
943 .funcs = &uvd_v5_0_ip_funcs,
944 },
945 {
946 .type = AMD_IP_BLOCK_TYPE_VCE,
947 .major = 3,
948 .minor = 0,
949 .rev = 0,
950 .funcs = &vce_v3_0_ip_funcs,
951 },
952};
953
954static const struct amdgpu_ip_block_version tonga_ip_blocks_vd[] =
955{
956 /* ORDER MATTERS! */
957 {
958 .type = AMD_IP_BLOCK_TYPE_COMMON,
959 .major = 2,
960 .minor = 0,
961 .rev = 0,
962 .funcs = &vi_common_ip_funcs,
963 },
964 {
965 .type = AMD_IP_BLOCK_TYPE_GMC,
966 .major = 8,
967 .minor = 0,
968 .rev = 0,
969 .funcs = &gmc_v8_0_ip_funcs,
970 },
971 {
972 .type = AMD_IP_BLOCK_TYPE_IH,
973 .major = 3,
974 .minor = 0,
975 .rev = 0,
976 .funcs = &tonga_ih_ip_funcs,
977 },
978 {
979 .type = AMD_IP_BLOCK_TYPE_SMC,
980 .major = 7,
981 .minor = 1,
982 .rev = 0,
983 .funcs = &amdgpu_pp_ip_funcs,
984 },
985 {
986 .type = AMD_IP_BLOCK_TYPE_DCE,
987 .major = 10,
988 .minor = 0,
989 .rev = 0,
990 .funcs = &dce_virtual_ip_funcs,
991 },
992 {
993 .type = AMD_IP_BLOCK_TYPE_GFX,
994 .major = 8,
995 .minor = 0,
996 .rev = 0,
997 .funcs = &gfx_v8_0_ip_funcs,
998 },
999 {
1000 .type = AMD_IP_BLOCK_TYPE_SDMA,
1001 .major = 3,
1002 .minor = 0,
1003 .rev = 0,
1004 .funcs = &sdma_v3_0_ip_funcs,
1005 },
1006 {
1007 .type = AMD_IP_BLOCK_TYPE_UVD,
1008 .major = 5,
1009 .minor = 0,
1010 .rev = 0,
1011 .funcs = &uvd_v5_0_ip_funcs,
1012 },
1013 {
1014 .type = AMD_IP_BLOCK_TYPE_VCE,
1015 .major = 3,
1016 .minor = 0,
1017 .rev = 0,
1018 .funcs = &vce_v3_0_ip_funcs,
1019 },
1020};
1021
1022static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
1023{
1024 /* ORDER MATTERS! */
1025 {
1026 .type = AMD_IP_BLOCK_TYPE_COMMON,
1027 .major = 2,
1028 .minor = 0,
1029 .rev = 0,
1030 .funcs = &vi_common_ip_funcs,
1031 },
1032 {
1033 .type = AMD_IP_BLOCK_TYPE_GMC,
1034 .major = 8,
1035 .minor = 5,
1036 .rev = 0,
1037 .funcs = &gmc_v8_0_ip_funcs,
1038 },
1039 {
1040 .type = AMD_IP_BLOCK_TYPE_IH,
1041 .major = 3,
1042 .minor = 0,
1043 .rev = 0,
1044 .funcs = &tonga_ih_ip_funcs,
1045 },
1046 {
1047 .type = AMD_IP_BLOCK_TYPE_SMC,
1048 .major = 7,
1049 .minor = 1,
1050 .rev = 0,
1051 .funcs = &amdgpu_pp_ip_funcs,
1052 },
1053 {
1054 .type = AMD_IP_BLOCK_TYPE_DCE,
1055 .major = 10,
1056 .minor = 1,
1057 .rev = 0,
1058 .funcs = &dce_v10_0_ip_funcs,
1059 },
1060 {
1061 .type = AMD_IP_BLOCK_TYPE_GFX,
1062 .major = 8,
1063 .minor = 0,
1064 .rev = 0,
1065 .funcs = &gfx_v8_0_ip_funcs,
1066 },
1067 {
1068 .type = AMD_IP_BLOCK_TYPE_SDMA,
1069 .major = 3,
1070 .minor = 0,
1071 .rev = 0,
1072 .funcs = &sdma_v3_0_ip_funcs,
1073 },
1074 {
1075 .type = AMD_IP_BLOCK_TYPE_UVD,
1076 .major = 6,
1077 .minor = 0,
1078 .rev = 0,
1079 .funcs = &uvd_v6_0_ip_funcs,
1080 },
1081 {
1082 .type = AMD_IP_BLOCK_TYPE_VCE,
1083 .major = 3,
1084 .minor = 0,
1085 .rev = 0,
1086 .funcs = &vce_v3_0_ip_funcs,
1087 },
1088};
1089
1090static const struct amdgpu_ip_block_version fiji_ip_blocks_vd[] =
1091{
1092 /* ORDER MATTERS! */
1093 {
1094 .type = AMD_IP_BLOCK_TYPE_COMMON,
1095 .major = 2,
1096 .minor = 0,
1097 .rev = 0,
1098 .funcs = &vi_common_ip_funcs,
1099 },
1100 {
1101 .type = AMD_IP_BLOCK_TYPE_GMC,
1102 .major = 8,
1103 .minor = 5,
1104 .rev = 0,
1105 .funcs = &gmc_v8_0_ip_funcs,
1106 },
1107 {
1108 .type = AMD_IP_BLOCK_TYPE_IH,
1109 .major = 3,
1110 .minor = 0,
1111 .rev = 0,
1112 .funcs = &tonga_ih_ip_funcs,
1113 },
1114 {
1115 .type = AMD_IP_BLOCK_TYPE_SMC,
1116 .major = 7,
1117 .minor = 1,
1118 .rev = 0,
1119 .funcs = &amdgpu_pp_ip_funcs,
1120 },
1121 {
1122 .type = AMD_IP_BLOCK_TYPE_DCE,
1123 .major = 10,
1124 .minor = 1,
1125 .rev = 0,
1126 .funcs = &dce_virtual_ip_funcs,
1127 },
1128 {
1129 .type = AMD_IP_BLOCK_TYPE_GFX,
1130 .major = 8,
1131 .minor = 0,
1132 .rev = 0,
1133 .funcs = &gfx_v8_0_ip_funcs,
1134 },
1135 {
1136 .type = AMD_IP_BLOCK_TYPE_SDMA,
1137 .major = 3,
1138 .minor = 0,
1139 .rev = 0,
1140 .funcs = &sdma_v3_0_ip_funcs,
1141 },
1142 {
1143 .type = AMD_IP_BLOCK_TYPE_UVD,
1144 .major = 6,
1145 .minor = 0,
1146 .rev = 0,
1147 .funcs = &uvd_v6_0_ip_funcs,
1148 },
1149 {
1150 .type = AMD_IP_BLOCK_TYPE_VCE,
1151 .major = 3,
1152 .minor = 0,
1153 .rev = 0,
1154 .funcs = &vce_v3_0_ip_funcs,
1155 },
1156};
1157
1158static const struct amdgpu_ip_block_version polaris11_ip_blocks[] =
1159{
1160 /* ORDER MATTERS! */
1161 {
1162 .type = AMD_IP_BLOCK_TYPE_COMMON,
1163 .major = 2,
1164 .minor = 0,
1165 .rev = 0,
1166 .funcs = &vi_common_ip_funcs,
1167 },
1168 {
1169 .type = AMD_IP_BLOCK_TYPE_GMC,
1170 .major = 8,
1171 .minor = 1,
1172 .rev = 0,
1173 .funcs = &gmc_v8_0_ip_funcs,
1174 },
1175 {
1176 .type = AMD_IP_BLOCK_TYPE_IH,
1177 .major = 3,
1178 .minor = 1,
1179 .rev = 0,
1180 .funcs = &tonga_ih_ip_funcs,
1181 },
1182 {
1183 .type = AMD_IP_BLOCK_TYPE_SMC,
1184 .major = 7,
1185 .minor = 2,
1186 .rev = 0,
1187 .funcs = &amdgpu_pp_ip_funcs,
1188 },
1189 {
1190 .type = AMD_IP_BLOCK_TYPE_DCE,
1191 .major = 11,
1192 .minor = 2,
1193 .rev = 0,
1194 .funcs = &dce_v11_0_ip_funcs,
1195 },
1196 {
1197 .type = AMD_IP_BLOCK_TYPE_GFX,
1198 .major = 8,
1199 .minor = 0,
1200 .rev = 0,
1201 .funcs = &gfx_v8_0_ip_funcs,
1202 },
1203 {
1204 .type = AMD_IP_BLOCK_TYPE_SDMA,
1205 .major = 3,
1206 .minor = 1,
1207 .rev = 0,
1208 .funcs = &sdma_v3_0_ip_funcs,
1209 },
1210 {
1211 .type = AMD_IP_BLOCK_TYPE_UVD,
1212 .major = 6,
1213 .minor = 3,
1214 .rev = 0,
1215 .funcs = &uvd_v6_0_ip_funcs,
1216 },
1217 {
1218 .type = AMD_IP_BLOCK_TYPE_VCE,
1219 .major = 3,
1220 .minor = 4,
1221 .rev = 0,
1222 .funcs = &vce_v3_0_ip_funcs,
1223 },
1224};
1225
1226static const struct amdgpu_ip_block_version polaris11_ip_blocks_vd[] =
1227{
1228 /* ORDER MATTERS! */
1229 {
1230 .type = AMD_IP_BLOCK_TYPE_COMMON,
1231 .major = 2,
1232 .minor = 0,
1233 .rev = 0,
1234 .funcs = &vi_common_ip_funcs,
1235 },
1236 {
1237 .type = AMD_IP_BLOCK_TYPE_GMC,
1238 .major = 8,
1239 .minor = 1,
1240 .rev = 0,
1241 .funcs = &gmc_v8_0_ip_funcs,
1242 },
1243 {
1244 .type = AMD_IP_BLOCK_TYPE_IH,
1245 .major = 3,
1246 .minor = 1,
1247 .rev = 0,
1248 .funcs = &tonga_ih_ip_funcs,
1249 },
1250 {
1251 .type = AMD_IP_BLOCK_TYPE_SMC,
1252 .major = 7,
1253 .minor = 2,
1254 .rev = 0,
1255 .funcs = &amdgpu_pp_ip_funcs,
1256 },
1257 {
1258 .type = AMD_IP_BLOCK_TYPE_DCE,
1259 .major = 11,
1260 .minor = 2,
1261 .rev = 0,
1262 .funcs = &dce_virtual_ip_funcs,
1263 },
1264 {
1265 .type = AMD_IP_BLOCK_TYPE_GFX,
1266 .major = 8,
1267 .minor = 0,
1268 .rev = 0,
1269 .funcs = &gfx_v8_0_ip_funcs,
1270 },
1271 {
1272 .type = AMD_IP_BLOCK_TYPE_SDMA,
1273 .major = 3,
1274 .minor = 1,
1275 .rev = 0,
1276 .funcs = &sdma_v3_0_ip_funcs,
1277 },
1278 {
1279 .type = AMD_IP_BLOCK_TYPE_UVD,
1280 .major = 6,
1281 .minor = 3,
1282 .rev = 0,
1283 .funcs = &uvd_v6_0_ip_funcs,
1284 },
1285 {
1286 .type = AMD_IP_BLOCK_TYPE_VCE,
1287 .major = 3,
1288 .minor = 4,
1289 .rev = 0,
1290 .funcs = &vce_v3_0_ip_funcs,
1291 },
1292};
1293
1294static const struct amdgpu_ip_block_version cz_ip_blocks[] =
1295{
1296 /* ORDER MATTERS! */
1297 {
1298 .type = AMD_IP_BLOCK_TYPE_COMMON,
1299 .major = 2,
1300 .minor = 0,
1301 .rev = 0,
1302 .funcs = &vi_common_ip_funcs,
1303 },
1304 {
1305 .type = AMD_IP_BLOCK_TYPE_GMC,
1306 .major = 8,
1307 .minor = 0,
1308 .rev = 0,
1309 .funcs = &gmc_v8_0_ip_funcs,
1310 },
1311 {
1312 .type = AMD_IP_BLOCK_TYPE_IH,
1313 .major = 3,
1314 .minor = 0,
1315 .rev = 0,
1316 .funcs = &cz_ih_ip_funcs,
1317 },
1318 {
1319 .type = AMD_IP_BLOCK_TYPE_SMC,
1320 .major = 8,
1321 .minor = 0,
1322 .rev = 0,
1323 .funcs = &amdgpu_pp_ip_funcs
1324 },
1325 {
1326 .type = AMD_IP_BLOCK_TYPE_DCE,
1327 .major = 11,
1328 .minor = 0,
1329 .rev = 0,
1330 .funcs = &dce_v11_0_ip_funcs,
1331 },
1332 {
1333 .type = AMD_IP_BLOCK_TYPE_GFX,
1334 .major = 8,
1335 .minor = 0,
1336 .rev = 0,
1337 .funcs = &gfx_v8_0_ip_funcs,
1338 },
1339 {
1340 .type = AMD_IP_BLOCK_TYPE_SDMA,
1341 .major = 3,
1342 .minor = 0,
1343 .rev = 0,
1344 .funcs = &sdma_v3_0_ip_funcs,
1345 },
1346 {
1347 .type = AMD_IP_BLOCK_TYPE_UVD,
1348 .major = 6,
1349 .minor = 0,
1350 .rev = 0,
1351 .funcs = &uvd_v6_0_ip_funcs,
1352 },
1353 {
1354 .type = AMD_IP_BLOCK_TYPE_VCE,
1355 .major = 3,
1356 .minor = 0,
1357 .rev = 0,
1358 .funcs = &vce_v3_0_ip_funcs,
1359 },
1360#if defined(CONFIG_DRM_AMD_ACP)
1361 {
1362 .type = AMD_IP_BLOCK_TYPE_ACP,
1363 .major = 2,
1364 .minor = 2,
1365 .rev = 0,
1366 .funcs = &acp_ip_funcs,
1367 },
1368#endif
1369};
1370
1371static const struct amdgpu_ip_block_version cz_ip_blocks_vd[] =
1372{
1373 /* ORDER MATTERS! */
1374 {
1375 .type = AMD_IP_BLOCK_TYPE_COMMON,
1376 .major = 2,
1377 .minor = 0,
1378 .rev = 0,
1379 .funcs = &vi_common_ip_funcs,
1380 },
1381 {
1382 .type = AMD_IP_BLOCK_TYPE_GMC,
1383 .major = 8,
1384 .minor = 0,
1385 .rev = 0,
1386 .funcs = &gmc_v8_0_ip_funcs,
1387 },
1388 {
1389 .type = AMD_IP_BLOCK_TYPE_IH,
1390 .major = 3,
1391 .minor = 0,
1392 .rev = 0,
1393 .funcs = &cz_ih_ip_funcs,
1394 },
1395 {
1396 .type = AMD_IP_BLOCK_TYPE_SMC,
1397 .major = 8,
1398 .minor = 0,
1399 .rev = 0,
1400 .funcs = &amdgpu_pp_ip_funcs
1401 },
1402 {
1403 .type = AMD_IP_BLOCK_TYPE_DCE,
1404 .major = 11,
1405 .minor = 0,
1406 .rev = 0,
1407 .funcs = &dce_virtual_ip_funcs,
1408 },
1409 {
1410 .type = AMD_IP_BLOCK_TYPE_GFX,
1411 .major = 8,
1412 .minor = 0,
1413 .rev = 0,
1414 .funcs = &gfx_v8_0_ip_funcs,
1415 },
1416 {
1417 .type = AMD_IP_BLOCK_TYPE_SDMA,
1418 .major = 3,
1419 .minor = 0,
1420 .rev = 0,
1421 .funcs = &sdma_v3_0_ip_funcs,
1422 },
1423 {
1424 .type = AMD_IP_BLOCK_TYPE_UVD,
1425 .major = 6,
1426 .minor = 0,
1427 .rev = 0,
1428 .funcs = &uvd_v6_0_ip_funcs,
1429 },
1430 {
1431 .type = AMD_IP_BLOCK_TYPE_VCE,
1432 .major = 3,
1433 .minor = 0,
1434 .rev = 0,
1435 .funcs = &vce_v3_0_ip_funcs,
1436 },
1437#if defined(CONFIG_DRM_AMD_ACP)
1438 {
1439 .type = AMD_IP_BLOCK_TYPE_ACP,
1440 .major = 2,
1441 .minor = 2,
1442 .rev = 0,
1443 .funcs = &acp_ip_funcs,
1444 },
1445#endif
1446};
1447
1448int vi_set_ip_blocks(struct amdgpu_device *adev)
1449{
1450 if (adev->enable_virtual_display) {
1451 switch (adev->asic_type) {
1452 case CHIP_TOPAZ:
1453 adev->ip_blocks = topaz_ip_blocks_vd;
1454 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks_vd);
1455 break;
1456 case CHIP_FIJI:
1457 adev->ip_blocks = fiji_ip_blocks_vd;
1458 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks_vd);
1459 break;
1460 case CHIP_TONGA:
1461 adev->ip_blocks = tonga_ip_blocks_vd;
1462 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks_vd);
1463 break;
1464 case CHIP_POLARIS11:
1465 case CHIP_POLARIS10:
1466 adev->ip_blocks = polaris11_ip_blocks_vd;
1467 adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks_vd);
1468 break;
1469
1470 case CHIP_CARRIZO:
1471 case CHIP_STONEY:
1472 adev->ip_blocks = cz_ip_blocks_vd;
1473 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks_vd);
1474 break;
1475 default:
1476 /* FIXME: not supported yet */
1477 return -EINVAL;
1478 }
1479 } else {
1480 switch (adev->asic_type) {
1481 case CHIP_TOPAZ:
1482 adev->ip_blocks = topaz_ip_blocks;
1483 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
1484 break;
1485 case CHIP_FIJI:
1486 adev->ip_blocks = fiji_ip_blocks;
1487 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
1488 break;
1489 case CHIP_TONGA:
1490 adev->ip_blocks = tonga_ip_blocks;
1491 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
1492 break;
1493 case CHIP_POLARIS11:
1494 case CHIP_POLARIS10:
1495 adev->ip_blocks = polaris11_ip_blocks;
1496 adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
1497 break;
1498 case CHIP_CARRIZO:
1499 case CHIP_STONEY:
1500 adev->ip_blocks = cz_ip_blocks;
1501 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
1502 break;
1503 default:
1504 /* FIXME: not supported yet */
1505 return -EINVAL;
1506 }
1507 }
1508
1509 return 0;
1510}
1511
1512#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044 849#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
1513#define ATI_REV_ID_FUSE_MACRO__SHIFT 9 850#define ATI_REV_ID_FUSE_MACRO__SHIFT 9
1514#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00 851#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
@@ -1593,7 +930,7 @@ static int vi_common_early_init(void *handle)
1593 break; 930 break;
1594 case CHIP_TONGA: 931 case CHIP_TONGA:
1595 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; 932 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
1596 adev->pg_flags = 0; 933 adev->pg_flags = AMD_PG_SUPPORT_UVD;
1597 adev->external_rev_id = adev->rev_id + 0x14; 934 adev->external_rev_id = adev->rev_id + 0x14;
1598 break; 935 break;
1599 case CHIP_POLARIS11: 936 case CHIP_POLARIS11:
@@ -1908,7 +1245,7 @@ static int vi_common_set_powergating_state(void *handle,
1908 return 0; 1245 return 0;
1909} 1246}
1910 1247
1911const struct amd_ip_funcs vi_common_ip_funcs = { 1248static const struct amd_ip_funcs vi_common_ip_funcs = {
1912 .name = "vi_common", 1249 .name = "vi_common",
1913 .early_init = vi_common_early_init, 1250 .early_init = vi_common_early_init,
1914 .late_init = NULL, 1251 .late_init = NULL,
@@ -1925,3 +1262,110 @@ const struct amd_ip_funcs vi_common_ip_funcs = {
1925 .set_powergating_state = vi_common_set_powergating_state, 1262 .set_powergating_state = vi_common_set_powergating_state,
1926}; 1263};
1927 1264
1265static const struct amdgpu_ip_block_version vi_common_ip_block =
1266{
1267 .type = AMD_IP_BLOCK_TYPE_COMMON,
1268 .major = 1,
1269 .minor = 0,
1270 .rev = 0,
1271 .funcs = &vi_common_ip_funcs,
1272};
1273
1274int vi_set_ip_blocks(struct amdgpu_device *adev)
1275{
1276 switch (adev->asic_type) {
1277 case CHIP_TOPAZ:
1278 /* topaz has no DCE, UVD, VCE */
1279 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1280 amdgpu_ip_block_add(adev, &gmc_v7_4_ip_block);
1281 amdgpu_ip_block_add(adev, &iceland_ih_ip_block);
1282 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1283 if (adev->enable_virtual_display)
1284 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1285 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1286 amdgpu_ip_block_add(adev, &sdma_v2_4_ip_block);
1287 break;
1288 case CHIP_FIJI:
1289 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1290 amdgpu_ip_block_add(adev, &gmc_v8_5_ip_block);
1291 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1292 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1293 if (adev->enable_virtual_display)
1294 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1295 else
1296 amdgpu_ip_block_add(adev, &dce_v10_1_ip_block);
1297 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1298 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1299 amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block);
1300 amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
1301 break;
1302 case CHIP_TONGA:
1303 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1304 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1305 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1306 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1307 if (adev->enable_virtual_display)
1308 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1309 else
1310 amdgpu_ip_block_add(adev, &dce_v10_0_ip_block);
1311 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1312 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1313 amdgpu_ip_block_add(adev, &uvd_v5_0_ip_block);
1314 amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
1315 break;
1316 case CHIP_POLARIS11:
1317 case CHIP_POLARIS10:
1318 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1319 amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block);
1320 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1321 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1322 if (adev->enable_virtual_display)
1323 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1324 else
1325 amdgpu_ip_block_add(adev, &dce_v11_2_ip_block);
1326 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1327 amdgpu_ip_block_add(adev, &sdma_v3_1_ip_block);
1328 amdgpu_ip_block_add(adev, &uvd_v6_3_ip_block);
1329 amdgpu_ip_block_add(adev, &vce_v3_4_ip_block);
1330 break;
1331 case CHIP_CARRIZO:
1332 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1333 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1334 amdgpu_ip_block_add(adev, &cz_ih_ip_block);
1335 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1336 if (adev->enable_virtual_display)
1337 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1338 else
1339 amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
1340 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1341 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1342 amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block);
1343 amdgpu_ip_block_add(adev, &vce_v3_1_ip_block);
1344#if defined(CONFIG_DRM_AMD_ACP)
1345 amdgpu_ip_block_add(adev, &acp_ip_block);
1346#endif
1347 break;
1348 case CHIP_STONEY:
1349 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1350 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1351 amdgpu_ip_block_add(adev, &cz_ih_ip_block);
1352 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1353 if (adev->enable_virtual_display)
1354 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1355 else
1356 amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
1357 amdgpu_ip_block_add(adev, &gfx_v8_1_ip_block);
1358 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1359 amdgpu_ip_block_add(adev, &uvd_v6_2_ip_block);
1360 amdgpu_ip_block_add(adev, &vce_v3_4_ip_block);
1361#if defined(CONFIG_DRM_AMD_ACP)
1362 amdgpu_ip_block_add(adev, &acp_ip_block);
1363#endif
1364 break;
1365 default:
1366 /* FIXME: not supported yet */
1367 return -EINVAL;
1368 }
1369
1370 return 0;
1371}
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-02 02:51:45 -0400