diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vce_v3_0.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 34 |
1 files changed, 9 insertions, 25 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index e76bc092becc..0db59d885f04 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | |||
@@ -808,27 +808,6 @@ static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring) | |||
808 | amdgpu_ring_write(ring, seq); | 808 | amdgpu_ring_write(ring, seq); |
809 | } | 809 | } |
810 | 810 | ||
811 | static unsigned vce_v3_0_ring_get_emit_ib_size(struct amdgpu_ring *ring) | ||
812 | { | ||
813 | return | ||
814 | 5; /* vce_v3_0_ring_emit_ib */ | ||
815 | } | ||
816 | |||
817 | static unsigned vce_v3_0_ring_get_dma_frame_size(struct amdgpu_ring *ring) | ||
818 | { | ||
819 | return | ||
820 | 4 + /* vce_v3_0_emit_pipeline_sync */ | ||
821 | 6; /* amdgpu_vce_ring_emit_fence x1 no user fence */ | ||
822 | } | ||
823 | |||
824 | static unsigned vce_v3_0_ring_get_dma_frame_size_vm(struct amdgpu_ring *ring) | ||
825 | { | ||
826 | return | ||
827 | 6 + /* vce_v3_0_emit_vm_flush */ | ||
828 | 4 + /* vce_v3_0_emit_pipeline_sync */ | ||
829 | 6 + 6; /* amdgpu_vce_ring_emit_fence x2 vm fence */ | ||
830 | } | ||
831 | |||
832 | const struct amd_ip_funcs vce_v3_0_ip_funcs = { | 811 | const struct amd_ip_funcs vce_v3_0_ip_funcs = { |
833 | .name = "vce_v3_0", | 812 | .name = "vce_v3_0", |
834 | .early_init = vce_v3_0_early_init, | 813 | .early_init = vce_v3_0_early_init, |
@@ -854,6 +833,10 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = { | |||
854 | .get_wptr = vce_v3_0_ring_get_wptr, | 833 | .get_wptr = vce_v3_0_ring_get_wptr, |
855 | .set_wptr = vce_v3_0_ring_set_wptr, | 834 | .set_wptr = vce_v3_0_ring_set_wptr, |
856 | .parse_cs = amdgpu_vce_ring_parse_cs, | 835 | .parse_cs = amdgpu_vce_ring_parse_cs, |
836 | .emit_frame_size = | ||
837 | 4 + /* vce_v3_0_emit_pipeline_sync */ | ||
838 | 6, /* amdgpu_vce_ring_emit_fence x1 no user fence */ | ||
839 | .emit_ib_size = 5, /* vce_v3_0_ring_emit_ib */ | ||
857 | .emit_ib = amdgpu_vce_ring_emit_ib, | 840 | .emit_ib = amdgpu_vce_ring_emit_ib, |
858 | .emit_fence = amdgpu_vce_ring_emit_fence, | 841 | .emit_fence = amdgpu_vce_ring_emit_fence, |
859 | .test_ring = amdgpu_vce_ring_test_ring, | 842 | .test_ring = amdgpu_vce_ring_test_ring, |
@@ -862,14 +845,17 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = { | |||
862 | .pad_ib = amdgpu_ring_generic_pad_ib, | 845 | .pad_ib = amdgpu_ring_generic_pad_ib, |
863 | .begin_use = amdgpu_vce_ring_begin_use, | 846 | .begin_use = amdgpu_vce_ring_begin_use, |
864 | .end_use = amdgpu_vce_ring_end_use, | 847 | .end_use = amdgpu_vce_ring_end_use, |
865 | .get_emit_ib_size = vce_v3_0_ring_get_emit_ib_size, | ||
866 | .get_dma_frame_size = vce_v3_0_ring_get_dma_frame_size, | ||
867 | }; | 848 | }; |
868 | 849 | ||
869 | static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { | 850 | static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { |
870 | .get_rptr = vce_v3_0_ring_get_rptr, | 851 | .get_rptr = vce_v3_0_ring_get_rptr, |
871 | .get_wptr = vce_v3_0_ring_get_wptr, | 852 | .get_wptr = vce_v3_0_ring_get_wptr, |
872 | .set_wptr = vce_v3_0_ring_set_wptr, | 853 | .set_wptr = vce_v3_0_ring_set_wptr, |
854 | .emit_frame_size = | ||
855 | 6 + /* vce_v3_0_emit_vm_flush */ | ||
856 | 4 + /* vce_v3_0_emit_pipeline_sync */ | ||
857 | 6 + 6, /* amdgpu_vce_ring_emit_fence x2 vm fence */ | ||
858 | .emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */ | ||
873 | .emit_ib = vce_v3_0_ring_emit_ib, | 859 | .emit_ib = vce_v3_0_ring_emit_ib, |
874 | .emit_vm_flush = vce_v3_0_emit_vm_flush, | 860 | .emit_vm_flush = vce_v3_0_emit_vm_flush, |
875 | .emit_pipeline_sync = vce_v3_0_emit_pipeline_sync, | 861 | .emit_pipeline_sync = vce_v3_0_emit_pipeline_sync, |
@@ -880,8 +866,6 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { | |||
880 | .pad_ib = amdgpu_ring_generic_pad_ib, | 866 | .pad_ib = amdgpu_ring_generic_pad_ib, |
881 | .begin_use = amdgpu_vce_ring_begin_use, | 867 | .begin_use = amdgpu_vce_ring_begin_use, |
882 | .end_use = amdgpu_vce_ring_end_use, | 868 | .end_use = amdgpu_vce_ring_end_use, |
883 | .get_emit_ib_size = vce_v3_0_ring_get_emit_ib_size, | ||
884 | .get_dma_frame_size = vce_v3_0_ring_get_dma_frame_size_vm, | ||
885 | }; | 869 | }; |
886 | 870 | ||
887 | static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev) | 871 | static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev) |