diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vce_v3_0.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 24 |
1 files changed, 10 insertions, 14 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 8db26559fd1b..93ec8815bb13 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | |||
@@ -230,10 +230,6 @@ static int vce_v3_0_start(struct amdgpu_device *adev) | |||
230 | struct amdgpu_ring *ring; | 230 | struct amdgpu_ring *ring; |
231 | int idx, r; | 231 | int idx, r; |
232 | 232 | ||
233 | vce_v3_0_override_vce_clock_gating(adev, true); | ||
234 | if (!(adev->flags & AMD_IS_APU)) | ||
235 | amdgpu_asic_set_vce_clocks(adev, 10000, 10000); | ||
236 | |||
237 | ring = &adev->vce.ring[0]; | 233 | ring = &adev->vce.ring[0]; |
238 | WREG32(mmVCE_RB_RPTR, ring->wptr); | 234 | WREG32(mmVCE_RB_RPTR, ring->wptr); |
239 | WREG32(mmVCE_RB_WPTR, ring->wptr); | 235 | WREG32(mmVCE_RB_WPTR, ring->wptr); |
@@ -436,9 +432,9 @@ static int vce_v3_0_hw_init(void *handle) | |||
436 | int r, i; | 432 | int r, i; |
437 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | 433 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
438 | 434 | ||
439 | r = vce_v3_0_start(adev); | 435 | vce_v3_0_override_vce_clock_gating(adev, true); |
440 | if (r) | 436 | if (!(adev->flags & AMD_IS_APU)) |
441 | return r; | 437 | amdgpu_asic_set_vce_clocks(adev, 10000, 10000); |
442 | 438 | ||
443 | for (i = 0; i < adev->vce.num_rings; i++) | 439 | for (i = 0; i < adev->vce.num_rings; i++) |
444 | adev->vce.ring[i].ready = false; | 440 | adev->vce.ring[i].ready = false; |
@@ -514,6 +510,8 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx) | |||
514 | WREG32(mmVCE_LMI_SWAP_CNTL, 0); | 510 | WREG32(mmVCE_LMI_SWAP_CNTL, 0); |
515 | WREG32(mmVCE_LMI_SWAP_CNTL1, 0); | 511 | WREG32(mmVCE_LMI_SWAP_CNTL1, 0); |
516 | WREG32(mmVCE_LMI_VM_CTRL, 0); | 512 | WREG32(mmVCE_LMI_VM_CTRL, 0); |
513 | WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000); | ||
514 | |||
517 | if (adev->asic_type >= CHIP_STONEY) { | 515 | if (adev->asic_type >= CHIP_STONEY) { |
518 | WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); | 516 | WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); |
519 | WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8)); | 517 | WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8)); |
@@ -766,17 +764,14 @@ static int vce_v3_0_set_powergating_state(void *handle, | |||
766 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | 764 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
767 | int ret = 0; | 765 | int ret = 0; |
768 | 766 | ||
769 | if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE)) | ||
770 | return 0; | ||
771 | |||
772 | if (state == AMD_PG_STATE_GATE) { | 767 | if (state == AMD_PG_STATE_GATE) { |
773 | adev->vce.is_powergated = true; | 768 | ret = vce_v3_0_stop(adev); |
774 | /* XXX do we need a vce_v3_0_stop()? */ | 769 | if (ret) |
770 | goto out; | ||
775 | } else { | 771 | } else { |
776 | ret = vce_v3_0_start(adev); | 772 | ret = vce_v3_0_start(adev); |
777 | if (ret) | 773 | if (ret) |
778 | goto out; | 774 | goto out; |
779 | adev->vce.is_powergated = false; | ||
780 | } | 775 | } |
781 | 776 | ||
782 | out: | 777 | out: |
@@ -790,7 +785,8 @@ static void vce_v3_0_get_clockgating_state(void *handle, u32 *flags) | |||
790 | 785 | ||
791 | mutex_lock(&adev->pm.mutex); | 786 | mutex_lock(&adev->pm.mutex); |
792 | 787 | ||
793 | if (adev->vce.is_powergated) { | 788 | if (RREG32_SMC(ixCURRENT_PG_STATUS) & |
789 | CURRENT_PG_STATUS__VCE_PG_STATUS_MASK) { | ||
794 | DRM_INFO("Cannot get clockgating state when VCE is powergated.\n"); | 790 | DRM_INFO("Cannot get clockgating state when VCE is powergated.\n"); |
795 | goto out; | 791 | goto out; |
796 | } | 792 | } |