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path: root/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c42
1 files changed, 13 insertions, 29 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index f74229496cc7..aeb1b6e2c518 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -725,31 +725,6 @@ static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
725 amdgpu_ring_write(ring, 0xE); 725 amdgpu_ring_write(ring, 0xE);
726} 726}
727 727
728static unsigned uvd_v6_0_ring_get_emit_ib_size(struct amdgpu_ring *ring)
729{
730 return
731 8; /* uvd_v6_0_ring_emit_ib */
732}
733
734static unsigned uvd_v6_0_ring_get_dma_frame_size(struct amdgpu_ring *ring)
735{
736 return
737 2 + /* uvd_v6_0_ring_emit_hdp_flush */
738 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
739 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
740 14; /* uvd_v6_0_ring_emit_fence x1 no user fence */
741}
742
743static unsigned uvd_v6_0_ring_get_dma_frame_size_vm(struct amdgpu_ring *ring)
744{
745 return
746 2 + /* uvd_v6_0_ring_emit_hdp_flush */
747 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
748 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
749 20 + /* uvd_v6_0_ring_emit_vm_flush */
750 14 + 14; /* uvd_v6_0_ring_emit_fence x2 vm fence */
751}
752
753static bool uvd_v6_0_is_idle(void *handle) 728static bool uvd_v6_0_is_idle(void *handle)
754{ 729{
755 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 730 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1052,6 +1027,12 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
1052 .get_wptr = uvd_v6_0_ring_get_wptr, 1027 .get_wptr = uvd_v6_0_ring_get_wptr,
1053 .set_wptr = uvd_v6_0_ring_set_wptr, 1028 .set_wptr = uvd_v6_0_ring_set_wptr,
1054 .parse_cs = amdgpu_uvd_ring_parse_cs, 1029 .parse_cs = amdgpu_uvd_ring_parse_cs,
1030 .emit_frame_size =
1031 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1032 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1033 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1034 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
1035 .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1055 .emit_ib = uvd_v6_0_ring_emit_ib, 1036 .emit_ib = uvd_v6_0_ring_emit_ib,
1056 .emit_fence = uvd_v6_0_ring_emit_fence, 1037 .emit_fence = uvd_v6_0_ring_emit_fence,
1057 .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush, 1038 .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
@@ -1062,14 +1043,19 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
1062 .pad_ib = amdgpu_ring_generic_pad_ib, 1043 .pad_ib = amdgpu_ring_generic_pad_ib,
1063 .begin_use = amdgpu_uvd_ring_begin_use, 1044 .begin_use = amdgpu_uvd_ring_begin_use,
1064 .end_use = amdgpu_uvd_ring_end_use, 1045 .end_use = amdgpu_uvd_ring_end_use,
1065 .get_emit_ib_size = uvd_v6_0_ring_get_emit_ib_size,
1066 .get_dma_frame_size = uvd_v6_0_ring_get_dma_frame_size,
1067}; 1046};
1068 1047
1069static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { 1048static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
1070 .get_rptr = uvd_v6_0_ring_get_rptr, 1049 .get_rptr = uvd_v6_0_ring_get_rptr,
1071 .get_wptr = uvd_v6_0_ring_get_wptr, 1050 .get_wptr = uvd_v6_0_ring_get_wptr,
1072 .set_wptr = uvd_v6_0_ring_set_wptr, 1051 .set_wptr = uvd_v6_0_ring_set_wptr,
1052 .emit_frame_size =
1053 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1054 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1055 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1056 20 + /* uvd_v6_0_ring_emit_vm_flush */
1057 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
1058 .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1073 .emit_ib = uvd_v6_0_ring_emit_ib, 1059 .emit_ib = uvd_v6_0_ring_emit_ib,
1074 .emit_fence = uvd_v6_0_ring_emit_fence, 1060 .emit_fence = uvd_v6_0_ring_emit_fence,
1075 .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush, 1061 .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
@@ -1082,8 +1068,6 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
1082 .pad_ib = amdgpu_ring_generic_pad_ib, 1068 .pad_ib = amdgpu_ring_generic_pad_ib,
1083 .begin_use = amdgpu_uvd_ring_begin_use, 1069 .begin_use = amdgpu_uvd_ring_begin_use,
1084 .end_use = amdgpu_uvd_ring_end_use, 1070 .end_use = amdgpu_uvd_ring_end_use,
1085 .get_emit_ib_size = uvd_v6_0_ring_get_emit_ib_size,
1086 .get_dma_frame_size = uvd_v6_0_ring_get_dma_frame_size_vm,
1087}; 1071};
1088 1072
1089static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1073static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)