diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 21 |
1 files changed, 5 insertions, 16 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index f6c941550b8f..708de997e3b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | |||
@@ -526,20 +526,6 @@ static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, | |||
526 | amdgpu_ring_write(ring, ib->length_dw); | 526 | amdgpu_ring_write(ring, ib->length_dw); |
527 | } | 527 | } |
528 | 528 | ||
529 | static unsigned uvd_v4_2_ring_get_emit_ib_size(struct amdgpu_ring *ring) | ||
530 | { | ||
531 | return | ||
532 | 4; /* uvd_v4_2_ring_emit_ib */ | ||
533 | } | ||
534 | |||
535 | static unsigned uvd_v4_2_ring_get_dma_frame_size(struct amdgpu_ring *ring) | ||
536 | { | ||
537 | return | ||
538 | 2 + /* uvd_v4_2_ring_emit_hdp_flush */ | ||
539 | 2 + /* uvd_v4_2_ring_emit_hdp_invalidate */ | ||
540 | 14; /* uvd_v4_2_ring_emit_fence x1 no user fence */ | ||
541 | } | ||
542 | |||
543 | /** | 529 | /** |
544 | * uvd_v4_2_mc_resume - memory controller programming | 530 | * uvd_v4_2_mc_resume - memory controller programming |
545 | * | 531 | * |
@@ -760,6 +746,11 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { | |||
760 | .get_wptr = uvd_v4_2_ring_get_wptr, | 746 | .get_wptr = uvd_v4_2_ring_get_wptr, |
761 | .set_wptr = uvd_v4_2_ring_set_wptr, | 747 | .set_wptr = uvd_v4_2_ring_set_wptr, |
762 | .parse_cs = amdgpu_uvd_ring_parse_cs, | 748 | .parse_cs = amdgpu_uvd_ring_parse_cs, |
749 | .emit_frame_size = | ||
750 | 2 + /* uvd_v4_2_ring_emit_hdp_flush */ | ||
751 | 2 + /* uvd_v4_2_ring_emit_hdp_invalidate */ | ||
752 | 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */ | ||
753 | .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */ | ||
763 | .emit_ib = uvd_v4_2_ring_emit_ib, | 754 | .emit_ib = uvd_v4_2_ring_emit_ib, |
764 | .emit_fence = uvd_v4_2_ring_emit_fence, | 755 | .emit_fence = uvd_v4_2_ring_emit_fence, |
765 | .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush, | 756 | .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush, |
@@ -770,8 +761,6 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { | |||
770 | .pad_ib = amdgpu_ring_generic_pad_ib, | 761 | .pad_ib = amdgpu_ring_generic_pad_ib, |
771 | .begin_use = amdgpu_uvd_ring_begin_use, | 762 | .begin_use = amdgpu_uvd_ring_begin_use, |
772 | .end_use = amdgpu_uvd_ring_end_use, | 763 | .end_use = amdgpu_uvd_ring_end_use, |
773 | .get_emit_ib_size = uvd_v4_2_ring_get_emit_ib_size, | ||
774 | .get_dma_frame_size = uvd_v4_2_ring_get_dma_frame_size, | ||
775 | }; | 764 | }; |
776 | 765 | ||
777 | static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) | 766 | static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) |