1 files changed, 64 insertions, 1 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 3de7bca5854b..917213396787 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -3171,6 +3171,7 @@ static void ni_update_current_ps(struct amdgpu_device *adev,
         eg_pi->current_rps = *rps;
         ni_pi->current_ps = *new_ps;
         eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
+        adev->pm.dpm.current_ps = &eg_pi->current_rps;
 }
 
 static void ni_update_requested_ps(struct amdgpu_device *adev,
@@ -3183,6 +3184,7 @@ static void ni_update_requested_ps(struct amdgpu_device *adev,
         eg_pi->requested_rps = *rps;
         ni_pi->requested_ps = *new_ps;
         eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
+        adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
 }
 
 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
@@ -7320,7 +7322,7 @@ static int si_parse_power_table(struct amdgpu_device *adev)
         adev->pm.dpm.num_ps = state_array->ucNumEntries;
 
         /* fill in the vce power states */
-        for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
+        for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
                 u32 sclk, mclk;
                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
                 clock_info = (union pplib_clock_info *)
@@ -7957,6 +7959,57 @@ static int si_dpm_early_init(void *handle)
         return 0;
 }
 
+static inline bool si_are_power_levels_equal(const struct rv7xx_pl  *si_cpl1,
+                                                const struct rv7xx_pl *si_cpl2)
+{
+        return ((si_cpl1->mclk == si_cpl2->mclk) &&
+                  (si_cpl1->sclk == si_cpl2->sclk) &&
+                  (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
+                  (si_cpl1->vddc == si_cpl2->vddc) &&
+                  (si_cpl1->vddci == si_cpl2->vddci));
+}
+
+static int si_check_state_equal(struct amdgpu_device *adev,
+                                struct amdgpu_ps *cps,
+                                struct amdgpu_ps *rps,
+                                bool *equal)
+{
+        struct si_ps *si_cps;
+        struct si_ps *si_rps;
+        int i;
+
+        if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
+                return -EINVAL;
+
+        si_cps = si_get_ps(cps);
+        si_rps = si_get_ps(rps);
+
+        if (si_cps == NULL) {
+                printk("si_cps is NULL\n");
+                *equal = false;
+                return 0;
+        }
+
+        if (si_cps->performance_level_count != si_rps->performance_level_count) {
+                *equal = false;
+                return 0;
+        }
+
+        for (i = 0; i < si_cps->performance_level_count; i++) {
+                if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
+                                        &(si_rps->performance_levels[i]))) {
+                        *equal = false;
+                        return 0;
+                }
+        }
+
+        /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
+        *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
+        *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
+
+        return 0;
+}
+
 
 const struct amd_ip_funcs si_dpm_ip_funcs = {
         .name = "si_dpm",
@@ -7991,6 +8044,8 @@ static const struct amdgpu_dpm_funcs si_dpm_funcs = {
         .get_fan_control_mode = &si_dpm_get_fan_control_mode,
         .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
         .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
+        .check_state_equal = &si_check_state_equal,
+        .get_vce_clock_state = amdgpu_get_vce_clock_state,
 };
 
 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
@@ -8010,3 +8065,11 @@ static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
         adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
 }
 
+const struct amdgpu_ip_block_version si_dpm_ip_block =
+{
+        .type = AMD_IP_BLOCK_TYPE_SMC,
+        .major = 6,
+        .minor = 0,
+        .rev = 0,
+        .funcs = &si_dpm_ip_funcs,
+};