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path: root/drivers/gpu/drm/amd/amdgpu/si.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/si.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si.c162
1 files changed, 43 insertions, 119 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index dc9511c5ecb8..3ed8ad8725b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -39,6 +39,7 @@
39#include "si_dma.h" 39#include "si_dma.h"
40#include "dce_v6_0.h" 40#include "dce_v6_0.h"
41#include "si.h" 41#include "si.h"
42#include "dce_virtual.h"
42 43
43static const u32 tahiti_golden_registers[] = 44static const u32 tahiti_golden_registers[] =
44{ 45{
@@ -905,7 +906,7 @@ static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
905 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 906 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
906} 907}
907 908
908u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) 909static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
909{ 910{
910 unsigned long flags; 911 unsigned long flags;
911 u32 r; 912 u32 r;
@@ -918,7 +919,7 @@ u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
918 return r; 919 return r;
919} 920}
920 921
921void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 922static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
922{ 923{
923 unsigned long flags; 924 unsigned long flags;
924 925
@@ -1811,7 +1812,7 @@ static int si_common_set_powergating_state(void *handle,
1811 return 0; 1812 return 0;
1812} 1813}
1813 1814
1814const struct amd_ip_funcs si_common_ip_funcs = { 1815static const struct amd_ip_funcs si_common_ip_funcs = {
1815 .name = "si_common", 1816 .name = "si_common",
1816 .early_init = si_common_early_init, 1817 .early_init = si_common_early_init,
1817 .late_init = NULL, 1818 .late_init = NULL,
@@ -1828,119 +1829,13 @@ const struct amd_ip_funcs si_common_ip_funcs = {
1828 .set_powergating_state = si_common_set_powergating_state, 1829 .set_powergating_state = si_common_set_powergating_state,
1829}; 1830};
1830 1831
1831static const struct amdgpu_ip_block_version verde_ip_blocks[] = 1832static const struct amdgpu_ip_block_version si_common_ip_block =
1832{ 1833{
1833 { 1834 .type = AMD_IP_BLOCK_TYPE_COMMON,
1834 .type = AMD_IP_BLOCK_TYPE_COMMON, 1835 .major = 1,
1835 .major = 1, 1836 .minor = 0,
1836 .minor = 0, 1837 .rev = 0,
1837 .rev = 0, 1838 .funcs = &si_common_ip_funcs,
1838 .funcs = &si_common_ip_funcs,
1839 },
1840 {
1841 .type = AMD_IP_BLOCK_TYPE_GMC,
1842 .major = 6,
1843 .minor = 0,
1844 .rev = 0,
1845 .funcs = &gmc_v6_0_ip_funcs,
1846 },
1847 {
1848 .type = AMD_IP_BLOCK_TYPE_IH,
1849 .major = 1,
1850 .minor = 0,
1851 .rev = 0,
1852 .funcs = &si_ih_ip_funcs,
1853 },
1854 {
1855 .type = AMD_IP_BLOCK_TYPE_SMC,
1856 .major = 6,
1857 .minor = 0,
1858 .rev = 0,
1859 .funcs = &amdgpu_pp_ip_funcs,
1860 },
1861 {
1862 .type = AMD_IP_BLOCK_TYPE_DCE,
1863 .major = 6,
1864 .minor = 0,
1865 .rev = 0,
1866 .funcs = &dce_v6_0_ip_funcs,
1867 },
1868 {
1869 .type = AMD_IP_BLOCK_TYPE_GFX,
1870 .major = 6,
1871 .minor = 0,
1872 .rev = 0,
1873 .funcs = &gfx_v6_0_ip_funcs,
1874 },
1875 {
1876 .type = AMD_IP_BLOCK_TYPE_SDMA,
1877 .major = 1,
1878 .minor = 0,
1879 .rev = 0,
1880 .funcs = &si_dma_ip_funcs,
1881 },
1882/* {
1883 .type = AMD_IP_BLOCK_TYPE_UVD,
1884 .major = 3,
1885 .minor = 1,
1886 .rev = 0,
1887 .funcs = &si_null_ip_funcs,
1888 },
1889 {
1890 .type = AMD_IP_BLOCK_TYPE_VCE,
1891 .major = 1,
1892 .minor = 0,
1893 .rev = 0,
1894 .funcs = &si_null_ip_funcs,
1895 },
1896 */
1897};
1898
1899
1900static const struct amdgpu_ip_block_version hainan_ip_blocks[] =
1901{
1902 {
1903 .type = AMD_IP_BLOCK_TYPE_COMMON,
1904 .major = 1,
1905 .minor = 0,
1906 .rev = 0,
1907 .funcs = &si_common_ip_funcs,
1908 },
1909 {
1910 .type = AMD_IP_BLOCK_TYPE_GMC,
1911 .major = 6,
1912 .minor = 0,
1913 .rev = 0,
1914 .funcs = &gmc_v6_0_ip_funcs,
1915 },
1916 {
1917 .type = AMD_IP_BLOCK_TYPE_IH,
1918 .major = 1,
1919 .minor = 0,
1920 .rev = 0,
1921 .funcs = &si_ih_ip_funcs,
1922 },
1923 {
1924 .type = AMD_IP_BLOCK_TYPE_SMC,
1925 .major = 6,
1926 .minor = 0,
1927 .rev = 0,
1928 .funcs = &amdgpu_pp_ip_funcs,
1929 },
1930 {
1931 .type = AMD_IP_BLOCK_TYPE_GFX,
1932 .major = 6,
1933 .minor = 0,
1934 .rev = 0,
1935 .funcs = &gfx_v6_0_ip_funcs,
1936 },
1937 {
1938 .type = AMD_IP_BLOCK_TYPE_SDMA,
1939 .major = 1,
1940 .minor = 0,
1941 .rev = 0,
1942 .funcs = &si_dma_ip_funcs,
1943 },
1944}; 1839};
1945 1840
1946int si_set_ip_blocks(struct amdgpu_device *adev) 1841int si_set_ip_blocks(struct amdgpu_device *adev)
@@ -1949,13 +1844,42 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
1949 case CHIP_VERDE: 1844 case CHIP_VERDE:
1950 case CHIP_TAHITI: 1845 case CHIP_TAHITI:
1951 case CHIP_PITCAIRN: 1846 case CHIP_PITCAIRN:
1847 amdgpu_ip_block_add(adev, &si_common_ip_block);
1848 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1849 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1850 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1851 if (adev->enable_virtual_display)
1852 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1853 else
1854 amdgpu_ip_block_add(adev, &dce_v6_0_ip_block);
1855 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1856 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1857 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1858 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
1859 break;
1952 case CHIP_OLAND: 1860 case CHIP_OLAND:
1953 adev->ip_blocks = verde_ip_blocks; 1861 amdgpu_ip_block_add(adev, &si_common_ip_block);
1954 adev->num_ip_blocks = ARRAY_SIZE(verde_ip_blocks); 1862 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1863 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1864 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1865 if (adev->enable_virtual_display)
1866 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1867 else
1868 amdgpu_ip_block_add(adev, &dce_v6_4_ip_block);
1869 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1870 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1871 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1872 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
1955 break; 1873 break;
1956 case CHIP_HAINAN: 1874 case CHIP_HAINAN:
1957 adev->ip_blocks = hainan_ip_blocks; 1875 amdgpu_ip_block_add(adev, &si_common_ip_block);
1958 adev->num_ip_blocks = ARRAY_SIZE(hainan_ip_blocks); 1876 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1877 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1878 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1879 if (adev->enable_virtual_display)
1880 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1881 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1882 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1959 break; 1883 break;
1960 default: 1884 default:
1961 BUG(); 1885 BUG();
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-02 02:47:36 -0400