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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c1514
1 files changed, 1514 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
new file mode 100644
index 000000000000..dd547c7f6cbc
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -0,0 +1,1514 @@
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_ucode.h"
28#include "amdgpu_trace.h"
29#include "vi.h"
30#include "vid.h"
31
32#include "oss/oss_3_0_d.h"
33#include "oss/oss_3_0_sh_mask.h"
34
35#include "gmc/gmc_8_1_d.h"
36#include "gmc/gmc_8_1_sh_mask.h"
37
38#include "gca/gfx_8_0_d.h"
39#include "gca/gfx_8_0_sh_mask.h"
40
41#include "bif/bif_5_0_d.h"
42#include "bif/bif_5_0_sh_mask.h"
43
44#include "tonga_sdma_pkt_open.h"
45
46static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
47static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
48static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
49static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
50
51MODULE_FIRMWARE("radeon/tonga_sdma.bin");
52MODULE_FIRMWARE("radeon/tonga_sdma1.bin");
53MODULE_FIRMWARE("radeon/carrizo_sdma.bin");
54MODULE_FIRMWARE("radeon/carrizo_sdma1.bin");
55
56static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
57{
58 SDMA0_REGISTER_OFFSET,
59 SDMA1_REGISTER_OFFSET
60};
61
62static const u32 golden_settings_tonga_a11[] =
63{
64 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
65 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
66 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
67 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
68 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
69 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
70 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
71 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
72 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
73 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
74};
75
76static const u32 tonga_mgcg_cgcg_init[] =
77{
78 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
79 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
80};
81
82static const u32 cz_golden_settings_a11[] =
83{
84 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
85 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
86 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
87 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
88 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
89 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
90 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
91 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
92 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
93 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
94 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
95 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
96};
97
98static const u32 cz_mgcg_cgcg_init[] =
99{
100 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
101 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
102};
103
104/*
105 * sDMA - System DMA
106 * Starting with CIK, the GPU has new asynchronous
107 * DMA engines. These engines are used for compute
108 * and gfx. There are two DMA engines (SDMA0, SDMA1)
109 * and each one supports 1 ring buffer used for gfx
110 * and 2 queues used for compute.
111 *
112 * The programming model is very similar to the CP
113 * (ring buffer, IBs, etc.), but sDMA has it's own
114 * packet format that is different from the PM4 format
115 * used by the CP. sDMA supports copying data, writing
116 * embedded data, solid fills, and a number of other
117 * things. It also has support for tiling/detiling of
118 * buffers.
119 */
120
121static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
122{
123 switch (adev->asic_type) {
124 case CHIP_TONGA:
125 amdgpu_program_register_sequence(adev,
126 tonga_mgcg_cgcg_init,
127 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
128 amdgpu_program_register_sequence(adev,
129 golden_settings_tonga_a11,
130 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
131 break;
132 case CHIP_CARRIZO:
133 amdgpu_program_register_sequence(adev,
134 cz_mgcg_cgcg_init,
135 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
136 amdgpu_program_register_sequence(adev,
137 cz_golden_settings_a11,
138 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
139 break;
140 default:
141 break;
142 }
143}
144
145/**
146 * sdma_v3_0_init_microcode - load ucode images from disk
147 *
148 * @adev: amdgpu_device pointer
149 *
150 * Use the firmware interface to load the ucode images into
151 * the driver (not loaded into hw).
152 * Returns 0 on success, error on failure.
153 */
154static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
155{
156 const char *chip_name;
157 char fw_name[30];
158 int err, i;
159 struct amdgpu_firmware_info *info = NULL;
160 const struct common_firmware_header *header = NULL;
161
162 DRM_DEBUG("\n");
163
164 switch (adev->asic_type) {
165 case CHIP_TONGA:
166 chip_name = "tonga";
167 break;
168 case CHIP_CARRIZO:
169 chip_name = "carrizo";
170 break;
171 default: BUG();
172 }
173
174 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
175 if (i == 0)
176 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
177 else
178 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
179 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
180 if (err)
181 goto out;
182 err = amdgpu_ucode_validate(adev->sdma[i].fw);
183 if (err)
184 goto out;
185
186 if (adev->firmware.smu_load) {
187 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
188 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
189 info->fw = adev->sdma[i].fw;
190 header = (const struct common_firmware_header *)info->fw->data;
191 adev->firmware.fw_size +=
192 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
193 }
194 }
195out:
196 if (err) {
197 printk(KERN_ERR
198 "sdma_v3_0: Failed to load firmware \"%s\"\n",
199 fw_name);
200 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
201 release_firmware(adev->sdma[i].fw);
202 adev->sdma[i].fw = NULL;
203 }
204 }
205 return err;
206}
207
208/**
209 * sdma_v3_0_ring_get_rptr - get the current read pointer
210 *
211 * @ring: amdgpu ring pointer
212 *
213 * Get the current rptr from the hardware (VI+).
214 */
215static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
216{
217 u32 rptr;
218
219 /* XXX check if swapping is necessary on BE */
220 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
221
222 return rptr;
223}
224
225/**
226 * sdma_v3_0_ring_get_wptr - get the current write pointer
227 *
228 * @ring: amdgpu ring pointer
229 *
230 * Get the current wptr from the hardware (VI+).
231 */
232static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
233{
234 struct amdgpu_device *adev = ring->adev;
235 u32 wptr;
236
237 if (ring->use_doorbell) {
238 /* XXX check if swapping is necessary on BE */
239 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
240 } else {
241 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
242
243 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
244 }
245
246 return wptr;
247}
248
249/**
250 * sdma_v3_0_ring_set_wptr - commit the write pointer
251 *
252 * @ring: amdgpu ring pointer
253 *
254 * Write the wptr back to the hardware (VI+).
255 */
256static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
257{
258 struct amdgpu_device *adev = ring->adev;
259
260 if (ring->use_doorbell) {
261 /* XXX check if swapping is necessary on BE */
262 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
263 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
264 } else {
265 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
266
267 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
268 }
269}
270
271static void sdma_v3_0_hdp_flush_ring_emit(struct amdgpu_ring *);
272
273/**
274 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
275 *
276 * @ring: amdgpu ring pointer
277 * @ib: IB object to schedule
278 *
279 * Schedule an IB in the DMA ring (VI).
280 */
281static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
282 struct amdgpu_ib *ib)
283{
284 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
285 u32 next_rptr = ring->wptr + 5;
286
287 if (ib->flush_hdp_writefifo)
288 next_rptr += 6;
289
290 while ((next_rptr & 7) != 2)
291 next_rptr++;
292 next_rptr += 6;
293
294 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
295 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
296 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
297 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
298 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
299 amdgpu_ring_write(ring, next_rptr);
300
301 /* flush HDP */
302 if (ib->flush_hdp_writefifo) {
303 sdma_v3_0_hdp_flush_ring_emit(ring);
304 }
305
306 /* IB packet must end on a 8 DW boundary */
307 while ((ring->wptr & 7) != 2)
308 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP));
309
310 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
311 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
312 /* base must be 32 byte aligned */
313 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
314 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
315 amdgpu_ring_write(ring, ib->length_dw);
316 amdgpu_ring_write(ring, 0);
317 amdgpu_ring_write(ring, 0);
318
319}
320
321/**
322 * sdma_v3_0_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
323 *
324 * @ring: amdgpu ring pointer
325 *
326 * Emit an hdp flush packet on the requested DMA ring.
327 */
328static void sdma_v3_0_hdp_flush_ring_emit(struct amdgpu_ring *ring)
329{
330 u32 ref_and_mask = 0;
331
332 if (ring == &ring->adev->sdma[0].ring)
333 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
334 else
335 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
336
337 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
338 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
339 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
340 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
341 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
342 amdgpu_ring_write(ring, ref_and_mask); /* reference */
343 amdgpu_ring_write(ring, ref_and_mask); /* mask */
344 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
345 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
346}
347
348/**
349 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
350 *
351 * @ring: amdgpu ring pointer
352 * @fence: amdgpu fence object
353 *
354 * Add a DMA fence packet to the ring to write
355 * the fence seq number and DMA trap packet to generate
356 * an interrupt if needed (VI).
357 */
358static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
359 bool write64bits)
360{
361 /* write the fence */
362 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
363 amdgpu_ring_write(ring, lower_32_bits(addr));
364 amdgpu_ring_write(ring, upper_32_bits(addr));
365 amdgpu_ring_write(ring, lower_32_bits(seq));
366
367 /* optionally write high bits as well */
368 if (write64bits) {
369 addr += 4;
370 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
371 amdgpu_ring_write(ring, lower_32_bits(addr));
372 amdgpu_ring_write(ring, upper_32_bits(addr));
373 amdgpu_ring_write(ring, upper_32_bits(seq));
374 }
375
376 /* generate an interrupt */
377 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
378 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
379}
380
381
382/**
383 * sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring
384 *
385 * @ring: amdgpu_ring structure holding ring information
386 * @semaphore: amdgpu semaphore object
387 * @emit_wait: wait or signal semaphore
388 *
389 * Add a DMA semaphore packet to the ring wait on or signal
390 * other rings (VI).
391 */
392static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring,
393 struct amdgpu_semaphore *semaphore,
394 bool emit_wait)
395{
396 u64 addr = semaphore->gpu_addr;
397 u32 sig = emit_wait ? 0 : 1;
398
399 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
400 SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
401 amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
402 amdgpu_ring_write(ring, upper_32_bits(addr));
403
404 return true;
405}
406
407/**
408 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
409 *
410 * @adev: amdgpu_device pointer
411 *
412 * Stop the gfx async dma ring buffers (VI).
413 */
414static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
415{
416 struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
417 struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
418 u32 rb_cntl, ib_cntl;
419 int i;
420
421 if ((adev->mman.buffer_funcs_ring == sdma0) ||
422 (adev->mman.buffer_funcs_ring == sdma1))
423 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
424
425 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
426 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
427 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
428 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
429 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
430 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
431 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
432 }
433 sdma0->ready = false;
434 sdma1->ready = false;
435}
436
437/**
438 * sdma_v3_0_rlc_stop - stop the compute async dma engines
439 *
440 * @adev: amdgpu_device pointer
441 *
442 * Stop the compute async dma queues (VI).
443 */
444static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
445{
446 /* XXX todo */
447}
448
449/**
450 * sdma_v3_0_enable - stop the async dma engines
451 *
452 * @adev: amdgpu_device pointer
453 * @enable: enable/disable the DMA MEs.
454 *
455 * Halt or unhalt the async dma engines (VI).
456 */
457static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
458{
459 u32 f32_cntl;
460 int i;
461
462 if (enable == false) {
463 sdma_v3_0_gfx_stop(adev);
464 sdma_v3_0_rlc_stop(adev);
465 }
466
467 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
468 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
469 if (enable)
470 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
471 else
472 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
473 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
474 }
475}
476
477/**
478 * sdma_v3_0_gfx_resume - setup and start the async dma engines
479 *
480 * @adev: amdgpu_device pointer
481 *
482 * Set up the gfx DMA ring buffers and enable them (VI).
483 * Returns 0 for success, error for failure.
484 */
485static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
486{
487 struct amdgpu_ring *ring;
488 u32 rb_cntl, ib_cntl;
489 u32 rb_bufsz;
490 u32 wb_offset;
491 u32 doorbell;
492 int i, j, r;
493
494 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
495 ring = &adev->sdma[i].ring;
496 wb_offset = (ring->rptr_offs * 4);
497
498 mutex_lock(&adev->srbm_mutex);
499 for (j = 0; j < 16; j++) {
500 vi_srbm_select(adev, 0, 0, 0, j);
501 /* SDMA GFX */
502 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
503 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
504 }
505 vi_srbm_select(adev, 0, 0, 0, 0);
506 mutex_unlock(&adev->srbm_mutex);
507
508 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
509
510 /* Set ring buffer size in dwords */
511 rb_bufsz = order_base_2(ring->ring_size / 4);
512 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
513 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
514#ifdef __BIG_ENDIAN
515 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
516 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
517 RPTR_WRITEBACK_SWAP_ENABLE, 1);
518#endif
519 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
520
521 /* Initialize the ring buffer's read and write pointers */
522 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
523 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
524
525 /* set the wb address whether it's enabled or not */
526 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
527 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
528 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
529 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
530
531 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
532
533 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
534 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
535
536 ring->wptr = 0;
537 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
538
539 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
540
541 if (ring->use_doorbell) {
542 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
543 OFFSET, ring->doorbell_index);
544 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
545 } else {
546 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
547 }
548 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
549
550 /* enable DMA RB */
551 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
552 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
553
554 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
555 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
556#ifdef __BIG_ENDIAN
557 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
558#endif
559 /* enable DMA IBs */
560 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
561
562 ring->ready = true;
563
564 r = amdgpu_ring_test_ring(ring);
565 if (r) {
566 ring->ready = false;
567 return r;
568 }
569
570 if (adev->mman.buffer_funcs_ring == ring)
571 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
572 }
573
574 return 0;
575}
576
577/**
578 * sdma_v3_0_rlc_resume - setup and start the async dma engines
579 *
580 * @adev: amdgpu_device pointer
581 *
582 * Set up the compute DMA queues and enable them (VI).
583 * Returns 0 for success, error for failure.
584 */
585static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
586{
587 /* XXX todo */
588 return 0;
589}
590
591/**
592 * sdma_v3_0_load_microcode - load the sDMA ME ucode
593 *
594 * @adev: amdgpu_device pointer
595 *
596 * Loads the sDMA0/1 ucode.
597 * Returns 0 for success, -EINVAL if the ucode is not available.
598 */
599static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
600{
601 const struct sdma_firmware_header_v1_0 *hdr;
602 const __le32 *fw_data;
603 u32 fw_size;
604 int i, j;
605
606 if (!adev->sdma[0].fw || !adev->sdma[1].fw)
607 return -EINVAL;
608
609 /* halt the MEs */
610 sdma_v3_0_enable(adev, false);
611
612 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
613 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
614 amdgpu_ucode_print_sdma_hdr(&hdr->header);
615 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
616 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
617
618 fw_data = (const __le32 *)
619 (adev->sdma[i].fw->data +
620 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
621 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
622 for (j = 0; j < fw_size; j++)
623 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
624 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
625 }
626
627 return 0;
628}
629
630/**
631 * sdma_v3_0_start - setup and start the async dma engines
632 *
633 * @adev: amdgpu_device pointer
634 *
635 * Set up the DMA engines and enable them (VI).
636 * Returns 0 for success, error for failure.
637 */
638static int sdma_v3_0_start(struct amdgpu_device *adev)
639{
640 int r;
641
642 if (!adev->firmware.smu_load) {
643 r = sdma_v3_0_load_microcode(adev);
644 if (r)
645 return r;
646 } else {
647 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
648 AMDGPU_UCODE_ID_SDMA0);
649 if (r)
650 return -EINVAL;
651 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
652 AMDGPU_UCODE_ID_SDMA1);
653 if (r)
654 return -EINVAL;
655 }
656
657 /* unhalt the MEs */
658 sdma_v3_0_enable(adev, true);
659
660 /* start the gfx rings and rlc compute queues */
661 r = sdma_v3_0_gfx_resume(adev);
662 if (r)
663 return r;
664 r = sdma_v3_0_rlc_resume(adev);
665 if (r)
666 return r;
667
668 return 0;
669}
670
671/**
672 * sdma_v3_0_ring_test_ring - simple async dma engine test
673 *
674 * @ring: amdgpu_ring structure holding ring information
675 *
676 * Test the DMA engine by writing using it to write an
677 * value to memory. (VI).
678 * Returns 0 for success, error for failure.
679 */
680static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
681{
682 struct amdgpu_device *adev = ring->adev;
683 unsigned i;
684 unsigned index;
685 int r;
686 u32 tmp;
687 u64 gpu_addr;
688
689 r = amdgpu_wb_get(adev, &index);
690 if (r) {
691 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
692 return r;
693 }
694
695 gpu_addr = adev->wb.gpu_addr + (index * 4);
696 tmp = 0xCAFEDEAD;
697 adev->wb.wb[index] = cpu_to_le32(tmp);
698
699 r = amdgpu_ring_lock(ring, 5);
700 if (r) {
701 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
702 amdgpu_wb_free(adev, index);
703 return r;
704 }
705
706 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
707 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
708 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
709 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
710 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
711 amdgpu_ring_write(ring, 0xDEADBEEF);
712 amdgpu_ring_unlock_commit(ring);
713
714 for (i = 0; i < adev->usec_timeout; i++) {
715 tmp = le32_to_cpu(adev->wb.wb[index]);
716 if (tmp == 0xDEADBEEF)
717 break;
718 DRM_UDELAY(1);
719 }
720
721 if (i < adev->usec_timeout) {
722 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
723 } else {
724 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
725 ring->idx, tmp);
726 r = -EINVAL;
727 }
728 amdgpu_wb_free(adev, index);
729
730 return r;
731}
732
733/**
734 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
735 *
736 * @ring: amdgpu_ring structure holding ring information
737 *
738 * Test a simple IB in the DMA ring (VI).
739 * Returns 0 on success, error on failure.
740 */
741static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
742{
743 struct amdgpu_device *adev = ring->adev;
744 struct amdgpu_ib ib;
745 unsigned i;
746 unsigned index;
747 int r;
748 u32 tmp = 0;
749 u64 gpu_addr;
750
751 r = amdgpu_wb_get(adev, &index);
752 if (r) {
753 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
754 return r;
755 }
756
757 gpu_addr = adev->wb.gpu_addr + (index * 4);
758 tmp = 0xCAFEDEAD;
759 adev->wb.wb[index] = cpu_to_le32(tmp);
760
761 r = amdgpu_ib_get(ring, NULL, 256, &ib);
762 if (r) {
763 amdgpu_wb_free(adev, index);
764 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
765 return r;
766 }
767
768 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
769 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
770 ib.ptr[1] = lower_32_bits(gpu_addr);
771 ib.ptr[2] = upper_32_bits(gpu_addr);
772 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
773 ib.ptr[4] = 0xDEADBEEF;
774 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
775 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
776 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
777 ib.length_dw = 8;
778
779 r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
780 if (r) {
781 amdgpu_ib_free(adev, &ib);
782 amdgpu_wb_free(adev, index);
783 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
784 return r;
785 }
786 r = amdgpu_fence_wait(ib.fence, false);
787 if (r) {
788 amdgpu_ib_free(adev, &ib);
789 amdgpu_wb_free(adev, index);
790 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
791 return r;
792 }
793 for (i = 0; i < adev->usec_timeout; i++) {
794 tmp = le32_to_cpu(adev->wb.wb[index]);
795 if (tmp == 0xDEADBEEF)
796 break;
797 DRM_UDELAY(1);
798 }
799 if (i < adev->usec_timeout) {
800 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
801 ib.fence->ring->idx, i);
802 } else {
803 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
804 r = -EINVAL;
805 }
806 amdgpu_ib_free(adev, &ib);
807 amdgpu_wb_free(adev, index);
808 return r;
809}
810
811/**
812 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
813 *
814 * @ib: indirect buffer to fill with commands
815 * @pe: addr of the page entry
816 * @src: src addr to copy from
817 * @count: number of page entries to update
818 *
819 * Update PTEs by copying them from the GART using sDMA (CIK).
820 */
821static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
822 uint64_t pe, uint64_t src,
823 unsigned count)
824{
825 while (count) {
826 unsigned bytes = count * 8;
827 if (bytes > 0x1FFFF8)
828 bytes = 0x1FFFF8;
829
830 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
831 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
832 ib->ptr[ib->length_dw++] = bytes;
833 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
834 ib->ptr[ib->length_dw++] = lower_32_bits(src);
835 ib->ptr[ib->length_dw++] = upper_32_bits(src);
836 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
837 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
838
839 pe += bytes;
840 src += bytes;
841 count -= bytes / 8;
842 }
843}
844
845/**
846 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
847 *
848 * @ib: indirect buffer to fill with commands
849 * @pe: addr of the page entry
850 * @addr: dst addr to write into pe
851 * @count: number of page entries to update
852 * @incr: increase next addr by incr bytes
853 * @flags: access flags
854 *
855 * Update PTEs by writing them manually using sDMA (CIK).
856 */
857static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
858 uint64_t pe,
859 uint64_t addr, unsigned count,
860 uint32_t incr, uint32_t flags)
861{
862 uint64_t value;
863 unsigned ndw;
864
865 while (count) {
866 ndw = count * 2;
867 if (ndw > 0xFFFFE)
868 ndw = 0xFFFFE;
869
870 /* for non-physically contiguous pages (system) */
871 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
872 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
873 ib->ptr[ib->length_dw++] = pe;
874 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
875 ib->ptr[ib->length_dw++] = ndw;
876 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
877 if (flags & AMDGPU_PTE_SYSTEM) {
878 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
879 value &= 0xFFFFFFFFFFFFF000ULL;
880 } else if (flags & AMDGPU_PTE_VALID) {
881 value = addr;
882 } else {
883 value = 0;
884 }
885 addr += incr;
886 value |= flags;
887 ib->ptr[ib->length_dw++] = value;
888 ib->ptr[ib->length_dw++] = upper_32_bits(value);
889 }
890 }
891}
892
893/**
894 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
895 *
896 * @ib: indirect buffer to fill with commands
897 * @pe: addr of the page entry
898 * @addr: dst addr to write into pe
899 * @count: number of page entries to update
900 * @incr: increase next addr by incr bytes
901 * @flags: access flags
902 *
903 * Update the page tables using sDMA (CIK).
904 */
905static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
906 uint64_t pe,
907 uint64_t addr, unsigned count,
908 uint32_t incr, uint32_t flags)
909{
910 uint64_t value;
911 unsigned ndw;
912
913 while (count) {
914 ndw = count;
915 if (ndw > 0x7FFFF)
916 ndw = 0x7FFFF;
917
918 if (flags & AMDGPU_PTE_VALID)
919 value = addr;
920 else
921 value = 0;
922
923 /* for physically contiguous pages (vram) */
924 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
925 ib->ptr[ib->length_dw++] = pe; /* dst addr */
926 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
927 ib->ptr[ib->length_dw++] = flags; /* mask */
928 ib->ptr[ib->length_dw++] = 0;
929 ib->ptr[ib->length_dw++] = value; /* value */
930 ib->ptr[ib->length_dw++] = upper_32_bits(value);
931 ib->ptr[ib->length_dw++] = incr; /* increment size */
932 ib->ptr[ib->length_dw++] = 0;
933 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
934
935 pe += ndw * 8;
936 addr += ndw * incr;
937 count -= ndw;
938 }
939}
940
941/**
942 * sdma_v3_0_vm_pad_ib - pad the IB to the required number of dw
943 *
944 * @ib: indirect buffer to fill with padding
945 *
946 */
947static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib)
948{
949 while (ib->length_dw & 0x7)
950 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
951}
952
953/**
954 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
955 *
956 * @ring: amdgpu_ring pointer
957 * @vm: amdgpu_vm pointer
958 *
959 * Update the page table base and flush the VM TLB
960 * using sDMA (VI).
961 */
962static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
963 unsigned vm_id, uint64_t pd_addr)
964{
965 u32 srbm_gfx_cntl = 0;
966
967 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
968 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
969 if (vm_id < 8) {
970 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
971 } else {
972 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
973 }
974 amdgpu_ring_write(ring, pd_addr >> 12);
975
976 /* update SH_MEM_* regs */
977 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id);
978 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
979 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
980 amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
981 amdgpu_ring_write(ring, srbm_gfx_cntl);
982
983 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
984 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
985 amdgpu_ring_write(ring, mmSH_MEM_BASES);
986 amdgpu_ring_write(ring, 0);
987
988 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
989 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
990 amdgpu_ring_write(ring, mmSH_MEM_CONFIG);
991 amdgpu_ring_write(ring, 0);
992
993 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
994 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
995 amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE);
996 amdgpu_ring_write(ring, 1);
997
998 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
999 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1000 amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT);
1001 amdgpu_ring_write(ring, 0);
1002
1003 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0);
1004 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1005 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1006 amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
1007 amdgpu_ring_write(ring, srbm_gfx_cntl);
1008
1009
1010 /* flush TLB */
1011 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1012 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1013 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1014 amdgpu_ring_write(ring, 1 << vm_id);
1015
1016 /* wait for flush */
1017 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1018 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1019 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1020 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1021 amdgpu_ring_write(ring, 0);
1022 amdgpu_ring_write(ring, 0); /* reference */
1023 amdgpu_ring_write(ring, 0); /* mask */
1024 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1025 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1026}
1027
1028static int sdma_v3_0_early_init(struct amdgpu_device *adev)
1029{
1030 sdma_v3_0_set_ring_funcs(adev);
1031 sdma_v3_0_set_buffer_funcs(adev);
1032 sdma_v3_0_set_vm_pte_funcs(adev);
1033 sdma_v3_0_set_irq_funcs(adev);
1034
1035 return 0;
1036}
1037
1038static int sdma_v3_0_sw_init(struct amdgpu_device *adev)
1039{
1040 struct amdgpu_ring *ring;
1041 int r;
1042
1043 /* SDMA trap event */
1044 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
1045 if (r)
1046 return r;
1047
1048 /* SDMA Privileged inst */
1049 r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
1050 if (r)
1051 return r;
1052
1053 /* SDMA Privileged inst */
1054 r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
1055 if (r)
1056 return r;
1057
1058 r = sdma_v3_0_init_microcode(adev);
1059 if (r) {
1060 DRM_ERROR("Failed to load sdma firmware!\n");
1061 return r;
1062 }
1063
1064 ring = &adev->sdma[0].ring;
1065 ring->ring_obj = NULL;
1066 ring->use_doorbell = true;
1067 ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE0;
1068
1069 ring = &adev->sdma[1].ring;
1070 ring->ring_obj = NULL;
1071 ring->use_doorbell = true;
1072 ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE1;
1073
1074 ring = &adev->sdma[0].ring;
1075 sprintf(ring->name, "sdma0");
1076 r = amdgpu_ring_init(adev, ring, 256 * 1024,
1077 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1078 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
1079 AMDGPU_RING_TYPE_SDMA);
1080 if (r)
1081 return r;
1082
1083 ring = &adev->sdma[1].ring;
1084 sprintf(ring->name, "sdma1");
1085 r = amdgpu_ring_init(adev, ring, 256 * 1024,
1086 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1087 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
1088 AMDGPU_RING_TYPE_SDMA);
1089 if (r)
1090 return r;
1091
1092 return r;
1093}
1094
1095static int sdma_v3_0_sw_fini(struct amdgpu_device *adev)
1096{
1097 amdgpu_ring_fini(&adev->sdma[0].ring);
1098 amdgpu_ring_fini(&adev->sdma[1].ring);
1099
1100 return 0;
1101}
1102
1103static int sdma_v3_0_hw_init(struct amdgpu_device *adev)
1104{
1105 int r;
1106
1107 sdma_v3_0_init_golden_registers(adev);
1108
1109 r = sdma_v3_0_start(adev);
1110 if (r)
1111 return r;
1112
1113 return r;
1114}
1115
1116static int sdma_v3_0_hw_fini(struct amdgpu_device *adev)
1117{
1118 sdma_v3_0_enable(adev, false);
1119
1120 return 0;
1121}
1122
1123static int sdma_v3_0_suspend(struct amdgpu_device *adev)
1124{
1125
1126 return sdma_v3_0_hw_fini(adev);
1127}
1128
1129static int sdma_v3_0_resume(struct amdgpu_device *adev)
1130{
1131
1132 return sdma_v3_0_hw_init(adev);
1133}
1134
1135static bool sdma_v3_0_is_idle(struct amdgpu_device *adev)
1136{
1137 u32 tmp = RREG32(mmSRBM_STATUS2);
1138
1139 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1140 SRBM_STATUS2__SDMA1_BUSY_MASK))
1141 return false;
1142
1143 return true;
1144}
1145
1146static int sdma_v3_0_wait_for_idle(struct amdgpu_device *adev)
1147{
1148 unsigned i;
1149 u32 tmp;
1150
1151 for (i = 0; i < adev->usec_timeout; i++) {
1152 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1153 SRBM_STATUS2__SDMA1_BUSY_MASK);
1154
1155 if (!tmp)
1156 return 0;
1157 udelay(1);
1158 }
1159 return -ETIMEDOUT;
1160}
1161
1162static void sdma_v3_0_print_status(struct amdgpu_device *adev)
1163{
1164 int i, j;
1165
1166 dev_info(adev->dev, "VI SDMA registers\n");
1167 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1168 RREG32(mmSRBM_STATUS2));
1169 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
1170 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1171 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1172 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n",
1173 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1174 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1175 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1176 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1177 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1178 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1179 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1180 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1181 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1182 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1183 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1184 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1185 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1186 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1187 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1188 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1189 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1190 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1191 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1192 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1193 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1194 dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n",
1195 i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]));
1196 mutex_lock(&adev->srbm_mutex);
1197 for (j = 0; j < 16; j++) {
1198 vi_srbm_select(adev, 0, 0, 0, j);
1199 dev_info(adev->dev, " VM %d:\n", j);
1200 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1201 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1202 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1203 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1204 }
1205 vi_srbm_select(adev, 0, 0, 0, 0);
1206 mutex_unlock(&adev->srbm_mutex);
1207 }
1208}
1209
1210static int sdma_v3_0_soft_reset(struct amdgpu_device *adev)
1211{
1212 u32 srbm_soft_reset = 0;
1213 u32 tmp = RREG32(mmSRBM_STATUS2);
1214
1215 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1216 /* sdma0 */
1217 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1218 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1219 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1220 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1221 }
1222 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1223 /* sdma1 */
1224 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1225 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1226 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1227 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1228 }
1229
1230 if (srbm_soft_reset) {
1231 sdma_v3_0_print_status(adev);
1232
1233 tmp = RREG32(mmSRBM_SOFT_RESET);
1234 tmp |= srbm_soft_reset;
1235 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1236 WREG32(mmSRBM_SOFT_RESET, tmp);
1237 tmp = RREG32(mmSRBM_SOFT_RESET);
1238
1239 udelay(50);
1240
1241 tmp &= ~srbm_soft_reset;
1242 WREG32(mmSRBM_SOFT_RESET, tmp);
1243 tmp = RREG32(mmSRBM_SOFT_RESET);
1244
1245 /* Wait a little for things to settle down */
1246 udelay(50);
1247
1248 sdma_v3_0_print_status(adev);
1249 }
1250
1251 return 0;
1252}
1253
1254static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1255 struct amdgpu_irq_src *source,
1256 unsigned type,
1257 enum amdgpu_interrupt_state state)
1258{
1259 u32 sdma_cntl;
1260
1261 switch (type) {
1262 case AMDGPU_SDMA_IRQ_TRAP0:
1263 switch (state) {
1264 case AMDGPU_IRQ_STATE_DISABLE:
1265 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1266 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1267 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1268 break;
1269 case AMDGPU_IRQ_STATE_ENABLE:
1270 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1271 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1272 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1273 break;
1274 default:
1275 break;
1276 }
1277 break;
1278 case AMDGPU_SDMA_IRQ_TRAP1:
1279 switch (state) {
1280 case AMDGPU_IRQ_STATE_DISABLE:
1281 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1282 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1283 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1284 break;
1285 case AMDGPU_IRQ_STATE_ENABLE:
1286 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1287 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1288 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1289 break;
1290 default:
1291 break;
1292 }
1293 break;
1294 default:
1295 break;
1296 }
1297 return 0;
1298}
1299
1300static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1301 struct amdgpu_irq_src *source,
1302 struct amdgpu_iv_entry *entry)
1303{
1304 u8 instance_id, queue_id;
1305
1306 instance_id = (entry->ring_id & 0x3) >> 0;
1307 queue_id = (entry->ring_id & 0xc) >> 2;
1308 DRM_DEBUG("IH: SDMA trap\n");
1309 switch (instance_id) {
1310 case 0:
1311 switch (queue_id) {
1312 case 0:
1313 amdgpu_fence_process(&adev->sdma[0].ring);
1314 break;
1315 case 1:
1316 /* XXX compute */
1317 break;
1318 case 2:
1319 /* XXX compute */
1320 break;
1321 }
1322 break;
1323 case 1:
1324 switch (queue_id) {
1325 case 0:
1326 amdgpu_fence_process(&adev->sdma[1].ring);
1327 break;
1328 case 1:
1329 /* XXX compute */
1330 break;
1331 case 2:
1332 /* XXX compute */
1333 break;
1334 }
1335 break;
1336 }
1337 return 0;
1338}
1339
1340static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1341 struct amdgpu_irq_src *source,
1342 struct amdgpu_iv_entry *entry)
1343{
1344 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1345 schedule_work(&adev->reset_work);
1346 return 0;
1347}
1348
1349static int sdma_v3_0_set_clockgating_state(struct amdgpu_device *adev,
1350 enum amdgpu_clockgating_state state)
1351{
1352 /* XXX handled via the smc on VI */
1353
1354 return 0;
1355}
1356
1357static int sdma_v3_0_set_powergating_state(struct amdgpu_device *adev,
1358 enum amdgpu_powergating_state state)
1359{
1360 return 0;
1361}
1362
1363const struct amdgpu_ip_funcs sdma_v3_0_ip_funcs = {
1364 .early_init = sdma_v3_0_early_init,
1365 .late_init = NULL,
1366 .sw_init = sdma_v3_0_sw_init,
1367 .sw_fini = sdma_v3_0_sw_fini,
1368 .hw_init = sdma_v3_0_hw_init,
1369 .hw_fini = sdma_v3_0_hw_fini,
1370 .suspend = sdma_v3_0_suspend,
1371 .resume = sdma_v3_0_resume,
1372 .is_idle = sdma_v3_0_is_idle,
1373 .wait_for_idle = sdma_v3_0_wait_for_idle,
1374 .soft_reset = sdma_v3_0_soft_reset,
1375 .print_status = sdma_v3_0_print_status,
1376 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1377 .set_powergating_state = sdma_v3_0_set_powergating_state,
1378};
1379
1380/**
1381 * sdma_v3_0_ring_is_lockup - Check if the DMA engine is locked up
1382 *
1383 * @ring: amdgpu_ring structure holding ring information
1384 *
1385 * Check if the async DMA engine is locked up (VI).
1386 * Returns true if the engine appears to be locked up, false if not.
1387 */
1388static bool sdma_v3_0_ring_is_lockup(struct amdgpu_ring *ring)
1389{
1390
1391 if (sdma_v3_0_is_idle(ring->adev)) {
1392 amdgpu_ring_lockup_update(ring);
1393 return false;
1394 }
1395 return amdgpu_ring_test_lockup(ring);
1396}
1397
1398static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1399 .get_rptr = sdma_v3_0_ring_get_rptr,
1400 .get_wptr = sdma_v3_0_ring_get_wptr,
1401 .set_wptr = sdma_v3_0_ring_set_wptr,
1402 .parse_cs = NULL,
1403 .emit_ib = sdma_v3_0_ring_emit_ib,
1404 .emit_fence = sdma_v3_0_ring_emit_fence,
1405 .emit_semaphore = sdma_v3_0_ring_emit_semaphore,
1406 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1407 .test_ring = sdma_v3_0_ring_test_ring,
1408 .test_ib = sdma_v3_0_ring_test_ib,
1409 .is_lockup = sdma_v3_0_ring_is_lockup,
1410};
1411
1412static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1413{
1414 adev->sdma[0].ring.funcs = &sdma_v3_0_ring_funcs;
1415 adev->sdma[1].ring.funcs = &sdma_v3_0_ring_funcs;
1416}
1417
1418static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1419 .set = sdma_v3_0_set_trap_irq_state,
1420 .process = sdma_v3_0_process_trap_irq,
1421};
1422
1423static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1424 .process = sdma_v3_0_process_illegal_inst_irq,
1425};
1426
1427static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1428{
1429 adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1430 adev->sdma_trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1431 adev->sdma_illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1432}
1433
1434/**
1435 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1436 *
1437 * @ring: amdgpu_ring structure holding ring information
1438 * @src_offset: src GPU address
1439 * @dst_offset: dst GPU address
1440 * @byte_count: number of bytes to xfer
1441 *
1442 * Copy GPU buffers using the DMA engine (VI).
1443 * Used by the amdgpu ttm implementation to move pages if
1444 * registered as the asic copy callback.
1445 */
1446static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ring *ring,
1447 uint64_t src_offset,
1448 uint64_t dst_offset,
1449 uint32_t byte_count)
1450{
1451 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1452 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR));
1453 amdgpu_ring_write(ring, byte_count);
1454 amdgpu_ring_write(ring, 0); /* src/dst endian swap */
1455 amdgpu_ring_write(ring, lower_32_bits(src_offset));
1456 amdgpu_ring_write(ring, upper_32_bits(src_offset));
1457 amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1458 amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1459}
1460
1461/**
1462 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1463 *
1464 * @ring: amdgpu_ring structure holding ring information
1465 * @src_data: value to write to buffer
1466 * @dst_offset: dst GPU address
1467 * @byte_count: number of bytes to xfer
1468 *
1469 * Fill GPU buffers using the DMA engine (VI).
1470 */
1471static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ring *ring,
1472 uint32_t src_data,
1473 uint64_t dst_offset,
1474 uint32_t byte_count)
1475{
1476 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL));
1477 amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1478 amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1479 amdgpu_ring_write(ring, src_data);
1480 amdgpu_ring_write(ring, byte_count);
1481}
1482
1483static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1484 .copy_max_bytes = 0x1fffff,
1485 .copy_num_dw = 7,
1486 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1487
1488 .fill_max_bytes = 0x1fffff,
1489 .fill_num_dw = 5,
1490 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1491};
1492
1493static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1494{
1495 if (adev->mman.buffer_funcs == NULL) {
1496 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1497 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
1498 }
1499}
1500
1501static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1502 .copy_pte = sdma_v3_0_vm_copy_pte,
1503 .write_pte = sdma_v3_0_vm_write_pte,
1504 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1505 .pad_ib = sdma_v3_0_vm_pad_ib,
1506};
1507
1508static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1509{
1510 if (adev->vm_manager.vm_pte_funcs == NULL) {
1511 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1512 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
1513 }
1514}
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-27 00:12:11 -0400