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path: root/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c14
1 files changed, 6 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index aa9ab299fd32..99616dd9594f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -365,9 +365,7 @@ static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
365 /* XXX check if swapping is necessary on BE */ 365 /* XXX check if swapping is necessary on BE */
366 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; 366 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
367 } else { 367 } else {
368 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 368 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
369
370 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
371 } 369 }
372 370
373 return wptr; 371 return wptr;
@@ -394,9 +392,7 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
394 392
395 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); 393 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
396 } else { 394 } else {
397 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 395 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
398
399 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
400 } 396 }
401} 397}
402 398
@@ -450,7 +446,7 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
450{ 446{
451 u32 ref_and_mask = 0; 447 u32 ref_and_mask = 0;
452 448
453 if (ring == &ring->adev->sdma.instance[0].ring) 449 if (ring->me == 0)
454 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 450 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
455 else 451 else
456 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 452 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
@@ -1655,8 +1651,10 @@ static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1655{ 1651{
1656 int i; 1652 int i;
1657 1653
1658 for (i = 0; i < adev->sdma.num_instances; i++) 1654 for (i = 0; i < adev->sdma.num_instances; i++) {
1659 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1655 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1656 adev->sdma.instance[i].ring.me = i;
1657 }
1660} 1658}
1661 1659
1662static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1660static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {