diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 27 |
1 files changed, 18 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index b4906d2f30d3..ad9054e3903c 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | |||
@@ -22,11 +22,11 @@ | |||
22 | */ | 22 | */ |
23 | 23 | ||
24 | #include "amdgpu.h" | 24 | #include "amdgpu.h" |
25 | #include "vega10/soc15ip.h" | 25 | #include "soc15ip.h" |
26 | #include "vega10/NBIO/nbio_6_1_offset.h" | 26 | #include "nbio/nbio_6_1_offset.h" |
27 | #include "vega10/NBIO/nbio_6_1_sh_mask.h" | 27 | #include "nbio/nbio_6_1_sh_mask.h" |
28 | #include "vega10/GC/gc_9_0_offset.h" | 28 | #include "gc/gc_9_0_offset.h" |
29 | #include "vega10/GC/gc_9_0_sh_mask.h" | 29 | #include "gc/gc_9_0_sh_mask.h" |
30 | #include "soc15.h" | 30 | #include "soc15.h" |
31 | #include "vega10_ih.h" | 31 | #include "vega10_ih.h" |
32 | #include "soc15_common.h" | 32 | #include "soc15_common.h" |
@@ -254,7 +254,7 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work) | |||
254 | } | 254 | } |
255 | 255 | ||
256 | /* Trigger recovery due to world switch failure */ | 256 | /* Trigger recovery due to world switch failure */ |
257 | amdgpu_sriov_gpu_reset(adev, NULL); | 257 | amdgpu_gpu_recover(adev, NULL); |
258 | } | 258 | } |
259 | 259 | ||
260 | static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev, | 260 | static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev, |
@@ -282,9 +282,17 @@ static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev, | |||
282 | /* see what event we get */ | 282 | /* see what event we get */ |
283 | r = xgpu_ai_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION); | 283 | r = xgpu_ai_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION); |
284 | 284 | ||
285 | /* only handle FLR_NOTIFY now */ | 285 | /* sometimes the interrupt is delayed to inject to VM, so under such case |
286 | if (!r) | 286 | * the IDH_FLR_NOTIFICATION is overwritten by VF FLR from GIM side, thus |
287 | schedule_work(&adev->virt.flr_work); | 287 | * above recieve message could be failed, we should schedule the flr_work |
288 | * anyway | ||
289 | */ | ||
290 | if (r) { | ||
291 | DRM_ERROR("FLR_NOTIFICATION is missed\n"); | ||
292 | xgpu_ai_mailbox_send_ack(adev); | ||
293 | } | ||
294 | |||
295 | schedule_work(&adev->virt.flr_work); | ||
288 | } | 296 | } |
289 | 297 | ||
290 | return 0; | 298 | return 0; |
@@ -353,5 +361,6 @@ const struct amdgpu_virt_ops xgpu_ai_virt_ops = { | |||
353 | .req_full_gpu = xgpu_ai_request_full_gpu_access, | 361 | .req_full_gpu = xgpu_ai_request_full_gpu_access, |
354 | .rel_full_gpu = xgpu_ai_release_full_gpu_access, | 362 | .rel_full_gpu = xgpu_ai_release_full_gpu_access, |
355 | .reset_gpu = xgpu_ai_request_reset, | 363 | .reset_gpu = xgpu_ai_request_reset, |
364 | .wait_reset = NULL, | ||
356 | .trans_msg = xgpu_ai_mailbox_trans_msg, | 365 | .trans_msg = xgpu_ai_mailbox_trans_msg, |
357 | }; | 366 | }; |