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path: root/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 6c8040e616c4..4f2788b61a08 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -124,7 +124,7 @@ static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
124 124
125static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 125static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
126{ 126{
127 uint32_t tmp; 127 uint32_t tmp, field;
128 128
129 /* Setup L2 cache */ 129 /* Setup L2 cache */
130 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); 130 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
@@ -143,8 +143,9 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
143 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 143 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
144 WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp); 144 WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
145 145
146 field = adev->vm_manager.fragment_size;
146 tmp = mmVM_L2_CNTL3_DEFAULT; 147 tmp = mmVM_L2_CNTL3_DEFAULT;
147 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 149 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
149 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp); 150 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
150 151