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path: root/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c30
1 files changed, 18 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7abefb80f93d..ae720851974f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1147,7 +1147,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
1147 if (r) { 1147 if (r) {
1148 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n", 1148 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
1149 r); 1149 r);
1150 gfx_v9_0_rlc_fini(adev); 1150 adev->gfx.rlc.funcs->fini(adev);
1151 return r; 1151 return r;
1152 } 1152 }
1153 /* set up the cs buffer */ 1153 /* set up the cs buffer */
@@ -1169,7 +1169,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
1169 if (r) { 1169 if (r) {
1170 dev_err(adev->dev, 1170 dev_err(adev->dev,
1171 "(%d) failed to create cp table bo\n", r); 1171 "(%d) failed to create cp table bo\n", r);
1172 gfx_v9_0_rlc_fini(adev); 1172 adev->gfx.rlc.funcs->fini(adev);
1173 return r; 1173 return r;
1174 } 1174 }
1175 1175
@@ -1733,7 +1733,7 @@ static int gfx_v9_0_sw_init(void *handle)
1733 return r; 1733 return r;
1734 } 1734 }
1735 1735
1736 r = gfx_v9_0_rlc_init(adev); 1736 r = adev->gfx.rlc.funcs->init(adev);
1737 if (r) { 1737 if (r) {
1738 DRM_ERROR("Failed to init rlc BOs!\n"); 1738 DRM_ERROR("Failed to init rlc BOs!\n");
1739 return r; 1739 return r;
@@ -2483,12 +2483,12 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2483 return 0; 2483 return 0;
2484 } 2484 }
2485 2485
2486 gfx_v9_0_rlc_stop(adev); 2486 adev->gfx.rlc.funcs->stop(adev);
2487 2487
2488 /* disable CG */ 2488 /* disable CG */
2489 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 2489 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2490 2490
2491 gfx_v9_0_rlc_reset(adev); 2491 adev->gfx.rlc.funcs->reset(adev);
2492 2492
2493 gfx_v9_0_init_pg(adev); 2493 gfx_v9_0_init_pg(adev);
2494 2494
@@ -2521,7 +2521,7 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2521 gfx_v9_0_enable_lbpw(adev, false); 2521 gfx_v9_0_enable_lbpw(adev, false);
2522 } 2522 }
2523 2523
2524 gfx_v9_0_rlc_start(adev); 2524 adev->gfx.rlc.funcs->start(adev);
2525 2525
2526 return 0; 2526 return 0;
2527} 2527}
@@ -3344,7 +3344,7 @@ static int gfx_v9_0_hw_init(void *handle)
3344 if (r) 3344 if (r)
3345 return r; 3345 return r;
3346 3346
3347 r = gfx_v9_0_rlc_resume(adev); 3347 r = adev->gfx.rlc.funcs->resume(adev);
3348 if (r) 3348 if (r)
3349 return r; 3349 return r;
3350 3350
@@ -3424,7 +3424,7 @@ static int gfx_v9_0_hw_fini(void *handle)
3424 } 3424 }
3425 3425
3426 gfx_v9_0_cp_enable(adev, false); 3426 gfx_v9_0_cp_enable(adev, false);
3427 gfx_v9_0_rlc_stop(adev); 3427 adev->gfx.rlc.funcs->stop(adev);
3428 3428
3429 gfx_v9_0_csb_vram_unpin(adev); 3429 gfx_v9_0_csb_vram_unpin(adev);
3430 3430
@@ -3499,7 +3499,7 @@ static int gfx_v9_0_soft_reset(void *handle)
3499 3499
3500 if (grbm_soft_reset) { 3500 if (grbm_soft_reset) {
3501 /* stop the rlc */ 3501 /* stop the rlc */
3502 gfx_v9_0_rlc_stop(adev); 3502 adev->gfx.rlc.funcs->stop(adev);
3503 3503
3504 /* Disable GFX parsing/prefetching */ 3504 /* Disable GFX parsing/prefetching */
3505 gfx_v9_0_cp_gfx_enable(adev, false); 3505 gfx_v9_0_cp_gfx_enable(adev, false);
@@ -3655,7 +3655,7 @@ static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3655static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 3655static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3656 bool enable) 3656 bool enable)
3657{ 3657{
3658 gfx_v9_0_enter_rlc_safe_mode(adev); 3658 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3659 3659
3660 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 3660 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3661 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 3661 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
@@ -3666,7 +3666,7 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3666 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 3666 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3667 } 3667 }
3668 3668
3669 gfx_v9_0_exit_rlc_safe_mode(adev); 3669 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3670} 3670}
3671 3671
3672static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 3672static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
@@ -3882,7 +3882,13 @@ static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3882 3882
3883static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 3883static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3884 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode, 3884 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3885 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode 3885 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode,
3886 .init = gfx_v9_0_rlc_init,
3887 .fini = gfx_v9_0_rlc_fini,
3888 .resume = gfx_v9_0_rlc_resume,
3889 .stop = gfx_v9_0_rlc_stop,
3890 .reset = gfx_v9_0_rlc_reset,
3891 .start = gfx_v9_0_rlc_start
3886}; 3892};
3887 3893
3888static int gfx_v9_0_set_powergating_state(void *handle, 3894static int gfx_v9_0_set_powergating_state(void *handle,