1 files changed, 52 insertions, 269 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 2aeef2bb93a4..3d0f277a6523 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1173,64 +1173,61 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
                 }
         }
 
-        if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
-                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
-                info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
-                info->fw = adev->gfx.pfp_fw;
-                header = (const struct common_firmware_header *)info->fw->data;
-                adev->firmware.fw_size +=
-                        ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
-
-                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
-                info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
-                info->fw = adev->gfx.me_fw;
-                header = (const struct common_firmware_header *)info->fw->data;
-                adev->firmware.fw_size +=
-                        ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
-
-                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
-                info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
-                info->fw = adev->gfx.ce_fw;
-                header = (const struct common_firmware_header *)info->fw->data;
-                adev->firmware.fw_size +=
-                        ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+        info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
+        info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
+        info->fw = adev->gfx.pfp_fw;
+        header = (const struct common_firmware_header *)info->fw->data;
+        adev->firmware.fw_size +=
+                ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
+        info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
+        info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
+        info->fw = adev->gfx.me_fw;
+        header = (const struct common_firmware_header *)info->fw->data;
+        adev->firmware.fw_size +=
+                ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
+        info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
+        info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
+        info->fw = adev->gfx.ce_fw;
+        header = (const struct common_firmware_header *)info->fw->data;
+        adev->firmware.fw_size +=
+                ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
+        info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
+        info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
+        info->fw = adev->gfx.rlc_fw;
+        header = (const struct common_firmware_header *)info->fw->data;
+        adev->firmware.fw_size +=
+                ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
+        info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
+        info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
+        info->fw = adev->gfx.mec_fw;
+        header = (const struct common_firmware_header *)info->fw->data;
+        adev->firmware.fw_size +=
+                ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
+        /* we need account JT in */
+        cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
+        adev->firmware.fw_size +=
+                ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
 
-                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
-                info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
-                info->fw = adev->gfx.rlc_fw;
-                header = (const struct common_firmware_header *)info->fw->data;
+        if (amdgpu_sriov_vf(adev)) {
+                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
+                info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
+                info->fw = adev->gfx.mec_fw;
                 adev->firmware.fw_size +=
-                        ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+                        ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE);
+        }
 
-                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
-                info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
-                info->fw = adev->gfx.mec_fw;
+        if (adev->gfx.mec2_fw) {
+                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
+                info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
+                info->fw = adev->gfx.mec2_fw;
                 header = (const struct common_firmware_header *)info->fw->data;
                 adev->firmware.fw_size +=
                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
-
-                /* we need account JT in */
-                cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
-                adev->firmware.fw_size +=
-                        ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
-
-                if (amdgpu_sriov_vf(adev)) {
-                        info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
-                        info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
-                        info->fw = adev->gfx.mec_fw;
-                        adev->firmware.fw_size +=
-                                ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE);
-                }
-
-                if (adev->gfx.mec2_fw) {
-                        info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
-                        info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
-                        info->fw = adev->gfx.mec2_fw;
-                        header = (const struct common_firmware_header *)info->fw->data;
-                        adev->firmware.fw_size +=
-                                ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
-                }
-
         }
 
 out:
@@ -2048,11 +2045,6 @@ static int gfx_v8_0_sw_init(void *handle)
         adev->gfx.mec.num_pipe_per_mec = 4;
         adev->gfx.mec.num_queue_per_pipe = 8;
 
-        /* KIQ event */
-        r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_INT_IB2, &adev->gfx.kiq.irq);
-        if (r)
-                return r;
-
         /* EOP Event */
         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
         if (r)
@@ -4181,45 +4173,11 @@ static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
         udelay(50);
 }
 
-static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
-{
-        const struct rlc_firmware_header_v2_0 *hdr;
-        const __le32 *fw_data;
-        unsigned i, fw_size;
-
-        if (!adev->gfx.rlc_fw)
-                return -EINVAL;
-
-        hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
-        amdgpu_ucode_print_rlc_hdr(&hdr->header);
-
-        fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
-                           le32_to_cpu(hdr->header.ucode_array_offset_bytes));
-        fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
-
-        WREG32(mmRLC_GPM_UCODE_ADDR, 0);
-        for (i = 0; i < fw_size; i++)
-                WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
-        WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
-
-        return 0;
-}
-
 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
 {
-        int r;
-
         gfx_v8_0_rlc_stop(adev);
         gfx_v8_0_rlc_reset(adev);
         gfx_v8_0_init_pg(adev);
-
-        if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
-                /* legacy rlc firmware loading */
-                r = gfx_v8_0_rlc_load_microcode(adev);
-                if (r)
-                        return r;
-        }
-
         gfx_v8_0_rlc_start(adev);
 
         return 0;
@@ -4245,63 +4203,6 @@ static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
         udelay(50);
 }
 
-static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
-{
-        const struct gfx_firmware_header_v1_0 *pfp_hdr;
-        const struct gfx_firmware_header_v1_0 *ce_hdr;
-        const struct gfx_firmware_header_v1_0 *me_hdr;
-        const __le32 *fw_data;
-        unsigned i, fw_size;
-
-        if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
-                return -EINVAL;
-
-        pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
-                adev->gfx.pfp_fw->data;
-        ce_hdr = (const struct gfx_firmware_header_v1_0 *)
-                adev->gfx.ce_fw->data;
-        me_hdr = (const struct gfx_firmware_header_v1_0 *)
-                adev->gfx.me_fw->data;
-
-        amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
-        amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
-        amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
-
-        gfx_v8_0_cp_gfx_enable(adev, false);
-
-        /* PFP */
-        fw_data = (const __le32 *)
-                (adev->gfx.pfp_fw->data +
-                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
-        fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
-        WREG32(mmCP_PFP_UCODE_ADDR, 0);
-        for (i = 0; i < fw_size; i++)
-                WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
-        WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
-
-        /* CE */
-        fw_data = (const __le32 *)
-                (adev->gfx.ce_fw->data +
-                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
-        fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
-        WREG32(mmCP_CE_UCODE_ADDR, 0);
-        for (i = 0; i < fw_size; i++)
-                WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
-        WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
-
-        /* ME */
-        fw_data = (const __le32 *)
-                (adev->gfx.me_fw->data +
-                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
-        fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
-        WREG32(mmCP_ME_RAM_WADDR, 0);
-        for (i = 0; i < fw_size; i++)
-                WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
-        WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
-
-        return 0;
-}
-
 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
 {
         u32 count = 0;
@@ -4501,52 +4402,6 @@ static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
         udelay(50);
 }
 
-static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
-{
-        const struct gfx_firmware_header_v1_0 *mec_hdr;
-        const __le32 *fw_data;
-        unsigned i, fw_size;
-
-        if (!adev->gfx.mec_fw)
-                return -EINVAL;
-
-        gfx_v8_0_cp_compute_enable(adev, false);
-
-        mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
-        amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
-
-        fw_data = (const __le32 *)
-                (adev->gfx.mec_fw->data +
-                 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
-        fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
-
-        /* MEC1 */
-        WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
-        for (i = 0; i < fw_size; i++)
-                WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
-        WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
-
-        /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
-        if (adev->gfx.mec2_fw) {
-                const struct gfx_firmware_header_v1_0 *mec2_hdr;
-
-                mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
-                amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
-
-                fw_data = (const __le32 *)
-                        (adev->gfx.mec2_fw->data +
-                         le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
-                fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
-
-                WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
-                for (i = 0; i < fw_size; i++)
-                        WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
-                WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
-        }
-
-        return 0;
-}
-
 /* KIQ functions */
 static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring)
 {
@@ -4872,7 +4727,7 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
         struct vi_mqd *mqd = ring->mqd_ptr;
         int mqd_idx = ring - &adev->gfx.compute_ring[0];
 
-        if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
+        if (!adev->in_gpu_reset && !adev->in_suspend) {
                 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
                 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
                 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
@@ -4980,17 +4835,6 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
         if (!(adev->flags & AMD_IS_APU))
                 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
 
-        if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
-                        /* legacy firmware loading */
-                r = gfx_v8_0_cp_gfx_load_microcode(adev);
-                if (r)
-                        return r;
-
-                r = gfx_v8_0_cp_compute_load_microcode(adev);
-                if (r)
-                        return r;
-        }
-
         r = gfx_v8_0_kiq_resume(adev);
         if (r)
                 return r;
@@ -5142,19 +4986,12 @@ static int gfx_v8_0_hw_fini(void *handle)
 
 static int gfx_v8_0_suspend(void *handle)
 {
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        adev->gfx.in_suspend = true;
-        return gfx_v8_0_hw_fini(adev);
+        return gfx_v8_0_hw_fini(handle);
 }
 
 static int gfx_v8_0_resume(void *handle)
 {
-        int r;
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        r = gfx_v8_0_hw_init(adev);
-        adev->gfx.in_suspend = false;
-        return r;
+        return gfx_v8_0_hw_init(handle);
 }
 
 static bool gfx_v8_0_check_soft_reset(void *handle)
@@ -7025,52 +6862,6 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
         return 0;
 }
 
-static int gfx_v8_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
-                                            struct amdgpu_irq_src *src,
-                                            unsigned int type,
-                                            enum amdgpu_interrupt_state state)
-{
-        struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
-
-        switch (type) {
-        case AMDGPU_CP_KIQ_IRQ_DRIVER0:
-                WREG32_FIELD(CPC_INT_CNTL, GENERIC2_INT_ENABLE,
-                             state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
-                if (ring->me == 1)
-                        WREG32_FIELD_OFFSET(CP_ME1_PIPE0_INT_CNTL,
-                                     ring->pipe,
-                                     GENERIC2_INT_ENABLE,
-                                     state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
-                else
-                        WREG32_FIELD_OFFSET(CP_ME2_PIPE0_INT_CNTL,
-                                     ring->pipe,
-                                     GENERIC2_INT_ENABLE,
-                                     state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
-                break;
-        default:
-                BUG(); /* kiq only support GENERIC2_INT now */
-                break;
-        }
-        return 0;
-}
-
-static int gfx_v8_0_kiq_irq(struct amdgpu_device *adev,
-                            struct amdgpu_irq_src *source,
-                            struct amdgpu_iv_entry *entry)
-{
-        u8 me_id, pipe_id, queue_id;
-        struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
-
-        me_id = (entry->ring_id & 0x0c) >> 2;
-        pipe_id = (entry->ring_id & 0x03) >> 0;
-        queue_id = (entry->ring_id & 0x70) >> 4;
-        DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
-                   me_id, pipe_id, queue_id);
-
-        amdgpu_fence_process(ring);
-        return 0;
-}
-
 static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
         .name = "gfx_v8_0",
         .early_init = gfx_v8_0_early_init,
@@ -7221,11 +7012,6 @@ static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
         .process = gfx_v8_0_priv_inst_irq,
 };
 
-static const struct amdgpu_irq_src_funcs gfx_v8_0_kiq_irq_funcs = {
-        .set = gfx_v8_0_kiq_set_interrupt_state,
-        .process = gfx_v8_0_kiq_irq,
-};
-
 static const struct amdgpu_irq_src_funcs gfx_v8_0_cp_ecc_error_irq_funcs = {
         .set = gfx_v8_0_set_cp_ecc_int_state,
         .process = gfx_v8_0_cp_ecc_error_irq,
@@ -7247,9 +7033,6 @@ static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
         adev->gfx.priv_inst_irq.num_types = 1;
         adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
 
-        adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
-        adev->gfx.kiq.irq.funcs = &gfx_v8_0_kiq_irq_funcs;
-
         adev->gfx.cp_ecc_error_irq.num_types = 1;
         adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs;