1 files changed, 29 insertions, 58 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index dfc10b1baea0..147e92b3a959 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4132,18 +4132,12 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
         gfx_v8_0_rlc_reset(adev);
         gfx_v8_0_init_pg(adev);
 
-        if (!adev->pp_enabled) {
-                if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
-                        /* legacy rlc firmware loading */
-                        r = gfx_v8_0_rlc_load_microcode(adev);
-                        if (r)
-                                return r;
-                } else {
-                        r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-                                                        AMDGPU_UCODE_ID_RLC_G);
-                        if (r)
-                                return -EINVAL;
-                }
+
+        if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
+                /* legacy rlc firmware loading */
+                r = gfx_v8_0_rlc_load_microcode(adev);
+                if (r)
+                        return r;
         }
 
         gfx_v8_0_rlc_start(adev);
@@ -4959,43 +4953,15 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
         if (!(adev->flags & AMD_IS_APU))
                 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
 
-        if (!adev->pp_enabled) {
-                if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
+        if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
                         /* legacy firmware loading */
-                        r = gfx_v8_0_cp_gfx_load_microcode(adev);
-                        if (r)
-                                return r;
+                r = gfx_v8_0_cp_gfx_load_microcode(adev);
+                if (r)
+                        return r;
 
-                        r = gfx_v8_0_cp_compute_load_microcode(adev);
-                        if (r)
-                                return r;
-                } else {
-                        r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-                                                        AMDGPU_UCODE_ID_CP_CE);
-                        if (r)
-                                return -EINVAL;
-
-                        r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-                                                        AMDGPU_UCODE_ID_CP_PFP);
-                        if (r)
-                                return -EINVAL;
-
-                        r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-                                                        AMDGPU_UCODE_ID_CP_ME);
-                        if (r)
-                                return -EINVAL;
-
-                        if (adev->asic_type == CHIP_TOPAZ) {
-                                r = gfx_v8_0_cp_compute_load_microcode(adev);
-                                if (r)
-                                        return r;
-                        } else {
-                                r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-                                                                                 AMDGPU_UCODE_ID_CP_MEC1);
-                                if (r)
-                                        return -EINVAL;
-                        }
-                }
+                r = gfx_v8_0_cp_compute_load_microcode(adev);
+                if (r)
+                        return r;
         }
 
         r = gfx_v8_0_cp_gfx_resume(adev);
@@ -6018,7 +5984,6 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
 {
         uint32_t msg_id, pp_state = 0;
         uint32_t pp_support_state = 0;
-        void *pp_handle = adev->powerplay.pp_handle;
 
         if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
@@ -6036,7 +6001,8 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
                                 PP_BLOCK_GFX_CG,
                                 pp_support_state,
                                 pp_state);
-                amd_set_clockgating_by_smu(pp_handle, msg_id);
+                if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                        amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
         }
 
         if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
@@ -6057,7 +6023,8 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
                                 PP_BLOCK_GFX_MG,
                                 pp_support_state,
                                 pp_state);
-                amd_set_clockgating_by_smu(pp_handle, msg_id);
+                if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                        amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
         }
 
         return 0;
@@ -6069,7 +6036,6 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
 
         uint32_t msg_id, pp_state = 0;
         uint32_t pp_support_state = 0;
-        void *pp_handle = adev->powerplay.pp_handle;
 
         if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
@@ -6087,7 +6053,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
                                 PP_BLOCK_GFX_CG,
                                 pp_support_state,
                                 pp_state);
-                amd_set_clockgating_by_smu(pp_handle, msg_id);
+                if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                        amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
         }
 
         if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
@@ -6106,7 +6073,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
                                 PP_BLOCK_GFX_3D,
                                 pp_support_state,
                                 pp_state);
-                amd_set_clockgating_by_smu(pp_handle, msg_id);
+                if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                        amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
         }
 
         if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
@@ -6127,7 +6095,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
                                 PP_BLOCK_GFX_MG,
                                 pp_support_state,
                                 pp_state);
-                amd_set_clockgating_by_smu(pp_handle, msg_id);
+                if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                        amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
         }
 
         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
@@ -6142,7 +6111,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
                                 PP_BLOCK_GFX_RLC,
                                 pp_support_state,
                                 pp_state);
-                amd_set_clockgating_by_smu(pp_handle, msg_id);
+                if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                        amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
         }
 
         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
@@ -6156,7 +6126,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
                         PP_BLOCK_GFX_CP,
                         pp_support_state,
                         pp_state);
-                amd_set_clockgating_by_smu(pp_handle, msg_id);
+                if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+                        amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
         }
 
         return 0;
@@ -7076,7 +7047,7 @@ static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
 {
         uint64_t ce_payload_addr;
         int cnt_ce;
-        static union {
+        union {
                 struct vi_ce_ib_state regular;
                 struct vi_ce_ib_state_chained_ib chained;
         } ce_payload = {};
@@ -7105,7 +7076,7 @@ static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring)
 {
         uint64_t de_payload_addr, gds_addr, csa_addr;
         int cnt_de;
-        static union {
+        union {
                 struct vi_de_ib_state regular;
                 struct vi_de_ib_state_chained_ib chained;
         } de_payload = {};