1 files changed, 161 insertions, 88 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 6324f67bdb1f..d0ec00986f38 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3949,8 +3949,12 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
         temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
         data = mmRLC_SRM_INDEX_CNTL_DATA_0;
         for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
-                amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false);
-                amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);
+                if (unique_indices[i] != 0) {
+                        amdgpu_mm_wreg(adev, temp + i,
+                                        unique_indices[i] & 0x3FFFF, false);
+                        amdgpu_mm_wreg(adev, data + i,
+                                        unique_indices[i] >> 20, false);
+                }
         }
         kfree(register_list_format);
 
@@ -3966,20 +3970,17 @@ static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
 {
         uint32_t data;
 
-        if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
-                              AMD_PG_SUPPORT_GFX_SMG |
-                              AMD_PG_SUPPORT_GFX_DMG)) {
-                WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
+        WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
 
-                data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
-                data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
-                data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
-                data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
-                WREG32(mmRLC_PG_DELAY, data);
+        data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
+        data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
+        data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
+        data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
+        WREG32(mmRLC_PG_DELAY, data);
+
+        WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
+        WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
 
-                WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
-                WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
-        }
 }
 
 static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
@@ -3996,41 +3997,37 @@ static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
 
 static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
 {
-        WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 1 : 0);
+        WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
 }
 
 static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
 {
-        if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
-                              AMD_PG_SUPPORT_GFX_SMG |
-                              AMD_PG_SUPPORT_GFX_DMG |
-                              AMD_PG_SUPPORT_CP |
-                              AMD_PG_SUPPORT_GDS |
-                              AMD_PG_SUPPORT_RLC_SMU_HS)) {
+        if ((adev->asic_type == CHIP_CARRIZO) ||
+            (adev->asic_type == CHIP_STONEY)) {
                 gfx_v8_0_init_csb(adev);
                 gfx_v8_0_init_save_restore_list(adev);
                 gfx_v8_0_enable_save_restore_machine(adev);
-
-                if ((adev->asic_type == CHIP_CARRIZO) ||
-                    (adev->asic_type == CHIP_STONEY)) {
-                        WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
-                        gfx_v8_0_init_power_gating(adev);
-                        WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
-                        if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
-                                cz_enable_sck_slow_down_on_power_up(adev, true);
-                                cz_enable_sck_slow_down_on_power_down(adev, true);
-                        } else {
-                                cz_enable_sck_slow_down_on_power_up(adev, false);
-                                cz_enable_sck_slow_down_on_power_down(adev, false);
-                        }
-                        if (adev->pg_flags & AMD_PG_SUPPORT_CP)
-                                cz_enable_cp_power_gating(adev, true);
-                        else
-                                cz_enable_cp_power_gating(adev, false);
-                } else if (adev->asic_type == CHIP_POLARIS11) {
-                        gfx_v8_0_init_power_gating(adev);
+                WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
+                gfx_v8_0_init_power_gating(adev);
+                WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
+                if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
+                        cz_enable_sck_slow_down_on_power_up(adev, true);
+                        cz_enable_sck_slow_down_on_power_down(adev, true);
+                } else {
+                        cz_enable_sck_slow_down_on_power_up(adev, false);
+                        cz_enable_sck_slow_down_on_power_down(adev, false);
                 }
+                if (adev->pg_flags & AMD_PG_SUPPORT_CP)
+                        cz_enable_cp_power_gating(adev, true);
+                else
+                        cz_enable_cp_power_gating(adev, false);
+        } else if (adev->asic_type == CHIP_POLARIS11) {
+                gfx_v8_0_init_csb(adev);
+                gfx_v8_0_init_save_restore_list(adev);
+                gfx_v8_0_enable_save_restore_machine(adev);
+                gfx_v8_0_init_power_gating(adev);
         }
+
 }
 
 static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
@@ -5339,14 +5336,11 @@ static int gfx_v8_0_set_powergating_state(void *handle,
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
 
-        if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
-                return 0;
-
         switch (adev->asic_type) {
         case CHIP_CARRIZO:
         case CHIP_STONEY:
-                if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
-                        cz_update_gfx_cg_power_gating(adev, enable);
+
+                cz_update_gfx_cg_power_gating(adev, enable);
 
                 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
                         gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
@@ -5791,25 +5785,49 @@ static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
                                           enum amd_clockgating_state state)
 {
-        uint32_t msg_id, pp_state;
+        uint32_t msg_id, pp_state = 0;
+        uint32_t pp_support_state = 0;
         void *pp_handle = adev->powerplay.pp_handle;
 
-        if (state == AMD_CG_STATE_UNGATE)
-                pp_state = 0;
-        else
-                pp_state = PP_STATE_CG | PP_STATE_LS;
+        if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
+                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
+                        pp_support_state = PP_STATE_SUPPORT_LS;
+                        pp_state = PP_STATE_LS;
+                }
+                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
+                        pp_support_state |= PP_STATE_SUPPORT_CG;
+                        pp_state |= PP_STATE_CG;
+                }
+                if (state == AMD_CG_STATE_UNGATE)
+                        pp_state = 0;
+
+                msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                                PP_BLOCK_GFX_CG,
+                                pp_support_state,
+                                pp_state);
+                amd_set_clockgating_by_smu(pp_handle, msg_id);
+        }
 
-        msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-                        PP_BLOCK_GFX_CG,
-                        PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                        pp_state);
-        amd_set_clockgating_by_smu(pp_handle, msg_id);
+        if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
+                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
+                        pp_support_state = PP_STATE_SUPPORT_LS;
+                        pp_state = PP_STATE_LS;
+                }
 
-        msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-                        PP_BLOCK_GFX_MG,
-                        PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                        pp_state);
-        amd_set_clockgating_by_smu(pp_handle, msg_id);
+                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
+                        pp_support_state |= PP_STATE_SUPPORT_CG;
+                        pp_state |= PP_STATE_CG;
+                }
+
+                if (state == AMD_CG_STATE_UNGATE)
+                        pp_state = 0;
+
+                msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                                PP_BLOCK_GFX_MG,
+                                pp_support_state,
+                                pp_state);
+                amd_set_clockgating_by_smu(pp_handle, msg_id);
+        }
 
         return 0;
 }
@@ -5817,43 +5835,98 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
 static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
                                           enum amd_clockgating_state state)
 {
-        uint32_t msg_id, pp_state;
+
+        uint32_t msg_id, pp_state = 0;
+        uint32_t pp_support_state = 0;
         void *pp_handle = adev->powerplay.pp_handle;
 
-        if (state == AMD_CG_STATE_UNGATE)
-                pp_state = 0;
-        else
-                pp_state = PP_STATE_CG | PP_STATE_LS;
+        if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
+                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
+                        pp_support_state = PP_STATE_SUPPORT_LS;
+                        pp_state = PP_STATE_LS;
+                }
+                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
+                        pp_support_state |= PP_STATE_SUPPORT_CG;
+                        pp_state |= PP_STATE_CG;
+                }
+                if (state == AMD_CG_STATE_UNGATE)
+                        pp_state = 0;
+
+                msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                                PP_BLOCK_GFX_CG,
+                                pp_support_state,
+                                pp_state);
+                amd_set_clockgating_by_smu(pp_handle, msg_id);
+        }
 
-        msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-                        PP_BLOCK_GFX_CG,
-                        PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                        pp_state);
-        amd_set_clockgating_by_smu(pp_handle, msg_id);
+        if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
+                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
+                        pp_support_state = PP_STATE_SUPPORT_LS;
+                        pp_state = PP_STATE_LS;
+                }
+                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
+                        pp_support_state |= PP_STATE_SUPPORT_CG;
+                        pp_state |= PP_STATE_CG;
+                }
+                if (state == AMD_CG_STATE_UNGATE)
+                        pp_state = 0;
+
+                msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                                PP_BLOCK_GFX_3D,
+                                pp_support_state,
+                                pp_state);
+                amd_set_clockgating_by_smu(pp_handle, msg_id);
+        }
 
-        msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-                        PP_BLOCK_GFX_3D,
-                        PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                        pp_state);
-        amd_set_clockgating_by_smu(pp_handle, msg_id);
+        if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
+                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
+                        pp_support_state = PP_STATE_SUPPORT_LS;
+                        pp_state = PP_STATE_LS;
+                }
 
-        msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-                        PP_BLOCK_GFX_MG,
-                        PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                        pp_state);
-        amd_set_clockgating_by_smu(pp_handle, msg_id);
+                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
+                        pp_support_state |= PP_STATE_SUPPORT_CG;
+                        pp_state |= PP_STATE_CG;
+                }
 
-        msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-                        PP_BLOCK_GFX_RLC,
-                        PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                        pp_state);
-        amd_set_clockgating_by_smu(pp_handle, msg_id);
+                if (state == AMD_CG_STATE_UNGATE)
+                        pp_state = 0;
+
+                msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                                PP_BLOCK_GFX_MG,
+                                pp_support_state,
+                                pp_state);
+                amd_set_clockgating_by_smu(pp_handle, msg_id);
+        }
+
+        if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
+                pp_support_state = PP_STATE_SUPPORT_LS;
 
-        msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                if (state == AMD_CG_STATE_UNGATE)
+                        pp_state = 0;
+                else
+                        pp_state = PP_STATE_LS;
+
+                msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                                PP_BLOCK_GFX_RLC,
+                                pp_support_state,
+                                pp_state);
+                amd_set_clockgating_by_smu(pp_handle, msg_id);
+        }
+
+        if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
+                pp_support_state = PP_STATE_SUPPORT_LS;
+
+                if (state == AMD_CG_STATE_UNGATE)
+                        pp_state = 0;
+                else
+                        pp_state = PP_STATE_LS;
+                msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
                         PP_BLOCK_GFX_CP,
-                        PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+                        pp_support_state,
                         pp_state);
-        amd_set_clockgating_by_smu(pp_handle, msg_id);
+                amd_set_clockgating_by_smu(pp_handle, msg_id);
+        }
 
         return 0;
 }