1 files changed, 29 insertions, 50 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 53f07439a512..cb4f68f53f24 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -868,7 +868,7 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
                 r = amdgpu_bo_create(adev,
                                      adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
                                      PAGE_SIZE, true,
-                                     AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
+                                     AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
                                      &adev->gfx.mec.hpd_eop_obj);
                 if (r) {
                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
@@ -940,12 +940,6 @@ static int gfx_v8_0_sw_init(void *handle)
                 return r;
         }
 
-        r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs);
-        if (r) {
-                DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r);
-                return r;
-        }
-
         /* set up the gfx ring */
         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
                 ring = &adev->gfx.gfx_ring[i];
@@ -995,21 +989,21 @@ static int gfx_v8_0_sw_init(void *handle)
         /* reserve GDS, GWS and OA resource for gfx */
         r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
                         PAGE_SIZE, true,
-                        AMDGPU_GEM_DOMAIN_GDS, 0,
+                        AMDGPU_GEM_DOMAIN_GDS, 0, NULL,
                         NULL, &adev->gds.gds_gfx_bo);
         if (r)
                 return r;
 
         r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
                 PAGE_SIZE, true,
-                AMDGPU_GEM_DOMAIN_GWS, 0,
+                AMDGPU_GEM_DOMAIN_GWS, 0, NULL,
                 NULL, &adev->gds.gws_gfx_bo);
         if (r)
                 return r;
 
         r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
                         PAGE_SIZE, true,
-                        AMDGPU_GEM_DOMAIN_OA, 0,
+                        AMDGPU_GEM_DOMAIN_OA, 0, NULL,
                         NULL, &adev->gds.oa_gfx_bo);
         if (r)
                 return r;
@@ -1033,8 +1027,6 @@ static int gfx_v8_0_sw_fini(void *handle)
         for (i = 0; i < adev->gfx.num_compute_rings; i++)
                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
 
-        amdgpu_wb_free(adev, adev->gfx.ce_sync_offs);
-
         gfx_v8_0_mec_fini(adev);
 
         return 0;
@@ -3106,7 +3098,7 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
                                              sizeof(struct vi_mqd),
                                              PAGE_SIZE, true,
                                              AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
-                                             &ring->mqd_obj);
+                                             NULL, &ring->mqd_obj);
                         if (r) {
                                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
                                 return r;
@@ -3965,6 +3957,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
                           DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
         amdgpu_ring_write(ring, lower_32_bits(seq));
         amdgpu_ring_write(ring, upper_32_bits(seq));
+
 }
 
 /**
@@ -4005,49 +3998,34 @@ static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
         return true;
 }
 
-static void gfx_v8_0_ce_sync_me(struct amdgpu_ring *ring)
+static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
+                                        unsigned vm_id, uint64_t pd_addr)
 {
-        struct amdgpu_device *adev = ring->adev;
-        u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4;
-
-        /* instruct DE to set a magic number */
-        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-        amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-                                                         WRITE_DATA_DST_SEL(5)));
-        amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
-        amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
-        amdgpu_ring_write(ring, 1);
+        int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
+        uint32_t seq = ring->fence_drv.sync_seq[ring->idx];
+        uint64_t addr = ring->fence_drv.gpu_addr;
 
-        /* let CE wait till condition satisfied */
         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
-        amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
-                                                         WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
-                                                         WAIT_REG_MEM_FUNCTION(3) |  /* == */
-                                                         WAIT_REG_MEM_ENGINE(2)));   /* ce */
-        amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
-        amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
-        amdgpu_ring_write(ring, 1);
+        amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
+                 WAIT_REG_MEM_FUNCTION(3))); /* equal */
+        amdgpu_ring_write(ring, addr & 0xfffffffc);
+        amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
+        amdgpu_ring_write(ring, seq);
         amdgpu_ring_write(ring, 0xffffffff);
         amdgpu_ring_write(ring, 4); /* poll interval */
 
-        /* instruct CE to reset wb of ce_sync to zero */
-        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-        amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
-                                                         WRITE_DATA_DST_SEL(5) |
-                                                         WR_CONFIRM));
-        amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
-        amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
-        amdgpu_ring_write(ring, 0);
-}
-
-static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                                        unsigned vm_id, uint64_t pd_addr)
-{
-        int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
+        if (usepfp) {
+                /* synce CE with ME to prevent CE fetch CEIB before context switch done */
+                amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
+                amdgpu_ring_write(ring, 0);
+                amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
+                amdgpu_ring_write(ring, 0);
+        }
 
         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
-                                 WRITE_DATA_DST_SEL(0)));
+                                 WRITE_DATA_DST_SEL(0)) |
+                                 WR_CONFIRM);
         if (vm_id < 8) {
                 amdgpu_ring_write(ring,
                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
@@ -4083,9 +4061,10 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
                 amdgpu_ring_write(ring, 0x0);
-
-                /* synce CE with ME to prevent CE fetch CEIB before context switch done */
-                gfx_v8_0_ce_sync_me(ring);
+                amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
+                amdgpu_ring_write(ring, 0);
+                amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
+                amdgpu_ring_write(ring, 0);
         }
 }