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path: root/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c137
1 files changed, 21 insertions, 116 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 05436b8730b4..0710b0b2e4b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1238,29 +1238,8 @@ static void cz_init_cp_jump_table(struct amdgpu_device *adev)
1238 1238
1239static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev) 1239static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev)
1240{ 1240{
1241 int r; 1241 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
1242 1242 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
1243 /* clear state block */
1244 if (adev->gfx.rlc.clear_state_obj) {
1245 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
1246 if (unlikely(r != 0))
1247 dev_warn(adev->dev, "(%d) reserve RLC cbs bo failed\n", r);
1248 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1249 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1250 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
1251 adev->gfx.rlc.clear_state_obj = NULL;
1252 }
1253
1254 /* jump table block */
1255 if (adev->gfx.rlc.cp_table_obj) {
1256 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, true);
1257 if (unlikely(r != 0))
1258 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
1259 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
1260 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
1261 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
1262 adev->gfx.rlc.cp_table_obj = NULL;
1263 }
1264} 1243}
1265 1244
1266static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) 1245static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
@@ -1278,39 +1257,17 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1278 /* clear state block */ 1257 /* clear state block */
1279 adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev); 1258 adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev);
1280 1259
1281 if (adev->gfx.rlc.clear_state_obj == NULL) { 1260 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
1282 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, 1261 AMDGPU_GEM_DOMAIN_VRAM,
1283 AMDGPU_GEM_DOMAIN_VRAM, 1262 &adev->gfx.rlc.clear_state_obj,
1284 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 1263 &adev->gfx.rlc.clear_state_gpu_addr,
1285 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 1264 (void **)&adev->gfx.rlc.cs_ptr);
1286 NULL, NULL,
1287 &adev->gfx.rlc.clear_state_obj);
1288 if (r) {
1289 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
1290 gfx_v8_0_rlc_fini(adev);
1291 return r;
1292 }
1293 }
1294 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1295 if (unlikely(r != 0)) {
1296 gfx_v8_0_rlc_fini(adev);
1297 return r;
1298 }
1299 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
1300 &adev->gfx.rlc.clear_state_gpu_addr);
1301 if (r) { 1265 if (r) {
1302 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 1266 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
1303 dev_warn(adev->dev, "(%d) pin RLC cbs bo failed\n", r);
1304 gfx_v8_0_rlc_fini(adev); 1267 gfx_v8_0_rlc_fini(adev);
1305 return r; 1268 return r;
1306 } 1269 }
1307 1270
1308 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
1309 if (r) {
1310 dev_warn(adev->dev, "(%d) map RLC cbs bo failed\n", r);
1311 gfx_v8_0_rlc_fini(adev);
1312 return r;
1313 }
1314 /* set up the cs buffer */ 1271 /* set up the cs buffer */
1315 dst_ptr = adev->gfx.rlc.cs_ptr; 1272 dst_ptr = adev->gfx.rlc.cs_ptr;
1316 gfx_v8_0_get_csb_buffer(adev, dst_ptr); 1273 gfx_v8_0_get_csb_buffer(adev, dst_ptr);
@@ -1321,34 +1278,13 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1321 if ((adev->asic_type == CHIP_CARRIZO) || 1278 if ((adev->asic_type == CHIP_CARRIZO) ||
1322 (adev->asic_type == CHIP_STONEY)) { 1279 (adev->asic_type == CHIP_STONEY)) {
1323 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 1280 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1324 if (adev->gfx.rlc.cp_table_obj == NULL) { 1281 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
1325 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true, 1282 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1326 AMDGPU_GEM_DOMAIN_VRAM, 1283 &adev->gfx.rlc.cp_table_obj,
1327 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 1284 &adev->gfx.rlc.cp_table_gpu_addr,
1328 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 1285 (void **)&adev->gfx.rlc.cp_table_ptr);
1329 NULL, NULL,
1330 &adev->gfx.rlc.cp_table_obj);
1331 if (r) {
1332 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
1333 return r;
1334 }
1335 }
1336
1337 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
1338 if (unlikely(r != 0)) {
1339 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
1340 return r;
1341 }
1342 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
1343 &adev->gfx.rlc.cp_table_gpu_addr);
1344 if (r) { 1286 if (r) {
1345 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 1287 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
1346 dev_warn(adev->dev, "(%d) pin RLC cp table bo failed\n", r);
1347 return r;
1348 }
1349 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
1350 if (r) {
1351 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
1352 return r; 1288 return r;
1353 } 1289 }
1354 1290
@@ -1363,17 +1299,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1363 1299
1364static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) 1300static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1365{ 1301{
1366 int r; 1302 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1367
1368 if (adev->gfx.mec.hpd_eop_obj) {
1369 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true);
1370 if (unlikely(r != 0))
1371 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
1372 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
1373 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1374 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
1375 adev->gfx.mec.hpd_eop_obj = NULL;
1376 }
1377} 1303}
1378 1304
1379static int gfx_v8_0_mec_init(struct amdgpu_device *adev) 1305static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
@@ -1389,34 +1315,13 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1389 1315
1390 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; 1316 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
1391 1317
1392 if (adev->gfx.mec.hpd_eop_obj == NULL) { 1318 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1393 r = amdgpu_bo_create(adev, 1319 AMDGPU_GEM_DOMAIN_GTT,
1394 mec_hpd_size, 1320 &adev->gfx.mec.hpd_eop_obj,
1395 PAGE_SIZE, true, 1321 &adev->gfx.mec.hpd_eop_gpu_addr,
1396 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 1322 (void **)&hpd);
1397 &adev->gfx.mec.hpd_eop_obj);
1398 if (r) {
1399 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1400 return r;
1401 }
1402 }
1403
1404 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
1405 if (unlikely(r != 0)) {
1406 gfx_v8_0_mec_fini(adev);
1407 return r;
1408 }
1409 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
1410 &adev->gfx.mec.hpd_eop_gpu_addr);
1411 if (r) {
1412 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
1413 gfx_v8_0_mec_fini(adev);
1414 return r;
1415 }
1416 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
1417 if (r) { 1323 if (r) {
1418 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); 1324 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1419 gfx_v8_0_mec_fini(adev);
1420 return r; 1325 return r;
1421 } 1326 }
1422 1327
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 13:15:20 -0400