1 files changed, 10 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 1675d5837c3c..32773b7523d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1441,6 +1441,15 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
         }
         nv_grbm_select(adev, 0, 0, 0, 0);
         mutex_unlock(&adev->srbm_mutex);
+
+        /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+           acccess. These should be enabled by FW for target VMIDs. */
+        for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
+                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
+                WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
+                WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
+        }
 }
 
 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
@@ -4611,6 +4620,7 @@ gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
                                             TIME_STAMP_INT_ENABLE, 0);
                 WREG32(cp_int_cntl_reg, cp_int_cntl);
+                break;
         case AMDGPU_IRQ_STATE_ENABLE:
                 cp_int_cntl = RREG32(cp_int_cntl_reg);
                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,